JPH06267271A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a delay time in a wiring in a chip in a semiconductor integrated circuit. CONSTITUTION:A memory cell array in the semiconductor integrated circuit is divided into plural pieces of blocks, and an output buffer circuit 140 and an output pad 150 for outputting the data in the memory cell array 120 in the block are provided on every block independently. Further, the semiconductor integrated circuit is provided with a decoding means decoding an address signal so as to read the data of one bit from every memory cell 120 in plural divided blocks. Further, the circuit is provided with an input buffer circuit 520 and input pads 540-541 for inputting a signal and a decoder circuit 530 decoding an address signal on every block independently. Thus, the delay time, etc., from the memory block to the output circuit are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a memory configuration with a reduced wiring delay time.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, in order to facilitate connection of a lead wire of a package to an input / output pad of the semiconductor integrated circuit, an input / output buffer means (input / output buffer means) is provided along an outer peripheral portion of the semiconductor integrated circuit. Circuits and I / O pads) were arranged.

A semiconductor integrated circuit 700 constituting the conventional semiconductor memory shown in FIG. 7 has an output bit width of 8 bits, and is composed of a memory block 71 composed of a memory cell array 720 and a read circuit 730.
0 to 717, decoder circuits 740 to 745, a common bus 750 for propagating the read signals from the memory blocks 710 to 717 to the output buffer circuit 760, output pads 780 to 787, an input buffer circuit 770,
Input pads 790-795 are included.

In the semiconductor integrated circuit having the above structure, the read signals from the memory blocks 710 to 717 arranged over the entire surface are output to the common bus 750 having the wiring extending from one end to the other in the semiconductor integrated circuit, and the chip outer peripheral portion is output. Was being propagated to. Although not shown in FIG. 7, the input buffer circuit 7
A long wiring extends from 70 to the decoder circuits 740 to 745. Therefore, in these conventional configurations, the delay time of the wiring within the chip is large, which is an obstacle to speeding up.

FIG. 8 is a diagram simply showing the decoding means of the semiconductor integrated circuit shown in FIG. In this example, the address signals 820 and 821 are decoded by the row decoder 830, the column decoder 831 and the block decoder 832 to become the row selection signal 840, the column selection signal 841 and the block selection signal 842, and the memory selected by the block selection signal 842. Memory cell 810 in cell array 720
~ 817 is selected by the row selection signal 840 and the column selection signal 841. The signal read from the selected memory cell is sent to the common bus 750 and the output circuit 76.
0 to reach the output pads 780 to 787, from where they are propagated out of the semiconductor device. That is, one of the eight memory cell arrays 720 is selected by the address signal, 8-bit data therein is selected, and is output from the output pads 780 to 787. Therefore, which memory cell array 720 has been read. Data output pad 7
A common bus 750 is provided over the entire length of the semiconductor device for output from 80-787. First, if one of the memory cell arrays is selected and 8-bit data is taken out from this memory cell array, it is not necessary to operate the remaining memory cell array, and it is easy to reduce power consumption. .

Note that, as a structure related to this kind of semiconductor integrated circuit, for example, Japanese Patent Laid-Open No. 3-123071, JP SSC, Digest, etc.
Of Technical Papers, Paragraphs 214-215
, 1992 (ISSCC, Digest of Technical
Papers, pp. 214-215, 1992).

Recently, for the purpose of reducing the delay time of wiring,
LOC with an input / output pad arranged in the center of a semiconductor integrated circuit
(Lead on chip) technology is drawing attention. However, the common bus 7 for connecting the memory blocks 710 to 717 is used.
Since it is 50, it has not been a fundamental measure for reducing the wiring delay time.

[0008]

According to the conventional circuit described above, the wiring from the memory block to the output buffer circuit (hereinafter referred to as the output circuit) and the input buffer circuit (hereinafter referred to as the input circuit) to each memory block. Wiring was long, and the delay time in the on-chip wiring was long. The delay time of the wiring has come to occupy a large part of the delay time of the critical path as the memory becomes finer and the chip size increases. In order to reduce the delay time of these wirings, conventionally, the wiring width has been widened to reduce the wiring resistance, and the input / output pad is arranged at the center of the semiconductor integrated circuit to shorten the wiring length in the chip to deal with the problem. However, there was a limit to these measures.

Japanese Unexamined Patent Publication (Kokai) No. 4-144276 also discloses a semiconductor device in which the wiring delay time is shortened. Also in this technique, the final output stage region is arranged in the chip outer peripheral region. It was

An object of the present invention is to reduce the delay time of wiring in a semiconductor integrated circuit.

[0011]

The above object is to provide an output buffer means for dividing a memory cell array into a plurality of memory blocks and independently outputting stored data in the memory blocks to each of the memory blocks. To be achieved.

The above object can be achieved by providing an input buffer unit for inputting a signal and a decoding unit for decoding an address signal independently in each of the memory blocks.

Further, the above object is to divide the memory cell array into memory blocks of the number corresponding to the output bit width, and to independently decode the input buffer means for inputting a signal and the address signal to each of the memory blocks. It is also achieved by including the decoding means and the output buffer means of (1) and outputting each 1-bit data from each memory block to make the data of a predetermined bit width as a whole.

[0014]

According to the above means, the memory cell array in the semiconductor integrated circuit is divided into a plurality of memory blocks, and each memory block and the input / output buffer means are arranged close to each other. Therefore, the chip from the memory block to the output buffer means is arranged. The internal wiring length and the internal wiring length from the input buffer means to the memory block are shortened. When the wiring length in the chip is shortened, the delay time of the wiring can be shortened.

Further, since the decoding means outputs each 1-bit data from each memory block to make the data of a predetermined bit width as a whole, the output buffer of the bit data output from each memory block is outputted. It suffices to connect the means, and it becomes unnecessary to connect the output buffer means to each memory block via the common bus.

That is, according to the above means, it is possible to suppress the delay time of the wiring occupying the critical path, which is a problem in advancing the miniaturization of the semiconductor integrated circuit and increasing the chip size.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. The same parts are denoted by the same reference symbols throughout the drawings to avoid duplication of description. FIG. 1 shows a first embodiment of the present invention. The illustrated semiconductor integrated circuit 100 includes eight memory blocks 1 each including a memory cell array 120.
10 to 117, a read circuit 130 arranged in each of the memory blocks 110 to 117 and reading data from the memory cell array 120, an output circuit 140 provided in each of the read circuits 130, and an output provided in each of the output circuits 140. Decoder circuits 160 to 1 arranged between the pad 150 and each memory cell array 120
65, an input circuit 170 arranged at the right end of the memory blocks 110 to 117 in the figure, and the input circuit 170
And input pads 180 to 185 connected to.

The semiconductor integrated circuit of this embodiment has a structure in which one output circuit 140 is provided in each of the memory blocks 110 to 117. This does not limit the present invention, and it is possible to provide a plurality of output circuits in each of the memory blocks, for example. For example, it is possible to provide an 8-bit output semiconductor memory by providing two output circuits in each of the four divided memory blocks. In these cases, the output bit width of the semiconductor memory is equal to the total number of output circuits provided in all memory blocks. Similarly to the case described above, the embodiments shown below do not limit the number of divisions of the memory block or the number of output circuits in the memory block.

In the semiconductor integrated circuit shown in FIG. 1, a semiconductor memory having an output bit width of 8 bits is taken as an example, and data of any one bit of the output bit width is divided into eight memory blocks 110 to 117. Each memory cell array 1
Consider the case of storing in 20. This memory block 1
The stored data of 10 to 117 is, for example, LS of output bits.
From the B side, the 0th bit is assigned to the memory block 110, the 1st bit is assigned to the memory block 111, and the 7th bit is assigned to the memory block 117. With such a configuration, each memory block 110-1
It is not necessary to connect the read data between the memory blocks 17 via the common bus, and the output circuit 140 and the output pad 150 can be independently provided in each of the memory blocks 110 to 117. As a result, the data read from each of the memory blocks 110 to 117 can be output to the outside of the semiconductor integrated circuit via the output circuit 140 and the output pad 150 arranged in the vicinity. That is, the wiring length from the reading of the stored data to the output to the outside of the semiconductor integrated circuit can be shortened, the delay time due to the resistance and capacitance of the wiring can be greatly reduced, and the semiconductor integrated circuit can be speeded up.

FIG. 2 shows a second embodiment of the present invention.
It is a figure which showed the decoder circuit of the Example shown in FIG. As described above, the memory capacity of each memory cell array 120 including the memory cell 210 is 1 Mbit, which is 8 Mbit in total. The decoder circuit includes a row decoder 230, a column decoder 231, a wiring connecting the output side of the row decoder 230 and each memory cell array 120, and a wiring connecting the output side of the column decoder 231 and each memory cell array 120. It is configured.

The address signal 220 composed of 20 bits is supplied to the row decoder 230 and the column decoder 231.
To the row selection signal 240 and the column selection signal 241. The row selection signal 240 and the column selection signal 241 are input to each of the eight memory cell arrays 120 and select each 1-bit memory cell 210 of each of the eight memory cell arrays 120. 1-bit data is output from each of the eight selected memory cells, and 8-bit data is formed as a whole. That is, the address signal 220 is a signal for selecting each 1-bit memory cell 210 in the eight memory cell arrays 120 each having a storage capacity of 1 Mbit,
For 20 bits of the address signal 220, 1-bit data in each of the eight memory cell arrays 120 is selected, and 8-bit data is output as a whole.

In the first and second embodiments, one output circuit 140 and one output pad 150 are provided for each of the eight memory cell arrays 120, and data is read from the entire memory cell arrays 120 bit by bit. The divided memory cell array 1
It is also possible to provide eight output circuits 140 and output pads 150 for each 20. In this case, data having an output bit width of 8 bits is output from one memory cell array 120, but data is output bit by bit from each of the eight output circuits and the output pads 150 connected to the memory cell array 120. , Each output pad 15
Since 0 is arranged close to the memory cell array 120, the in-chip wiring can be short and the wiring delay time can be shortened.

FIG. 3 shows a third embodiment of the present invention. The illustrated semiconductor integrated circuit 300 includes memory blocks 310 to 310 each including memory cell arrays 320 and 321.
313, read circuits 330 and 331 for reading data in the memory cell arrays 320 and 321, output circuits 340 commonly connected to the read circuits 330 and 331 in memory block units, and output circuits 340. The output pad 350 and the decoder circuits 360 to 365 arranged between the memory cell arrays are included.

In the semiconductor integrated circuit of this embodiment, for example, a semiconductor memory having an output bit width of 4 bits is taken as an example, and a memory block 310 obtained by dividing data of an arbitrary 1 bit in the output bit width of 4 bits into 4 pieces. The memory cell arrays 320 and 321 in 313 to 313 are divided and stored. In addition, this embodiment is obtained by partially modifying the first embodiment shown in FIG. 1 for 4-bit output, and using a memory having an output bit width of 8 bits, a 4-bit output memory is used. Is easy to configure.

FIG. 4 shows a fourth embodiment of the present invention. The illustrated semiconductor integrated circuit 400 includes a memory block 410 including memory cell arrays 420 to 423,
411, read circuits 430 to 433 connected to the memory cell arrays 420 to 423 for reading data from the memory cell arrays 420 to 423, respectively, and an output circuit 440 connected in parallel to the read circuits 430 to 433.
And an output pad 450 connected to the output circuit 440
And decoder circuits 460 to 465 arranged between the memory cell arrays.

In the semiconductor integrated circuit 400 of this embodiment, a semiconductor memory having an output bit width of 2 bits is taken as an example, and one bit data of either one of the output bit widths of 2 bits is divided into two. Memory blocks 410, 411
One of the memory cell arrays 420 to 423 is divided and stored. Further, this embodiment is a modification of the first embodiment shown in FIG. 1 for 2-bit output. A 2-bit output memory is simple by using a memory having an output bit width of 8 bits. It can be configured to.

In the embodiment shown in FIGS. 3 and 4, as described in FIG. 1, while reducing the delay time of the wiring,
It shows that the output bit width can be easily changed.

FIG. 5 shows a fifth embodiment of the present invention. The illustrated semiconductor integrated circuit 500 includes memory blocks 510 to 517 each including a memory cell array 120.
An input circuit 520 provided in each of the memory blocks 510 to 517, input pads 540 and 541 provided in each of the input circuits 520, and a decoder circuit 5
30 is included. The semiconductor integrated circuit of this embodiment is an example of a semiconductor memory having an output bit width of 8 bits, as in the case of the first embodiment shown in FIG. Each memory cell array 1 in the memory blocks 510 to 517 divided into two
It is stored in 20. That is, each memory cell array 120 stores data of any one of 8 bits.

Further, in this embodiment, an input circuit 520, a decoder circuit 530, and input pads 540 to 541 are added to the memory blocks 510 to 517, respectively, as compared with the first embodiment shown in FIG. ing. As a result, since the operation is closed in each of the memory blocks 510 to 517 from the input of data or address to the output of stored data, there is no long wiring portion from the input to the output of the semiconductor integrated circuit 500. This has the effect of speeding up data input to output. In this case, the semiconductor integrated circuit 500 has a plurality of input pads and input circuits corresponding to the same address signal.

FIG. 6 shows a sixth embodiment of the present invention. The illustrated semiconductor package 600 includes a semiconductor integrated circuit 610 of the present invention and lead wires 620, 621, 622A, 62.
2B and 623 to 626 are included.
The lead wires 622A and 622B are lead wires for the same signal. The lead wires 622A and 622B are connected by a wiring 650. The semiconductor integrated circuit 610 has input / output pads 630, 633, 634 and 636, and input pads 631A and 631B, 6 for inputting the same signal, respectively.
32A and 632B, 635A and 635B, and connecting means 640 that connects the lead wire on the semiconductor package 600 and the input / output pad in the semiconductor integrated circuit 610. That is, the semiconductor integrated circuit 610 has a plurality of input pads for inputting the same signal.

In the sixth embodiment shown in FIG. 6, lead wires 621 and 625 are connected to a plurality of input pads at the physically separated positions in the semiconductor integrated circuit 610 even though the same signal is input. , A plurality of connecting means 640 are provided, and a plurality of lead wires for the same signal, such as lead wires 622A and 622B, are provided. As a result, the wiring length outside the semiconductor integrated circuit 610 is increased by a part, but the wiring length for propagating a signal in the semiconductor integrated circuit 610 is shortened, and the semiconductor integrated circuit 610 as a whole.
The operation of was accelerated. Further, the semiconductor integrated circuit 6 of the present invention
By using 10, it was possible to improve the performance of the system.

[0032]

According to the present invention, the delay time of the wiring from each memory block in the semiconductor integrated circuit to the output circuit and the delay time of the wiring from the input circuit to each memory block can be reduced. This effect becomes remarkable as miniaturization and chip size increase in the future. That is, according to the above means, there is an effect of suppressing the delay time of the wiring occupying the critical path, which becomes a problem in advancing the miniaturization of the semiconductor integrated circuit and the increase of the chip size.

[Brief description of drawings]

FIG. 1 is a layout conceptual diagram showing a first embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a conceptual diagram of a decoder means showing a second embodiment of the semiconductor integrated circuit of the present invention.

FIG. 3 is a layout conceptual diagram showing a third embodiment of the semiconductor integrated circuit of the present invention.

FIG. 4 is a layout conceptual diagram showing a fourth embodiment of the semiconductor integrated circuit of the present invention.

FIG. 5 is an arrangement conceptual diagram showing a fifth embodiment of the semiconductor integrated circuit of the present invention.

FIG. 6 is a layout conceptual diagram showing a sixth embodiment of the semiconductor integrated circuit of the present invention.

FIG. 7 is a layout conceptual diagram showing a conventional example of a semiconductor integrated circuit.

FIG. 8 is a conceptual diagram showing a conventional example of a decoder means of a semiconductor integrated circuit.

[Explanation of symbols]

100 semiconductor integrated circuits 110-117
Memory block 120 Memory cell array 130 Reading circuit 140 Output circuit 150 Output pad 160-165 Decoder circuit 170 Input circuit 180-185 Input pad 210 Memory cell 220 Address signal 230 Row decoder 231 Column decoder 240 Row selection signal 241 Column selection signal 300 Semiconductor device 310-313 memory blocks 320-321
Memory cell array 330 to 331 Read circuit 340 Output circuit 350 Output pad 360 to 365
Decoder circuit 400 Semiconductor device 410-411
Memory blocks 420 to 423 Memory cell arrays 430 to 433
Read circuit 440 Output circuit 450 Output pad 460-465 Decoder circuit 500 Semiconductor device 510-517 Memory block 520 Input circuit 530 Decoder circuit 540-541
Input pad 600 Semiconductor package 610 Semiconductor integrated circuit 620-626 Lead wire 630-636
Input / output pad 640 Means for connecting lead wire and input / output pad 650 Connection wiring 710-717
Memory block 720 Memory cell array 730 Read circuit 740 to 745 Decoder circuit 750 Common bus 760 Output circuit 770 Input circuit 780 to 787 Output pad 790 to 795
Input pad 810-817 Memory cell 820,821
Address signal 830 row decoder 831 column decoder 832 block decoder 840 row selection signal 841 column selection signal 842 block selection signal 860 switch means

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 7, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

FIG. 8 is a diagram simply showing a decoding means of the semiconductor integrated circuit shown in FIG. In this example, the address signals 820 and 821 are decoded by the row decoder 830, the column decoder 831 and the block decoder 832 to become the row selection signal 840, the column selection signal 841 and the block selection signal 842, and the memory selected by the block selection signal 842. Memory cell 81 in cell array 720
Any of 0 to 817 is selected by the row selection signal 840 and the column selection signal 841. The signal read from the selected memory cell is output to the common bus 750 and the output circuit 7.
Output pad 780-787 is reached via 60, and from here
Propagated outside the semiconductor integrated circuit . That is, one of the eight memory cell arrays 720 is selected according to the address signal.
One of them is selected, the 8-bit data therein is selected, and output from the output pads 780-787 . Therefore, in order to output the data read from any memory cell array 720 from the output pads 780 to 787, the semiconductor
A common bus 750 is provided that spans the entire length of the integrated circuit . First, if one of the memory cell arrays is selected and 8-bit data is taken out from this memory cell array, it is not necessary to operate the remaining memory cell array, and it is easy to reduce power consumption. .

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

An object of the present invention is to reduce the delay time of the semiconductor integrated circuit wiring.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

FIG. 2 shows a second embodiment of the present invention and is a diagram showing a decoder circuit of the embodiment shown in FIG. As described above, the memory capacity of each memory cell array 120 including the memory cell 210 is 1 Mbit,
The total is 8M bits. The decoder circuit includes a row decoder 230, a column decoder 231, a wiring connecting the output side of the row decoder 230 and each memory cell array 120, an output side of the column decoder 231, and each memory cell.
The wiring that connects the array 120 is included.

Claims (10)

[Claims] 1. A decoding means for decoding an address signal, a memory cell array in which memory cells are arranged in an array, a reading means for reading data in the memory cells, and an output for outputting the read data. In a semiconductor integrated circuit including a buffer means, the semiconductor integrated circuit is divided into a plurality of blocks, and an output buffer for outputting the data read from the block independently to each of the divided blocks. A semiconductor integrated circuit comprising means. 2. The semiconductor integrated circuit according to claim 1, wherein the decoding means decodes the address signal so that at least 1-bit data constituting each data is read from each divided block. A semiconductor integrated circuit characterized by being present. 3. The semiconductor integrated circuit according to claim 1, wherein the memory cell array in each divided block is divided into two, and the read signal line from each of the divided memory cell arrays is divided into two. A semiconductor integrated circuit characterized by being connected between memory cell arrays. 4. The semiconductor integrated circuit according to claim 1, wherein the memory cell array in each divided block is divided into four, and the read signal line from each of the four divided memory cell arrays is divided into four. A semiconductor integrated circuit characterized by being connected between memory cell arrays. 5. A decoding means for decoding an address signal, a memory cell array in which memory cells are arranged in an array, a reading means for reading data in the memory cells, and an output for outputting the read data. In a semiconductor integrated circuit including a buffer means and an input buffer means for inputting a signal, the semiconductor integrated circuit is divided into a plurality of blocks, and each of the blocks independently of the output buffer means and the input buffer. A semiconductor integrated circuit comprising means. 6. The semiconductor integrated circuit according to claim 5, wherein the decoding means decodes the address signal so that at least 1-bit data forming each data is read from each divided block. A semiconductor integrated circuit characterized by being present. 7. The semiconductor integrated circuit according to claim 5 or 6, wherein each block is independently provided with a decoding unit for decoding an address signal. 8. A decoding means for decoding an address signal, a memory cell array in which memory cells are arranged in an array, a reading means for reading data in the memory cells, and an input buffer means for inputting a signal. In the semiconductor integrated circuit including the above, the input buffer means includes a plurality of input buffer means for inputting the same signal. 9. A semiconductor package comprising the semiconductor integrated circuit according to claim 8 and an input signal lead wire, wherein at least one of the input signal lead wires is provided at a plurality of input buffers in the semiconductor integrated circuit. A semiconductor package comprising means for transmitting a signal to the means. 10. A semiconductor package comprising the semiconductor integrated circuit according to claim 8 and an input signal lead wire, from a plurality of lead wires of the same input signal to a plurality of input buffer means in the semiconductor integrated circuit. A semiconductor semiconductor package comprising means for transmitting signals, respectively.