JP2013093354A - Semiconductor device design method and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit deterioration in yield of a semiconductor device.SOLUTION: A semiconductor device design method comprises: acquiring wiring pattern data indicating a wiring pattern (step S10); subsequently, analyzing the wiring pattern data to identify a first direction pattern and a second direction pattern (step S20) where the first direction pattern is a pattern extending in a first direction and the second direction pattern is a pattern extending in a direction orthogonal to the first direction; subsequently, detecting an intersection point of the first direction pattern and the second direction pattern; detecting among patterns extending from the intersection point, a pattern that is not connected to any one of a via, a contact and another pattern as an unnecessary pattern and removing the detected unnecessary pattern (step S30); and subsequently, performing optical proximity correction on the designed wiring pattern (step S40).

Description

  The present invention relates to a semiconductor device design method and a semiconductor device manufacturing method.

  Generally, a design apparatus is used for designing a semiconductor device. For example, the semiconductor device design apparatus described in Patent Document 1 performs the following processing. First, layout data is generated by arranging and wiring cells using data in the library. Then, after optical proximity correction is performed on the layout data, error determination is performed.

JP 2009-152298 A

  As a result of studies by the present inventors, it has been found that there are the following problems. Since a semiconductor device design apparatus automatically generates a layout, an unnecessary pattern on a circuit may be generated. If this unnecessary pattern has a small process margin, the yield of the semiconductor device may be reduced due to the unnecessary pattern.

According to the present invention, a step of obtaining wiring pattern data indicating a wiring pattern;
Analyzing the wiring pattern data to identify a first direction pattern extending in a first direction and a second direction pattern extending in a direction orthogonal to the first direction, the first direction pattern and the Detecting an intersection of the second direction patterns;
Detecting unnecessary patterns that are not connected to any of vias, contacts, and other patterns among patterns extending from the intersection, and removing the detected unnecessary patterns;
A method of designing a semiconductor device is provided.

According to the present invention, a step of designing a wiring pattern;
Forming a wiring layer using the designed wiring pattern;
Have
The step of designing the wiring pattern includes:
Obtaining wiring pattern data indicating the wiring pattern;
Analyzing the wiring pattern data to identify a first direction pattern extending in a first direction and a second direction pattern extending in a direction orthogonal to the first direction, the first direction pattern and the Detecting an intersection of the second direction patterns;
Detecting unnecessary patterns that are not connected to any of vias, contacts, and other patterns among patterns extending from the intersection, and removing the detected unnecessary patterns;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, it is possible to suppress a decrease in yield of a semiconductor device due to an unnecessary pattern.

3 is a flowchart illustrating a method for designing a semiconductor device according to an embodiment. It is a figure which shows the design method of the semiconductor device which concerns on embodiment. It is a figure which shows the design method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the structure of the semiconductor device which has a wiring layer designed using the method shown in FIGS.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a flowchart illustrating a method for designing a semiconductor device according to an embodiment. This semiconductor device design method includes the following steps. First, wiring pattern data indicating a wiring pattern belonging to the same wiring layer is acquired (step S10). This step may be a step of generating wiring pattern data or a step of reading already generated wiring pattern data from a recording medium. Next, the wiring pattern data is analyzed to identify the first direction pattern and the second direction pattern (step S20). The first direction pattern is a pattern that extends in the first direction, and the second direction pattern is a pattern that extends in a direction orthogonal to the first direction. Next, the intersection of the first direction pattern and the second direction pattern is detected. Of the patterns extending from the intersection, a pattern that is not connected to any of the vias, contacts, and other patterns is detected as an unnecessary pattern, and the detected unnecessary pattern is removed (step S30). Thereafter, optical proximity correction (OPC) is performed on the designed wiring pattern (step S40). Hereinafter, this will be specifically described with reference to FIGS.

  First, as shown in FIG. 2A, a plurality of virtual first direction patterns 10 are arranged. The plurality of virtual first direction patterns 10 extend in parallel to each other and indicate portions where wiring patterns can actually be arranged.

  Next, as shown in FIG. 2B, the first direction pattern 20 is arranged in a necessary portion among the plurality of virtual first direction patterns 10. In the example shown in this figure, the first direction pattern 20 is arranged in two virtual first direction patterns 10 adjacent to each other. Further, another first direction pattern 20 is arranged with at least one virtual first direction pattern 10 sandwiched between these two first direction patterns 20.

  Next, as shown in FIG. 3A, the second direction pattern 30 is arranged. The second direction pattern 30 shown in the figure connects the first direction patterns 20 adjacent to each other.

  At this time, depending on the algorithm of the design device, the second direction pattern 30 protrudes from the two first direction patterns 20 and is connected to the virtual first direction pattern 10 in which the first direction pattern 20 is not arranged. May be.

  Moreover, the 2nd direction pattern 40 which is an unnecessary pattern may be formed depending on the algorithm of a design apparatus. In the example shown in this figure, the second direction pattern 40 is provided so as to connect a certain first direction pattern 20 to the adjacent virtual first direction pattern 10 (however, the first direction pattern 20 is not disposed). It has been.

  Next, as shown in FIG. 3B, an unnecessary wiring pattern is detected from the designed wiring pattern using a design apparatus, and the detected wiring pattern is removed. Specifically, the design apparatus first detects the intersection between the second direction pattern 30 and the first direction pattern 20 and the intersection between the second direction pattern 40 and the first direction pattern 20. Of the wiring patterns extending from the detected intersection, a pattern that is not connected to any of the vias, contacts, and other patterns is detected as an unnecessary pattern. In the example illustrated in FIG. 3B, the design apparatus regards a portion of the second direction pattern 30 that connects the first direction pattern 20 and the adjacent virtual first direction pattern 10 as the unnecessary pattern 32. Remove. Further, the design apparatus considers the second direction pattern 40 as an unnecessary pattern and removes it.

  Thereafter, optical proximity effect correction is performed. Then, a reticle is manufactured according to the wiring pattern subjected to the optical proximity effect correction, and a wiring layer of the semiconductor device is formed using this reticle. This wiring layer is a layer in which, for example, a gate wiring is formed, but it may be a wiring layer thereon.

  The semiconductor device design method described above is performed using a semiconductor device design apparatus. This design apparatus is realized by installing a program in a computer. This program may be installed in the computer via a recording medium, for example, or may be installed in the computer via a communication line.

  FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device having a wiring layer designed by using the above-described method. This semiconductor device has a MOS transistor. This MOS transistor is formed in the element formation region. The element formation region is separated from other regions by the element isolation film 102. The element isolation film 102 is, for example, STI.

  The MOS transistor has a gate insulating film 103, a gate electrode 104, a sidewall 105, an extension region 106, and a diffusion region 107. The gate insulating film 103 is formed on the semiconductor substrate 100. The semiconductor substrate 100 is, for example, a Si substrate. The gate insulating film 103 is, for example, a silicon oxide film, but may be a film (High-k film) having a dielectric constant higher than that of silicon oxide, for example, an Hf-containing film. A gate electrode 104 is formed on the gate insulating film 103. The gate electrode 104 is, for example, polysilicon, but may be a metal gate such as TiN.

  Sidewalls 105 are formed on the side walls of the gate insulating film 103 and the gate electrode 104. The sidewall 105 may have a single layer structure or a stacked structure in which a plurality of layers are stacked.

  The extension region 106 and the diffusion region 107 are formed by introducing impurities into the semiconductor substrate 100. The diffusion region 107 functions as a source / drain of the MOS transistor.

  A wiring layer 120 is formed on the element isolation film 102 and the MOS transistor. A contact 122 and a wiring 124 are embedded in the wiring layer 120. The contact 122 connects the wiring 124 and the MOS transistor.

  Among the structures described above, the pattern of the gate electrode 104 is designed by the method described with reference to FIGS. The wiring 124 may also be designed by the method described with reference to FIGS.

  Next, a method for manufacturing this semiconductor device will be described. First, the element isolation film 102 is formed on the semiconductor substrate 100. Thereby, the element formation region is separated. The element isolation film 102 is formed using, for example, the STI method, but may be formed using the LOCOS method. Next, a gate insulating film 103 is formed on the semiconductor substrate 100 located in the element formation region.

  Next, a conductive film to be a gate electrode is formed over the gate insulating film 103. Next, a resist film is formed on the conductive film, and the resist film is exposed and developed using a reticle. The pattern of the reticle is designed by the method described with reference to FIGS. Thereby, a resist pattern is formed. Next, the conductive film is selectively removed using this resist pattern. Thereby, the gate electrode 104 is formed.

  When the gate insulating film 103 is a silicon oxide film, the gate electrode 104 is formed of a polysilicon film. When the gate insulating film 103 is a high dielectric constant film, the gate electrode 104 is formed of a laminated film of a metal film (for example, TiN) and a polysilicon film. In the case where the gate electrode 104 is formed of polysilicon, a polysilicon resistor may be formed on the element isolation film 102 in the step of forming the gate electrode 104.

  Next, source and drain extension regions 106 are formed in the semiconductor substrate 100 located in the element formation region. Next, a sidewall 105 is formed on the sidewall of the gate electrode 104. Next, diffusion regions 107 serving as a source and a drain are formed in the semiconductor substrate 100 located in the element formation region. In this way, a MOS transistor is formed on the semiconductor substrate 100.

  Next, a wiring layer 120 is formed on the element isolation film 102 and the MOS transistor. The wiring layer 120 is formed by, for example, a single damascene method, but may be formed by a dual damascene method. When the wiring layer 120 is formed, a wiring groove is formed in the insulating film of the wiring layer 120. The pattern of the reticle for forming the wiring groove may be designed by the method described with reference to FIGS.

  Next, the effect of this embodiment will be described. According to this embodiment, the gate electrode 104 does not have an unnecessary pattern. If there is an unnecessary pattern in the gate electrode 104, the possibility of manufacturing failure of the semiconductor device increases accordingly. For this reason, it can suppress that the manufacturing defect of a semiconductor device arises due to an unnecessary pattern. In particular, when the unnecessary pattern is the minimum pattern allowed by the design rule of the semiconductor device, this effect becomes remarkable.

  In addition, when the wirings included in the wiring layer 120 are also designed by the method described with reference to FIGS. 1 to 3, it is possible to suppress a manufacturing failure of the semiconductor device due to an unnecessary pattern when the wiring layer 120 is formed. it can.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

10 virtual first direction pattern 20 first direction pattern 30 second direction pattern 32 unnecessary pattern 40 second direction pattern 100 semiconductor substrate 102 element isolation film 103 gate insulating film 104 gate electrode 105 sidewall 106 extension region 107 diffusion region 120 wiring layer 122 Contact 124 Wiring

Claims (4)

Obtaining wiring pattern data indicating the wiring pattern;
Analyzing the wiring pattern data to identify a first direction pattern extending in a first direction and a second direction pattern extending in a direction orthogonal to the first direction, the first direction pattern and the Detecting an intersection of the second direction patterns;
Detecting unnecessary patterns that are not connected to any of vias, contacts, and other patterns among patterns extending from the intersection, and removing the detected unnecessary patterns;
A method for designing a semiconductor device comprising: The method for designing a semiconductor device according to claim 1,
A method for designing a semiconductor device, wherein the wiring pattern is a gate wiring pattern. In the design method of the semiconductor device according to claim 1 or 2,
A method for designing a semiconductor device, comprising a step of performing optical proximity correction on the wiring pattern after the step of removing the unnecessary pattern. A process of designing a wiring pattern;
Forming a wiring layer using the designed wiring pattern;
Have
The step of designing the wiring pattern includes:
Obtaining wiring pattern data indicating the wiring pattern;
Analyzing the wiring pattern data to identify a first direction pattern extending in a first direction and a second direction pattern extending in a direction orthogonal to the first direction, the first direction pattern and the Detecting an intersection of the second direction patterns;
Detecting unnecessary patterns that are not connected to any of vias, contacts, and other patterns among patterns extending from the intersection, and removing the detected unnecessary patterns;
A method for manufacturing a semiconductor device comprising:

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