JP2012209350A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a failure occurs in a pattern when a core insulating film which is to be a profile material for forming a cylinder type electrode is removed at a wafer edge part at which defocus occurs at the time of cylinder hole formation when forming a capacitor having a cylinder type electrode that is held by a support film.SOLUTION: An opening part of a support film 27 formed to remove a core insulating film 26 is not formed at a wafer edge part where defocus occurs. A mat width Mb larger than a mat width Ma of an ordinary exposure part is preferred to be formed, so that the core insulating film 26 remains under the support film 27 of the wafer edge part.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a crown type capacitor.

  In a semiconductor device such as a DRAM, a capacitor having a three-dimensional structure is exclusively used with miniaturization. In particular, as a capacitor used in a DRAM memory cell, a crown type capacitor in which both an inner wall and an outer wall of a lower electrode are used as electrodes is applied. By making the capacitor a crown type, the capacitance can be increased without increasing the occupied area.

  In such a method of forming a crown capacitor, a cylinder hole is formed in a core insulating film to form a cylindrical lower electrode, then a lower electrode is formed in the cylinder hole, and then the core insulating film is removed. As a result, the outer wall of the lower electrode is exposed.

  When removing the core insulating film, the core insulating film is removed by wet etching. At this time, the lower electrode may collapse (collapse). To prevent this, a support film (support) structure is provided. The thing provided with is known (patent document 1).

  In addition, openings are formed in a predetermined pattern in the support film in order to penetrate the wet etching chemical.

JP 2003-297852 A

  Usually, in a semiconductor device such as a DRAM, a plurality of chips are formed together on a silicon wafer. The edge portion of the silicon wafer is processed into a chamfered (round) shape to prevent cracking and chipping. In order to reduce the manufacturing cost of the semiconductor device, it is advantageous to provide a chip removal region as close to the wafer edge as possible so as to form as many chips as possible on one wafer.

  When forming a cylinder hole for forming a capacitor in the core insulating film, a number of fine hole patterns are formed in the resist film by using a photolithography technique. In the photolithographic technique, shot exposure is generally performed in which a top is sequentially exposed on a single ridge using a mask (reticle) that can expose a predetermined region at a time. In shot exposure, exposure is performed across the wafer edge. However, there is a problem in that defocusing (focal shift) is likely to occur at a wafer edge portion having a step, particularly in cylinder hole exposure for forming a fine hole pattern. At the wafer edge portion where such defocusing occurs, the hole pattern diameter formed in the resist mask is smaller than that in the normally exposed portion, and cylinder hole processing is performed on the core insulating film using this resist mask. And cause poor opening. The lower electrode material is also formed in such a defective hole portion, and when the support film is formed and the core insulating film is removed thereafter, the lower electrode material in the defective hole portion is detached (so-called pattern skip). It is a source of garbage.

  In the present invention, at the time of patterning the support film on the wafer edge portion where defocusing occurs, the opening of the support film that is normally formed is not formed, but the core insulating film is left under the support film on the wafer edge portion when removing the core insulating film. Thus, a method for suppressing pattern skipping is provided.

Specifically, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
Forming a functional element on a semiconductor substrate;
Forming a core insulating film on the functional element;
Forming a support film on the core insulating film;
Forming a cylinder hole in the support film and the core insulating film;
Forming a lower electrode of a capacitor in the cylinder hole;
Forming an opening in the support film;
Selectively removing the core insulating film under the support film by wet etching through the opening;
And manufacturing a plurality of semiconductor devices on a single wafer as the semiconductor substrate,
In a portion where defocus occurs in the wafer edge portion when the cylinder hole is formed, an opening is not formed in the support film, and in the step of selectively removing the core insulating film, the core insulating film under the support film in the portion A method of manufacturing a semiconductor device, wherein at least a part of the semiconductor device is left.

  More preferably, at the time of pattern exposure for forming an opening in the support film, the pattern exposure is performed evenly on the entire surface using a negative resist, and then the defocusing unit is subjected to two-stage exposure to form the pattern. By exposing at least the unexposed part corresponding to the opening pattern in the exposure and increasing the resist remaining area in the pattern exposure, no opening is formed in the defocus part when processing the support film using the resist mask. Increase the remaining support film.

  According to an embodiment of the present invention, pattern skipping is suppressed by eliminating the opening of the support film at the wafer edge where defocusing occurs when forming the cylinder hole, and leaving the core insulating film without being removed.

1 is a plan view showing a layout of a memory cell region in a DRAM device according to an embodiment of the present invention. 1 is a schematic cross-sectional view showing a structure of one memory cell of a DRAM device according to an embodiment of the present invention. It is process sectional drawing explaining the manufacturing method of the DRAM apparatus which concerns on the example of 1 embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the DRAM apparatus which concerns on the example of 1 embodiment of this invention. It is a figure which shows the wafer shot layout at the time of cylinder hole formation. 4A and 4B are process cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, where FIG. 5A is a wafer edge portion where defocusing occurs, and FIG. 5B is a normal exposure portion. 4A and 4B are process cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, where FIG. 5A is a wafer edge portion where defocusing occurs, and FIG. 5B is a normal exposure portion. 4A and 4B are process cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, where FIG. 5A is a wafer edge portion where defocusing occurs, and FIG. 5B is a normal exposure portion. 4A and 4B are process cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, where FIG. 5A is a wafer edge portion where defocusing occurs, and FIG. 5B is a normal exposure portion. It is a top view which shows an example of the opening part pattern formed in a support film. It is a top view which shows an example of the exposure mask (reticle) used for exposure of an opening part pattern, (a) is a general view, (b) is an enlarged view of the normal exposure part A, (c) is an expansion of the additional exposure part B FIG. It is a figure which shows the wafer shot layout at the time of support film opening formation, (a) is normal exposure, (b) is a shot layout of additional exposure. 4A and 4B are process cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, where FIG. 5A is a wafer edge portion where defocusing occurs, and FIG. 5B is a normal exposure portion. 4A and 4B are process cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, where FIG. 5A is a wafer edge portion where defocusing occurs, and FIG. 5B is a normal exposure portion. 4A and 4B are process cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, where FIG. 5A is a wafer edge portion where defocusing occurs, and FIG. 5B is a normal exposure portion. It is a figure which shows the outline from cylinder hole formation to core insulation film removal which concerns on one Embodiment of this invention, (a) is the schematic after cylinder hole formation, (b) is after the opening part formation to a support film Schematic (c) is a schematic diagram after removal of the core insulating film. It is a figure which shows the outline from cylinder hole formation of a prior art example to core insulation film removal, (a) is the schematic after cylinder hole formation, (b) is the schematic after opening part formation to a support film, (c) ) Is a schematic view after removal of the core insulating film.

  Hereinafter, exemplary embodiments of the present invention will be specifically described with reference to the drawings. However, the present invention is not limited only to these exemplary embodiments.

First, a semiconductor device having a crown type capacitor as an object of the present invention will be described.
FIG. 1 is a plan view showing a layout of a memory cell region in a semiconductor device according to the present invention, for example, a DRAM device.

  As shown in the figure, the semiconductor device 50 is provided with a plurality of memory cell regions 51. Around each memory cell region 51, a peripheral circuit region 52 including circuit blocks (not shown) other than memory cells such as a sense amplifier circuit and a decoder circuit is arranged. Note that a compensation capacitor can be provided in the peripheral circuit region 52, and a crown capacitor similar to the capacitor formed in the memory cell region can be formed.

  In one memory cell region, a plurality of crown capacitors are arranged in a general layout called, for example, 8F2, 6F2, 4F2, etc., and the lower electrode of each capacitor is supported by a support film above it. ing. FIG. 2 is a schematic cross-sectional view showing the structure of one memory cell.

  As shown in FIG. 2, two transistors are provided in the active region defined by the element isolation region 12 of the semiconductor substrate 11. The transistor is provided with a gate conductive film 14 and a gate cap layer 15 on a gate insulating film 13. A gate electrode 16 formed of a stacked layer, a gate sidewall spacer 17 formed on the side wall of the gate electrode 16, and diffusion layers 18a to 18c serving as source / drain regions in an active region between the gate electrodes. The diffusion layer 18b shared by the two transistors is connected to the bit line 21 on the first interlayer insulating film 19 via the cell contact plug 20b serving as a bit contact. The layers 18a and 18c are connected to the capacitor contact plug 23 penetrating the second interlayer insulating film 22 through the cell contact plugs 20a and 20c. Further, the capacitor contact plug 23 is connected to the pad electrode 24 on the second interlayer insulating film 22, and the pad electrode is covered with the third interlayer insulating film 25. A lower electrode 28 of the capacitor 31 is connected to the pad electrode 24 through the third interlayer insulating film 25, and the upper side of the lower electrode 28 is supported by a support film 27. A capacitor insulating film 29 and an upper electrode 30 are provided on the outer wall and the inner wall of the lower electrode 28 to constitute a capacitor 31.

Embodiment 1
Next, a method for manufacturing a semiconductor device will be described with reference to process cross-sectional views.
First, FIG. 3 shows a state where up to the third interlayer insulating film 25 is formed by a known method. Here, a planar type is given as an example of a transistor, but the present invention is not limited to this, and a recess gate structure in which a part of a gate electrode is embedded in a substrate or a trench gate structure in which a gate electrode is embedded in a substrate are also used. good. In addition, the arrangement of bit lines, the number of stacked contact plugs, and the like may be changed depending on the gate electrode structure.

  Next, as shown in FIG. 4, a core insulating film 26 is formed on the third interlayer insulating film 25. The core insulating film 26 functions as a mold material for forming the capacitor lower electrode, and is formed of, for example, a silicon oxide film. When the core insulating film 26 is formed of a silicon oxide film, the third interlayer insulating film 25 is formed of a material having an etching selectivity with respect to the core insulating film 26, for example, a silicon nitride film. A support film 27 is formed on the core insulating film 26, and the support film 27 is also formed of a silicon nitride film or the like having an etching selectivity with respect to the core insulating film 26.

  A resist mask pattern (not shown) for cylinder holes is formed on the support film 27 by using a photolithography technique. At this time, in order to form a plurality of chips on a single wafer, exposure (shot exposure) is sequentially performed while a reticle serving as a photomask is moved on the wafer by a stepper. FIG. 5 shows a wafer shot layout when forming a cylinder hole. As shown in the figure, cylinder defocus (Df) occurs in the shaded area due to the step of the wafer edge. When cylinder hole processing is performed in a state where such defocusing occurs, a desired cylinder hole 26b is formed in the normal exposure portion (b) as shown in FIG. 6, but defocusing of the wafer edge portion (a) is performed. The diameter of the portion becomes small, and an irregular cylinder hole 26a is formed. In addition, since there is no change about the structure below from the 3rd interlayer insulation film 25, description is abbreviate | omitted below.

  Next, as shown in FIG. 7, a lower electrode material 28M is formed. A lower electrode material 28M having a predetermined thickness is formed on the inner wall portion of the cylinder hole 26b from the upper portion of the support film 27. An example of the lower electrode material is titanium nitride (TiN), but is not limited thereto. The film thickness of the lower electrode material 28M is formed so as not to fill the inside of the cylinder hole 26b. For example, when the hole diameter of the cylinder hole 26b is 80 nm, the film thickness is about 10 to 20 nm. On the other hand, the lower electrode material is embedded in the cylinder hole 26a and the cylinder hole 26a is filled with the lower electrode material in the figure, but the present invention is not limited to this.

  Subsequently, as shown in FIG. 8, a cap insulating film 32 such as a silicon oxide film is formed on the lower electrode material by using a film forming method with poor step coverage such as a plasma CVD method. In the cylinder hole 26b, only the vicinity of the upper end of the opening is filled with the cap insulating film 32. This is because when a cap insulating film is formed by a film formation method with poor coverage on a cylinder hole processed with a design rule of the generation with a minimum processing dimension of 65 nm or later, the upper end of the hole is closed first and a film is deposited in the hole. It is because it does not. Since the cap insulating film 32 is removed in a later process, it is not necessary to completely prevent the inner wall of the lower electrode in the hole from being attached.

  Next, as shown in FIG. 9, a photoresist film 33 is formed as a mask in order to form an opening for removing the core insulating film 26 in the support film 27. A negative photoresist is used as the photoresist film 33. The exposure here is also performed by shot exposure.

  FIG. 10 is a plan view showing an example of the opening pattern 33A formed in the photoresist film 33. As shown in FIG. In the normal exposure portion, as shown in the figure, the opening pattern 33A is formed so that at least a part of the side wall of each lower electrode is held by the support film.

  FIG. 11A is a plan view showing an example of a reticle used for this shot exposure. The reticle is formed by forming a chromium (Cr) film in a predetermined pattern as a light shielding mask 2 on a transparent substrate 1 such as a glass substrate, and one square corresponds to one mat area. In this example, an example in which a normal exposure portion A corresponding to the opening pattern of the normal exposure portion and an additional exposure portion B that performs additional exposure described later is provided, but the additional exposure portion B may be a separate reticle. . Enlarged views of the patterns of the mat areas are shown in FIGS. FIG. 11B shows the mat pattern of the normal exposure portion A, where the hatched area is the light shielding mask 2, and the other area is the light transmission portion 3. On the other hand, as shown in FIG. 11C, the opening pattern to the support film is not provided inside the mat pattern of the additional exposure portion B. Further, the width of the mat area is set to Mb that is slightly larger than the mat width Ma of the normal exposure portion A.

  Using such a reticle, first, normal exposure is performed using the normal exposure portion A including the cylinder defocus portion as shown in FIG. By this exposure, an unexposed portion corresponding to the support film opening is also formed in the cylinder defocus portion at the wafer edge. Next, as shown in FIG. 12B, double exposure is performed using the additional exposure portion B on the reticle only at the cylinder defocus portion at the wafer edge. Thereby, an unexposed part is exposed. When development processing is performed after such exposure, the resist film remains in the exposed portion, and the unexposed portion is removed. That is, as shown in FIG. 9, the opening pattern is not formed on the support film of the cylinder defocus portion at the wafer edge (FIG. 9A), and the opening pattern is formed only in the normal exposure portion (FIG. 9). 9 (b)).

  Using the photoresist film 33 thus formed as a mask, anisotropic dry etching is performed to remove the cap insulating film 32, the lower electrode film 28M, and the support film 27 that are not covered with the photoresist film 33. . Thus, an opening (window pattern) is formed in the support film 27 corresponding to the opening pattern (FIG. 13B), but no opening is formed in the defocused portion of the wafer edge (FIG. 13). (A)). Further, the mat area of the support film becomes large at the wafer edge portion having the mat region width Mb wider than the mat region width Ma of the normal exposure portion.

  Next, the remaining cap insulating film 32 and the lower electrode film 28M on the support film 27 are removed by dry etching. Here, when the aspect ratio of the cylinder hole is high (for example, when the aspect ratio is 15 or more), the lower electrode film 28M on the support film 27 is removed without damaging the lower electrode film at the bottom of the cylinder hole. (FIG. 14B). Similarly, the lower electrode film 28M on the support film 27 is also removed at the wafer edge portion (FIG. 14A).

  Next, as shown in FIG. 15, the core insulating film 26 under the support film 27 is removed by wet etching using hydrofluoric acid (hydrofluoric acid (HF) solution) as a chemical solution. As the hydrofluoric acid solution, in order to shorten the time required for wet etching, it is preferable to use a concentrated hydrofluoric acid (49 wt%) stock solution commercially available for industrial use as it is.

  By such wet etching, the chemical solution penetrates through the opening formed in the support film 27 in the normal exposure portion, and the entire core insulating film 26 can be removed (FIG. 15B). On the other hand, at the wafer edge portion, the support film 27 is not provided with an opening, and the core insulating film 26 remains (FIG. 15A). At this time, since the etchant enters from the mat end, the mat end is etched. In consideration of the etching amount (side etching amount) from the mat end, it is preferable to select the mat width Mb so that the lower electrode film at the mat end is not exposed.

  FIG. 16 shows an outline from the formation of the cylinder hole to the removal of the core insulating film. FIG. 2A shows an outline after the cylinder hole is formed. FIG. 2B shows an outline after the opening is formed in the support film 27. It can be seen that the mat area of the wafer edge portion is formed in Mb wider than the width Ma of the mat area of the normal exposure portion. FIG. 2C shows an outline after the core insulating film 26 is removed. It can be seen that the core insulating film is removed in the normal exposure portion, but only the side etching from the mat end is performed in the wafer edge portion.

  Here, as a conventional example, FIG. 17 shows a case where the support film opening is formed in the same manner without performing additional exposure on the defocused portion of the wafer edge. FIGS. 16A to 16C correspond to FIGS. 16A to 16C, respectively. Since only the normal exposure shown in FIG. 12A is performed, the mat width of the support film is the same Ma even at the wafer edge portion where defocusing occurs as shown in FIG. 12B. Similarly, an opening is formed in the support film. When the core insulating film 26 is removed in such a state, the core insulating film 26 is also removed at the wafer edge portion, and pattern skipping occurs (FIG. 3C). It should be noted that the drawings are drawn by the inventor in order to explain the problems of the present invention, and are not the prior art itself. On the other hand, in this embodiment, no opening is formed in the support film at the wafer edge, and pattern skipping can be suppressed by leaving the core insulating film below the support film. Furthermore, by making the mat region width Mb larger than the mat width Ma of the normal exposure region, it is possible to increase the remaining core insulating film 26 and enhance the adhesion.

  Thereafter, the capacitor insulating film 29 and the upper electrode 30 are formed, whereby the device shown in FIG. 2 is completed. Further, by forming an upper interlayer film, upper wiring, etc. (not shown), the semiconductor device according to the present invention can be obtained. Further, each semiconductor device on the wafer is cut for each chip to obtain individual semiconductor devices. The one including the cylinder defocus portion at the wafer edge portion is discarded because it does not function normally as a capacitor.

Embodiment 2
In the first embodiment, the mat pattern different from the normal pattern is used to form the opening pattern of the support film 27. However, in this embodiment, the normal support film opening pattern is shifted by half a pitch and double exposure is performed. By doing so, the support opening of the defocus portion can be eliminated. Further, by performing multiple exposure with the position shifted larger than the core wet etching amount with respect to the four directions of the cell mat edge, the mat area width of the support film at the defocus portion of the wafer edge portion can be reduced as in the first embodiment. It can also be wider than the normal exposure area. In the present embodiment example, it is not necessary to separately prepare an expensive reticle, so that an increase in manufacturing cost can be suppressed.

Embodiment 3
In the above-described embodiment, the support film is separated as a mat area also in the defocus portion, but can be continuously left without being separated as a mat area. For example, the reticle for additional exposure may be exposed as a pattern having a larger light transmission portion 3.

DESCRIPTION OF SYMBOLS 1 Transparent substrate 2 Light-shielding film 3 Light transmission part 11 Semiconductor substrate 12 Element isolation film 13 Gate insulating film 14 Gate conductor film 15 Gate cap film 16 Gate electrode 17 Gate sidewall sidewall spacers 18a to 18c Diffusion layer 19 First interlayer insulating film 20a -20c Cell contact plug 21 Bit line 22 Second interlayer insulating film 23 Capacitor contact plug 24 Pad electrode 25 Third interlayer insulating film 26 Core insulating film 27 Support film 28 Lower electrode 29 Capacitor insulating film 30 Upper electrode 31 Capacitor 32 Cap insulating film 33 Photoresist film 33A Opening pattern

Claims (7)

Forming a functional element on a semiconductor substrate;
Forming a core insulating film on the functional element;
Forming a support film on the core insulating film;
Forming a cylinder hole in the support film and the core insulating film;
Forming a lower electrode of a capacitor in the cylinder hole;
Forming an opening in the support film;
Selectively removing the core insulating film under the support film by wet etching through the opening;
And manufacturing a plurality of semiconductor devices on a single wafer as the semiconductor substrate,
In a portion where defocus occurs in the wafer edge portion when the cylinder hole is formed, an opening is not formed in the support film, and in the step of selectively removing the core insulating film, the core insulating film under the support film in the portion A method for manufacturing a semiconductor device, wherein at least a part of the semiconductor device is left.   At the time of pattern exposure for forming openings in the support film, the defocus occurs after shot exposure is performed using an exposure mask having a predetermined opening pattern uniformly on the entire surface of the negative resist. Performing a multiple exposure on the portion, exposing at least an unexposed portion corresponding to the opening pattern in the shot exposure, forming a resist mask, and performing opening processing of the support film using the resist mask; The method of manufacturing a semiconductor device according to claim 1, wherein:   3. The method of manufacturing a semiconductor device according to claim 2, wherein the support film opening pattern is exposed while being shifted by a half pitch in the multiple exposure to the portion where the defocus occurs.   3. The method of manufacturing a semiconductor device according to claim 2, wherein exposure is performed so that the mat area is larger than the mat area of the normal exposure portion in the multiple exposure to the portion where the defocus occurs.   An exposure mask having no support film opening pattern at the time of multiple exposure to the defocused portion, and having an exposure pattern having a large mat width in four directions left, right, up and down from the mat area of the normal exposure portion The method for manufacturing a semiconductor device according to claim 4, wherein exposure is performed using the semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 5, wherein an exposure pattern having a large mat width in four directions left, right, up and down from the mat area of the normal exposure portion is formed on an exposure mask for performing normal exposure.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the multiple exposure is performed by shifting the support film opening pattern by a half pitch in the four directions of left, right, up and down during the multiple exposure on the portion where the defocus occurs.