US20180040558A1 - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same Download PDF

Info

Publication number
US20180040558A1
US20180040558A1 US15/247,948 US201615247948A US2018040558A1 US 20180040558 A1 US20180040558 A1 US 20180040558A1 US 201615247948 A US201615247948 A US 201615247948A US 2018040558 A1 US2018040558 A1 US 2018040558A1
Authority
US
United States
Prior art keywords
gate
plug
protruding portion
central axis
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/247,948
Other versions
US9870996B1 (en
Inventor
Ching-Wen Hung
Chih-Sen Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, CHIH-SEN, HUNG, CHING-WEN
Application granted granted Critical
Publication of US9870996B1 publication Critical patent/US9870996B1/en
Publication of US20180040558A1 publication Critical patent/US20180040558A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including metal gates and plug structures and a method of fabricating the same.
  • CD critical dimension
  • the semiconductor devices with enhanced reliability may be obtained accordingly.
  • the device reliability of the semiconductor device may be effectively enhanced accordingly.
  • a method of fabricating a semiconductor device includes the following steps.
  • a substrate is provided first.
  • a plurality of gates are formed on the substrate.
  • the gates extend in a first direction, and the gates include a first gate and a second gate.
  • the first gate includes a first protruding portion, and the first protruding portion extends in a second direction.
  • a plurality of plugs are then formed parallel with one another on the substrate.
  • the plugs include a first plug and a second plug.
  • the first plug and the second plug cover the first gate and the second gate respectively.
  • a central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
  • the semiconductor device includes a substrate, a plurality of gates, and a plurality of plugs.
  • the gates are disposed on the substrate and extend in a first direction.
  • the gates include a first gate and a second gate.
  • the first gate includes a first protruding portion, and the first protruding portion extends in a second direction.
  • the plugs are disposed parallel with one another on the substrate.
  • the plugs include a first plug and a second plug.
  • the first plug and the second plug cover the first gate and the second gate respectively.
  • a central axis of the first plug is shifted from a central axis of the first gate toward the second direction
  • a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
  • protruding portions with different sizes are formed at the left side or the right side of each of the gates in accordance with shifting directions and shifting distance of the plugs formed subsequently for being electrically connected to the gates.
  • the coverage ratio of the plugs covering the corresponding gates may be enhanced, and the coverage ratio of the plugs may be higher than or equal to 70% accordingly.
  • FIG. 1 and FIG. 2 are schematic drawings illustrating a method of fabricating a semiconductor device according to a first embodiment of the present invention, wherein
  • FIG. 1 is a schematic drawing illustrating the method of fabricating the semiconductor device in a starting step
  • FIG. 2 a schematic drawing illustrating the method of fabricating the semiconductor device after the step of forming plugs.
  • FIG. 3 is a top-view schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 4 is schematic drawing illustrating a semiconductor device in an actual circuit layout according to a preferred embodiment of the present invention.
  • FIG. 5 is a cross-sectional diagram taken along a line A-A′ and in FIG. 4 .
  • FIG. 1 and FIG. 2 are schematic drawings illustrating a method of fabricating a semiconductor device according to a first embodiment of the present invention.
  • a substrate 300 is provided.
  • the substrate 300 may be a silicon substrate, an epitaxial silicon substrate, or silicon on insulation (SOI) substrate, for example.
  • a plurality of gates 340 are formed on the substrate 300 .
  • At least one fin structure 301 and one insulation layer 302 may be selectively formed on the substrate 300 first.
  • the fin structure 301 may extend in a second direction D 2 , such as an x direction, and the gate 340 is then formed on the fin structure 301 and straddling the fin structure 301 .
  • the fin structure 301 may be formed by a spacer self-aligned double-patterning (SADP) approach, for example.
  • SADP spacer self-aligned double-patterning
  • a patterned material (not shown) may be formed on the substrate 300 , the patterns of the patterned mask may be transferred to the substrate 300 by an etching process for forming a plurality of trenches (not shown) in the substrate 300 , and the patterned mask is removed.
  • the insulation layer 302 is formed in the trenches, a part of the substrate 300 protruding from the insulation layer 302 becomes the fin structure 301 , and the insulation layer 302 becomes a shallow trench isolation (STI).
  • STI shallow trench isolation
  • at least one shallow trench isolation may be formed on a planar substrate (not shown) for defining different active areas (AA, not shown), and gates (not shown) may be formed directly on the planar substrate and straddling the active areas.
  • the method of forming the gates 340 may include the following steps for example.
  • a plurality of dummy gates may be formed on the substrate 300 , and a replacement metal gate (RMG) may then be performed for forming the gates 340 .
  • RMG replacement metal gate
  • the gates 340 may also be formed directly on the substrate 300 in some embodiments.
  • the gates 340 are aligned parallel to one another in a first direction D 1 (such as a y direction) perpendicular to the second direction D 2 , and the gates 340 are disposed bilateral symmetric with respect to a symmetry axis V, as shown in FIG. 1 .
  • Two outmost gates 340 are used to be dummy gates for example, but not limited thereto.
  • the gates 341 and 343 disposed between the symmetry axis V and the dummy gate disposed at one side (such as the right side) of the symmetry axis V may additionally include protruding portions 342 and 344 . As shown in FIG.
  • the protruding portions 342 and 344 extend from the right sides of the gates 341 and 343 toward the second direction D 2 respectively.
  • the protruding portion 342 of the gate 341 extends in the second direction D 2 , and a length L 1 of the protruding portion 342 in the second direction D 2 may be about 1-3 nanometers for example.
  • the protruding portion 344 of the gate 343 may have a ladder-shaped structure with a length L 2 , and the length L 2 may be about 2-6 nanometers for example.
  • the dimension of the protruding portion 342 may range between one fifth of the dimension of the gate 341 and one tenth of the dimension of the gate 341
  • the protruding portion 344 includes a first part 344 a protruding from a sidewall of the gate 343 and a second part 344 b protruding from a sidewall of the first part 344 a
  • the total dimension of the first part 344 a may range between one fifth of the total dimension of the gate 343 and one tenth of the total dimension of the gate 343
  • the length of the first part 344 a in the second direction D 2 may be equal to the length L 1 of the protruding portion 342 preferably.
  • the total dimension of the second part 344 b may range between one tenth of the total dimension of the gate 343 and one twentieth of the total dimension of the gate 343 , and the length of the second part 344 a in the first direction D 1 may be less the length of the first part 344 a preferably for avoiding too much stress on the gates 341 and 343 .
  • the gates 345 and 347 disposed between the symmetry axis V and the dummy gate disposed at another side (such as the left side) of the symmetry axis V may additionally include protruding portions 346 and 348 .
  • the protruding portions 346 and 348 extend from the left sides of the gates 345 and 347 toward a third direction D 3 away from the second direction D 2 respectively.
  • a length L 3 of the protruding portion 346 of the gate 345 in the third direction D 3 may be about 1-3 nanometers for example.
  • the protruding portion 348 of the gate 347 may have a ladder-shaped structure with a length L 4 , and the length L 4 may be about 2-6 nanometers for example.
  • the dimension of the protruding portion 346 may range between one fifth of the dimension of the gate 345 and one tenth of the dimension of the gate 345
  • the protruding portion 348 includes a first part 348 a protruding from a sidewall of the gate 347 and a second part 348 b protruding from a sidewall of the first part 348 a
  • the total dimension of the first part 348 a may range between one fifth of the total dimension of the gate 347 and one tenth of the total dimension of the gate 347
  • the length of the first part 348 a in the third direction D 3 may be equal to the length L 3 of the protruding portion 346 preferably.
  • the total dimension of the second part 348 b may range between one tenth of the total dimension of the gate 347 and one twentieth of the total dimension of the gate 347 , and the length of the second part 348 a in the first direction D 1 may be less the length of the first part 348 a preferably for avoiding too much stress on the gates 345 and 347 .
  • a plurality of plugs 380 are then formed to be electrically connected to the metal gates.
  • the plugs 380 are formed in an interlayer dielectric layer (ILD) above the gates 340 .
  • the method of forming the plugs 380 may include the following steps for example.
  • a patterned mask such as a patterned photoresist layer (not shown) may be formed on the interlayer dielectric layer first, and an etching process, such as a dry etching process, using the patterned photoresist layer as an etching mask is then performed for forming a plurality of contact holes (not shown) penetrating the interlayer dielectric layer and exposing the metal gates of the gates 340 .
  • a cleaning process may be optionally performed, and surfaces of the contact holes mentioned above may be cleaned by argon (Ar) in the cleaning process for removing residues of the etching process.
  • argon Ar
  • a silicide process and a contact plug process may be performed sequentially for forming the plugs 380 in the contact holes.
  • the plugs 380 are formed above the gates 340 .
  • the plugs 380 cover the gates 341 , 343 , 345 , and 347 and the protruding portions 342 , 344 , 346 , and 348 in a projective direction perpendicular to the substrate 300 respectively, and the plugs 380 cover a central axis G 1 of the gate 341 , a central axis G 2 of the gate 343 , a central axis G 3 of the gate 345 , and a central axis G 4 of the gate 347 preferably.
  • the plugs 380 are formed on an identical horizontal axis H preferably, and the plugs 380 are also aligned bilateral symmetric with respect to the symmetry axis V, as shown in FIG. 2 .
  • the plugs 381 and 383 disposed at the right side of the symmetry axis V may have a central axis P 1 and a central axis P 2 in the first direction D 1 respectively.
  • the central axes P 1 and P 2 of the plugs 381 and 383 are shifted from the central axes G 1 and G 2 of the gates 341 and 343 respectively and shifted toward the second direction D 2 .
  • the shifting direction of the central axes P 1 and P 2 of the plugs 381 and 383 is identical to the extending direction of the protruding portions 342 and 344 of the gates 341 and 343 . Accordingly, the plugs 381 and 383 may completely cover the gates 341 and 343 and the protruding portions 342 and 344 underneath the plugs 381 and 383 . It is worth noting that a shifting distance S 2 between the central axis P 2 of the plug 383 and the central axis G 2 of the gate 343 will be larger than a shifting distance S 1 between the central axis P 1 of the plug 381 and the central axis G 1 of the gate 341 .
  • the length L 2 and the dimension of the protruding portion 344 of the gate 343 is larger than the length L 1 and the dimension of the protruding portion 342 for ensuring that the coverage ratio of the plug 383 on the corresponding gate 343 may be higher than or equal to a specific level, such as about 70%.
  • the plugs 385 and 387 disposed at the left side of the symmetry axis V may have a central axis P 3 and a central axis P 4 in the first direction D 1 respectively.
  • the central axes P 3 and P 4 of the plugs 385 and 387 are shifted from the central axes G 3 and G 4 of the gates 345 and 347 respectively and shifted toward the third direction D 3 .
  • the shifting direction of the central axes P 3 and P 4 of the plugs 385 and 387 is identical to the extending direction of the protruding portions 346 and 348 of the gates 345 and 347 .
  • the plugs 385 and 387 may completely cover the gates 345 and 347 and the protruding portions 346 and 348 underneath the plugs 385 and 387 . It is worth noting that a shifting distance S 4 between the central axis P 4 of the plug 387 and the central axis G 4 of the gate 347 will be larger than a shifting distance S 3 between the central axis P 3 of the plug 385 and the central axis G 3 of the gate 345 .
  • the length L 4 and the dimension of the protruding portion 348 of the gate 347 is larger than the length L 3 and the dimension of the protruding portion 346 for ensuring that the coverage ratio of the plug 387 on the corresponding gate 347 may be higher than or equal to a specific level, such as about 70%.
  • the semiconductor device in the first preferred embodiment is formed.
  • the gates 340 and the plugs 380 are formed sequentially on the substrate 300 .
  • the gates 340 and the plugs 380 are aligned bilateral symmetric with respect to the symmetry axis V on the substrate 300 .
  • the gates 340 may be formed by a spacer self-aligned double-patterning approach, for example, and the pitch between the gates 340 may be relatively small.
  • the plugs 380 formed subsequently may be formed by a normal photolithography process, and the pitch between the plugs 380 may be relatively large accordingly.
  • the protruding portions 342 and 344 and the protruding portions 346 and 348 are formed at the right side of the gates 341 and 343 disposed at the right side of the symmetry axis V and at the left side of the gates 345 and 347 disposed at the left side of the symmetry axis V respectively in accordance with the shifting directions D 2 and D 3 and the shifting distances S 1 , S 2 , S 3 , and S 4 of the plugs 380 formed subsequently.
  • the process window may become larger at the protruding portion 342 of the gate 341 , the protruding portion 344 of the gate 343 , the protruding portion 346 of the gate 345 , and the protruding portion 348 of the gate 347 . Accordingly, in the semiconductor device, the coverage ratio of the plugs 380 on the gates 340 may become higher, and the coverage ratio may be higher than or equal to 70% preferably. Additionally, the dimension and the structure of the protruding portions 342 , 344 , 346 , and 348 may be modified in accordance with the shifting distances S 1 , S 2 , S 3 , and S 4 .
  • the protruding portions 344 and 348 may have a ladder-shape structure respectively, the length L 2 of the protruding portion 344 may be larger than the length L 1 of the protruding portion 342 , and the length L 4 of the protruding portion 348 may be larger than the length L 3 of the protruding portion 346 .
  • the lengths and the extending directions of the protruding portions of the gates are adjusted in accordance with the positions of the plugs formed subsequently or the actual process conditions, and the protruding portion is not limited to the embodiments described above.
  • other gates may be formed at the right side of the gate 343
  • protruding portions (not shown), which may be similar to the protruding portion of the gate 343 , having ladder-shaped structures and extending in the second direction D 2 may be formed on the gates.
  • the protruding portion may have a length larger than the length L 2 of the protruding portion 344 in the second direction D 2 .
  • the protruding portion may be composed of the first part, the second part, and a third part (not shown), or may be composed of the first part, the second part, the third part, and the fourth part (not shown).
  • Other gates may be formed at the left side of the gate 347 , and protruding portions (not shown), which may be similar to the protruding portion of the gate 347 , having ladder-shaped structures and extending in the third direction D 3 may be formed on the gates.
  • the protruding portion may have a length larger than the length L 4 of the protruding portion 348 in the third direction D 3 .
  • the protruding portion may be composed of the first part, the second part, and a third part (not shown), or may be composed of the first part, the second part, the third part, and the fourth part (not shown), but not limited thereto.
  • FIG. 3 is a top-view schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention.
  • the semiconductor device in this embodiment is substantially similar to the semiconductor device shown in FIG. 2 in the first embodiment and will not be redundantly described.
  • the difference between this embodiment and the embodiment mentioned above is that the semiconductor device of this embodiment further includes a gate 349 disposed on the symmetry axis V and a plug 389 covering the gate 349 .
  • the gate 349 is disposed between the gate 341 and the gate 345 .
  • the plug 389 formed above the gate 349 completely covers the gate 349 , and a central axis P 5 of the plug 389 and a central axis G 5 of the gate 349 are both corresponding to the symmetry axis V.
  • the central axis P 5 of the plug 389 overlaps the central axis G 5 of the gate 349 , and the coverage ratio of the plug 389 on the gate 349 is 100%. Therefore, there is no need to form a protruding portion on the gate 349 .
  • the central axes P 1 and P 2 of the plugs 381 and 383 disposed on the right side of the symmetry axis V will be shifted toward the second direction D 2 , and the gates 341 and 343 disposed under the plugs 381 and 383 have the protruding portions 342 and 344 extending toward the second direction D 2 for ensuring that the coverage ratio of the plugs 381 and 383 covering the gates 341 and 343 respectively may be larger than or equal to 70%.
  • the shifting distance S 2 between the central axis P 2 of the plug 383 and the central axis G 2 of the gate 343 is larger than the shifting distance S 1 between the central axis P 1 of the plug 381 and the central axis G 1 of the gate 341 , the length of the protruding portion 344 of the gate 343 is larger than the length of the protruding portion 342 of the gate 341 , as shown in FIG. 3 .
  • the central axes P 3 and P 3 of the plugs 385 and 387 disposed on the left side of the symmetry axis V will be shifted toward the third direction D 3
  • the gates 345 and 347 disposed under the plugs 385 and 387 have the protruding portions 346 and 348 extending toward the third direction D 3 for ensuring that the coverage ratio of the plugs 385 and 387 covering the gates 345 and 347 respectively may be larger than or equal to 70%.
  • the shifting distance S 4 between the central axis P 4 of the plug 387 and the central axis G 4 of the gate 347 is larger than the shifting distance S 3 between the central axis P 3 of the plug 385 and the central axis G 3 of the gate 345
  • the length of the protruding portion 348 of the gate 347 is larger than the length of the protruding portion 346 of the gate 345 , as shown in FIG. 3 .
  • the protruding portions with different dimensions are formed at the left side or the right side of each of the gates in accordance with the shifting directions and the shifting distances of the plugs formed subsequently for being electrically connected to the gates.
  • the coverage ratio of the plugs covering the corresponding gates may be enhanced.
  • the coverage ratio of the plugs may be higher than or equal to 70%, and the process window is also enhanced accordingly.
  • the lengths and the extending directions of the protruding portions of the gates may also be adjusted in accordance with the shifting distances of the plugs, and the protruding portion may have a ladder-shaped structure and a dimension increasing progressively.
  • the protruding portion may be composed of the first part; be composed of the first part and the second part; be composed of the first part, the second part, and the third part; or be composed of the first part, the second part . . . and the N th part.
  • the first part, the second part . . . and the N th part are smaller than the dimension of the gate for avoiding too much stress on the gate.
  • each of the parts mentioned above should have a length at least larger than or equal to the length of the plug in a direction parallel to the gate for ensuring that the coverage ratio of the plug covering the corresponding gate may be higher than or equal to a specific level.
  • FIG. 4 and FIG. 5 are schematic drawings illustrating a semiconductor device in an actual circuit layout according to a preferred embodiment of the present invention.
  • the semiconductor device includes a plurality of the gates 340 straddling the fin structure 301 .
  • each of the gates 340 is specifically composed of a high dielectric constant dielectric layer 311 , a work function layer 332 , a metal conductive layer 333 , and a capping layer 334 stacked on the substrate 300 sequentially, a spacer 335 disposed on two sides of the stacked layers, and a source/drain region 336 formed in the fin structure 301 .
  • the work function layer 332 may include materials such as tantalum nitride (TaN), titanium nitride (TiN), titanium aluminides (TiAl), or aluminum zirconium (ZrAl), for example.
  • the metal conductive layer 333 may include materials such as tungsten (W) or aluminum (Al) for forming a metal gate of each of the gates 340 , for example.
  • the capping layer 334 may include materials such as silicon nitride (SiN) or silicon carbon nitride (SiCN).
  • the spacer 335 may be a single layer or a multiple layer structure selectively, and the spacer 335 may include materials with high etching resistance and great coverage ability, such as high temperature oxide (HTO), silicon nitride, silicon oxide, silicon oxynitride, or HCD-SiN formed by hexachlorodisilane (Si 2 Cl 6 ), but not limited thereto.
  • HTO high temperature oxide
  • Si 2 Cl 6 hexachlorodisilane
  • the semiconductor device further includes a plurality of contact slots 360 electrically connected to source/drain regions 336 of the gates 340 and a plurality of the plugs 380 electrically connected to the metal gates.
  • the plugs 380 and the contact slots 360 are disposed in an interlayer dielectric layer 200 .
  • the contact slots 360 and the plugs 380 may be formed together in the same interlayer dielectric layer 200 by one identical photolithography process, or the plugs 380 may also be formed after the step of forming the contact slots 360 at two sides of the gate 340 .
  • the contact slot 360 may be an extending stripe parallel to an extending direction of the gate 340 (i.e. the first direction D 1 ) preferably.
  • the stripe contact slot 360 in this embodiment extends above the source/drain region 336 for increasing the contact area between the contact slot 360 and the source/drain region 336 .
  • at least one slot cut pattern may be formed before the step of forming the contact slots 360 in advance for cutting some of the extending stripes of the contact slots 360 into a part 360 a and a part 360 b (as shown in FIG. 4 ). It should be realized easily for those skilled in the related field that the layout patterns, and the dimensions, the shapes, and the amounts of the plugs and the contact slots may be further modified in accordance with the process requirements and are not limited to the conditions described above. In some embodiments, a single opening may also be formed selectively.
  • the plugs 380 cover the gates 341 and 343 , and the plugs 380 are shifted slightly toward the second direction D 2 . Accordingly, the protruding portions 342 and 344 extending in the second direction D 2 are formed on the gates 341 and 343 respectively for ensuring that the coverage ratio of the plugs 381 and 383 covering the gates 341 and 343 may be larger than or equal to a specific level, such as about 70%. Additionally, the shifting distance of the plug 383 is larger than the shifting distance of the plug 381 . Therefore, as shown in FIG.
  • the protruding portion 344 of the gate 343 has a ladder-shape structure, and the length and the dimension of the protruding portion 344 is larger than those of the protruding portion 342 for ensuring that the plug 383 contacts the metal gate truly.
  • the protruding portions with different dimensions are formed at the left side or the right side of each of the gates in accordance with the shifting directions and the shifting distances of the plugs formed subsequently for being electrically connected to the gates.
  • the coverage ratio of the plugs covering the corresponding gates may be enhanced.
  • the coverage ratio of the plugs may be higher than or equal to 70%, and the process window of the plugs may also be enhanced accordingly.

Abstract

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion extending in a second direction. The plugs are disposed parallel to one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including metal gates and plug structures and a method of fabricating the same.
    • 2. Description of the Prior Art
  • With the trend towards scaling down the critical dimension (CD) in semiconductor processes, conventional arts are miniaturizing the size of semiconductor devices, but have faced many problems in the integrated process of the semiconductor structure including metal gates, especially when the CD is miniaturized to a certain degree.
  • In order for a miniaturized semiconductor device to achieve a highly integrated and high-speed operation, conventional arts utilize miniaturized through holes and inter-layer dielectric layers to form a multilayered interconnected wiring structure for being electrically connected to the metal gate and the source/drain of the transistor respectively and being the input/output ends for imported electrical signals. However, conventional arts still face many problems in the integrated process of the metal gates and other units, such as contact plugs, because of optical limitations. For example, the entire electric performance of the semiconductor device will be seriously affected when the contact plugs for being electrically connected to the gates and the source/drain regions are not formed properly at the predetermined locations. Accordingly, it is very important to figure out the ways for improving the manufacturing process and the structure of the semiconductor devices.
    • SUMMARY OF THE INVENTION
  • It is one of the objectives of the present invention to provide a method of fabricating a semiconductor device for optimizing the dispositions of the plugs and the metal gates effectively. The semiconductor devices with enhanced reliability may be obtained accordingly.
  • It is one of the objectives of the present invention to provide a semiconductor device, and a coverage ratio between each plug and a corresponding metal gate in the semiconductor device may be higher than or equal to 70%. The device reliability of the semiconductor device may be effectively enhanced accordingly.
  • To achieve the purposes described above, a method of fabricating a semiconductor device is provided in one embodiment of the present invention. The method includes the following steps. A substrate is provided first. A plurality of gates are formed on the substrate. The gates extend in a first direction, and the gates include a first gate and a second gate. The first gate includes a first protruding portion, and the first protruding portion extends in a second direction. A plurality of plugs are then formed parallel with one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
  • To achieve the purposes described above, a semiconductor device is provided in one embodiment of the present invention. The semiconductor device includes a substrate, a plurality of gates, and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion, and the first protruding portion extends in a second direction. The plugs are disposed parallel with one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
  • In the method of forming the semiconductor device of the present invention, protruding portions with different sizes are formed at the left side or the right side of each of the gates in accordance with shifting directions and shifting distance of the plugs formed subsequently for being electrically connected to the gates. The coverage ratio of the plugs covering the corresponding gates may be enhanced, and the coverage ratio of the plugs may be higher than or equal to 70% accordingly.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 and FIG. 2 are schematic drawings illustrating a method of fabricating a semiconductor device according to a first embodiment of the present invention, wherein
  • FIG. 1 is a schematic drawing illustrating the method of fabricating the semiconductor device in a starting step; and
  • FIG. 2 a schematic drawing illustrating the method of fabricating the semiconductor device after the step of forming plugs.
  • FIG. 3 is a top-view schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 4 is schematic drawing illustrating a semiconductor device in an actual circuit layout according to a preferred embodiment of the present invention.
  • FIG. 5 is a cross-sectional diagram taken along a line A-A′ and in FIG. 4.
    •  DETAILED DESCRIPTION
  • To provide a better understanding of the present invention to users skilled in the technology of the present invention, embodiments are detailed as follows. The embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and effects to be achieved.
  • Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic drawings illustrating a method of fabricating a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, a substrate 300 is provided. The substrate 300 may be a silicon substrate, an epitaxial silicon substrate, or silicon on insulation (SOI) substrate, for example. A plurality of gates 340 are formed on the substrate 300.
  • In this embodiment, at least one fin structure 301 and one insulation layer 302 may be selectively formed on the substrate 300 first. The fin structure 301 may extend in a second direction D2, such as an x direction, and the gate 340 is then formed on the fin structure 301 and straddling the fin structure 301. The fin structure 301 may be formed by a spacer self-aligned double-patterning (SADP) approach, for example. A patterned material (not shown) may be formed on the substrate 300, the patterns of the patterned mask may be transferred to the substrate 300 by an etching process for forming a plurality of trenches (not shown) in the substrate 300, and the patterned mask is removed. Subsequently, the insulation layer 302 is formed in the trenches, a part of the substrate 300 protruding from the insulation layer 302 becomes the fin structure 301, and the insulation layer 302 becomes a shallow trench isolation (STI). In other embodiments, for forming planar transistors without fin structures, at least one shallow trench isolation (not shown) may be formed on a planar substrate (not shown) for defining different active areas (AA, not shown), and gates (not shown) may be formed directly on the planar substrate and straddling the active areas. In some embodiments, the method of forming the gates 340 may include the following steps for example. A plurality of dummy gates (not shown) may be formed on the substrate 300, and a replacement metal gate (RMG) may then be performed for forming the gates 340. However, it should be realized for those skilled in the related field that the gates 340 may also be formed directly on the substrate 300 in some embodiments.
  • Specifically, the gates 340 are aligned parallel to one another in a first direction D1 (such as a y direction) perpendicular to the second direction D2, and the gates 340 are disposed bilateral symmetric with respect to a symmetry axis V, as shown in FIG. 1. Two outmost gates 340 are used to be dummy gates for example, but not limited thereto. It is worth noting that the gates 341 and 343 disposed between the symmetry axis V and the dummy gate disposed at one side (such as the right side) of the symmetry axis V may additionally include protruding portions 342 and 344. As shown in FIG. 1, the protruding portions 342 and 344 extend from the right sides of the gates 341 and 343 toward the second direction D2 respectively. The protruding portion 342 of the gate 341 extends in the second direction D2, and a length L1 of the protruding portion 342 in the second direction D2 may be about 1-3 nanometers for example. The protruding portion 344 of the gate 343 may have a ladder-shaped structure with a length L2, and the length L2 may be about 2-6 nanometers for example. In detail, the dimension of the protruding portion 342 may range between one fifth of the dimension of the gate 341 and one tenth of the dimension of the gate 341, and the protruding portion 344 includes a first part 344 a protruding from a sidewall of the gate 343 and a second part 344 b protruding from a sidewall of the first part 344 a. The total dimension of the first part 344 a may range between one fifth of the total dimension of the gate 343 and one tenth of the total dimension of the gate 343, and the length of the first part 344 a in the second direction D2 may be equal to the length L1 of the protruding portion 342 preferably. The total dimension of the second part 344 b may range between one tenth of the total dimension of the gate 343 and one twentieth of the total dimension of the gate 343, and the length of the second part 344 a in the first direction D1 may be less the length of the first part 344 a preferably for avoiding too much stress on the gates 341 and 343.
  • Additionally, the gates 345 and 347 disposed between the symmetry axis V and the dummy gate disposed at another side (such as the left side) of the symmetry axis V may additionally include protruding portions 346 and 348. As shown in FIG. 1, the protruding portions 346 and 348 extend from the left sides of the gates 345 and 347 toward a third direction D3 away from the second direction D2 respectively. A length L3 of the protruding portion 346 of the gate 345 in the third direction D3 may be about 1-3 nanometers for example. The protruding portion 348 of the gate 347 may have a ladder-shaped structure with a length L4, and the length L4 may be about 2-6 nanometers for example. In detail, the dimension of the protruding portion 346 may range between one fifth of the dimension of the gate 345 and one tenth of the dimension of the gate 345, and the protruding portion 348 includes a first part 348 a protruding from a sidewall of the gate 347 and a second part 348 b protruding from a sidewall of the first part 348 a. The total dimension of the first part 348 a may range between one fifth of the total dimension of the gate 347 and one tenth of the total dimension of the gate 347, and the length of the first part 348 a in the third direction D3 may be equal to the length L3 of the protruding portion 346 preferably. The total dimension of the second part 348 b may range between one tenth of the total dimension of the gate 347 and one twentieth of the total dimension of the gate 347, and the length of the second part 348 a in the first direction D1 may be less the length of the first part 348 a preferably for avoiding too much stress on the gates 345 and 347.
  • As shown in FIG. 2, a plurality of plugs 380 (may also be referred as contact plugs) are then formed to be electrically connected to the metal gates. The plugs 380 are formed in an interlayer dielectric layer (ILD) above the gates 340. Specifically, the method of forming the plugs 380 may include the following steps for example. A patterned mask, such as a patterned photoresist layer (not shown), may be formed on the interlayer dielectric layer first, and an etching process, such as a dry etching process, using the patterned photoresist layer as an etching mask is then performed for forming a plurality of contact holes (not shown) penetrating the interlayer dielectric layer and exposing the metal gates of the gates 340. After the step of removing the patterned photoresist layer, a cleaning process may be optionally performed, and surfaces of the contact holes mentioned above may be cleaned by argon (Ar) in the cleaning process for removing residues of the etching process. Subsequently, a silicide process and a contact plug process may be performed sequentially for forming the plugs 380 in the contact holes.
  • The plugs 380 are formed above the gates 340. The plugs 380 cover the gates 341, 343, 345, and 347 and the protruding portions 342, 344, 346, and 348 in a projective direction perpendicular to the substrate 300 respectively, and the plugs 380 cover a central axis G1 of the gate 341, a central axis G2 of the gate 343, a central axis G3 of the gate 345, and a central axis G4 of the gate 347 preferably. In this embodiment, the plugs 380 are formed on an identical horizontal axis H preferably, and the plugs 380 are also aligned bilateral symmetric with respect to the symmetry axis V, as shown in FIG. 2. Specifically, the plugs 381 and 383 disposed at the right side of the symmetry axis V may have a central axis P1 and a central axis P2 in the first direction D1 respectively. As shown in FIG. 2, the central axes P1 and P2 of the plugs 381 and 383 are shifted from the central axes G1 and G2 of the gates 341 and 343 respectively and shifted toward the second direction D2. However, it is worth noting that the shifting direction of the central axes P1 and P2 of the plugs 381 and 383 is identical to the extending direction of the protruding portions 342 and 344 of the gates 341 and 343. Accordingly, the plugs 381 and 383 may completely cover the gates 341 and 343 and the protruding portions 342 and 344 underneath the plugs 381 and 383. It is worth noting that a shifting distance S2 between the central axis P2 of the plug 383 and the central axis G2 of the gate 343 will be larger than a shifting distance S1 between the central axis P1 of the plug 381 and the central axis G1 of the gate 341. The length L2 and the dimension of the protruding portion 344 of the gate 343 is larger than the length L1 and the dimension of the protruding portion 342 for ensuring that the coverage ratio of the plug 383 on the corresponding gate 343 may be higher than or equal to a specific level, such as about 70%.
  • Similarly, the plugs 385 and 387 disposed at the left side of the symmetry axis V may have a central axis P3 and a central axis P4 in the first direction D1 respectively. As shown in FIG. 2, the central axes P3 and P4 of the plugs 385 and 387 are shifted from the central axes G3 and G4 of the gates 345 and 347 respectively and shifted toward the third direction D3. However, it is worth noting that the shifting direction of the central axes P3 and P4 of the plugs 385 and 387 is identical to the extending direction of the protruding portions 346 and 348 of the gates 345 and 347. Accordingly, the plugs 385 and 387 may completely cover the gates 345 and 347 and the protruding portions 346 and 348 underneath the plugs 385 and 387. It is worth noting that a shifting distance S4 between the central axis P4 of the plug 387 and the central axis G4 of the gate 347 will be larger than a shifting distance S3 between the central axis P3 of the plug 385 and the central axis G3 of the gate 345. The length L4 and the dimension of the protruding portion 348 of the gate 347 is larger than the length L3 and the dimension of the protruding portion 346 for ensuring that the coverage ratio of the plug 387 on the corresponding gate 347 may be higher than or equal to a specific level, such as about 70%.
  • Accordingly, the semiconductor device in the first preferred embodiment is formed. In the method of fabricating the semiconductor device of this embodiment, the gates 340 and the plugs 380 are formed sequentially on the substrate 300. The gates 340 and the plugs 380 are aligned bilateral symmetric with respect to the symmetry axis V on the substrate 300. The gates 340 may be formed by a spacer self-aligned double-patterning approach, for example, and the pitch between the gates 340 may be relatively small. The plugs 380 formed subsequently may be formed by a normal photolithography process, and the pitch between the plugs 380 may be relatively large accordingly. In this condition, the position of some of the plugs 380 cannot be corresponding to the position of the gates 340 completely, and the plugs covering the gates 380 will be shifted toward the left side or the right side of the symmetry axis V. However, in this embodiment, the protruding portions 342 and 344 and the protruding portions 346 and 348 are formed at the right side of the gates 341 and 343 disposed at the right side of the symmetry axis V and at the left side of the gates 345 and 347 disposed at the left side of the symmetry axis V respectively in accordance with the shifting directions D2 and D3 and the shifting distances S1, S2, S3, and S4 of the plugs 380 formed subsequently. Therefore, the process window may become larger at the protruding portion 342 of the gate 341, the protruding portion 344 of the gate 343, the protruding portion 346 of the gate 345, and the protruding portion 348 of the gate 347. Accordingly, in the semiconductor device, the coverage ratio of the plugs 380 on the gates 340 may become higher, and the coverage ratio may be higher than or equal to 70% preferably. Additionally, the dimension and the structure of the protruding portions 342, 344, 346, and 348 may be modified in accordance with the shifting distances S1, S2, S3, and S4. For example, the protruding portions 344 and 348 may have a ladder-shape structure respectively, the length L2 of the protruding portion 344 may be larger than the length L1 of the protruding portion 342, and the length L4 of the protruding portion 348 may be larger than the length L3 of the protruding portion 346.
  • It should be realized for those skilled in the related field that in the present invention, the lengths and the extending directions of the protruding portions of the gates are adjusted in accordance with the positions of the plugs formed subsequently or the actual process conditions, and the protruding portion is not limited to the embodiments described above. For example, in other embodiments, other gates (not shown) may be formed at the right side of the gate 343, and protruding portions (not shown), which may be similar to the protruding portion of the gate 343, having ladder-shaped structures and extending in the second direction D2 may be formed on the gates. The protruding portion may have a length larger than the length L2 of the protruding portion 344 in the second direction D2. For example, the protruding portion may be composed of the first part, the second part, and a third part (not shown), or may be composed of the first part, the second part, the third part, and the fourth part (not shown). Other gates (not shown) may be formed at the left side of the gate 347, and protruding portions (not shown), which may be similar to the protruding portion of the gate 347, having ladder-shaped structures and extending in the third direction D3 may be formed on the gates. The protruding portion may have a length larger than the length L4 of the protruding portion 348 in the third direction D3. For example, the protruding portion may be composed of the first part, the second part, and a third part (not shown), or may be composed of the first part, the second part, the third part, and the fourth part (not shown), but not limited thereto.
  • The following description will detail the different embodiments of the semiconductor device in the present invention. To simplify the description, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described. Additionally, identical components in each of the following embodiments are marked with identical symbols for comparing between the embodiments.
  • Please refer to FIG. 3. FIG. 3 is a top-view schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention. The semiconductor device in this embodiment is substantially similar to the semiconductor device shown in FIG. 2 in the first embodiment and will not be redundantly described. The difference between this embodiment and the embodiment mentioned above is that the semiconductor device of this embodiment further includes a gate 349 disposed on the symmetry axis V and a plug 389 covering the gate 349.
  • In this embodiment, the gate 349 is disposed between the gate 341 and the gate 345. As shown in FIG. 3, the plug 389 formed above the gate 349 completely covers the gate 349, and a central axis P5 of the plug 389 and a central axis G5 of the gate 349 are both corresponding to the symmetry axis V. In other words, the central axis P5 of the plug 389 overlaps the central axis G5 of the gate 349, and the coverage ratio of the plug 389 on the gate 349 is 100%. Therefore, there is no need to form a protruding portion on the gate 349. The central axes P1 and P2 of the plugs 381 and 383 disposed on the right side of the symmetry axis V will be shifted toward the second direction D2, and the gates 341 and 343 disposed under the plugs 381 and 383 have the protruding portions 342 and 344 extending toward the second direction D2 for ensuring that the coverage ratio of the plugs 381 and 383 covering the gates 341 and 343 respectively may be larger than or equal to 70%. Because the shifting distance S2 between the central axis P2 of the plug 383 and the central axis G2 of the gate 343 is larger than the shifting distance S1 between the central axis P1 of the plug 381 and the central axis G1 of the gate 341, the length of the protruding portion 344 of the gate 343 is larger than the length of the protruding portion 342 of the gate 341, as shown in FIG. 3. Similarly, the central axes P3 and P3 of the plugs 385 and 387 disposed on the left side of the symmetry axis V will be shifted toward the third direction D3, and the gates 345 and 347 disposed under the plugs 385 and 387 have the protruding portions 346 and 348 extending toward the third direction D3 for ensuring that the coverage ratio of the plugs 385 and 387 covering the gates 345 and 347 respectively may be larger than or equal to 70%. Because the shifting distance S4 between the central axis P4 of the plug 387 and the central axis G4 of the gate 347 is larger than the shifting distance S3 between the central axis P3 of the plug 385 and the central axis G3 of the gate 345, the length of the protruding portion 348 of the gate 347 is larger than the length of the protruding portion 346 of the gate 345, as shown in FIG. 3.
  • Accordingly, in the method of forming the semiconductor device of the present invention, the protruding portions with different dimensions are formed at the left side or the right side of each of the gates in accordance with the shifting directions and the shifting distances of the plugs formed subsequently for being electrically connected to the gates. The coverage ratio of the plugs covering the corresponding gates may be enhanced. The coverage ratio of the plugs may be higher than or equal to 70%, and the process window is also enhanced accordingly. Additionally, in the semiconductor device of the present invention, the lengths and the extending directions of the protruding portions of the gates may also be adjusted in accordance with the shifting distances of the plugs, and the protruding portion may have a ladder-shaped structure and a dimension increasing progressively. For example, the protruding portion may be composed of the first part; be composed of the first part and the second part; be composed of the first part, the second part, and the third part; or be composed of the first part, the second part . . . and the Nth part. The first part, the second part . . . and the Nth part are smaller than the dimension of the gate for avoiding too much stress on the gate. Additionally, each of the parts mentioned above should have a length at least larger than or equal to the length of the plug in a direction parallel to the gate for ensuring that the coverage ratio of the plug covering the corresponding gate may be higher than or equal to a specific level.
  • In addition, it should be realized easily for those skilled in the related field that the application field of the present invention is not limited to the embodiments described above where the plugs are disposed above the gates for describing the embodiments. In other embodiments of the present invention, the allocation relation may be different. For example, the gates may be disposed above the plugs or other required corresponding components, such as contact slots and conductive lines, may be formed for enhancing the coverage ratio and the process window of the manufacturing process. Please refer to FIG. 4 and FIG. 5. FIG. 4 and FIG. 5 are schematic drawings illustrating a semiconductor device in an actual circuit layout according to a preferred embodiment of the present invention. The semiconductor device includes a plurality of the gates 340 straddling the fin structure 301.
  • As shown in FIG. 5, each of the gates 340 is specifically composed of a high dielectric constant dielectric layer 311, a work function layer 332, a metal conductive layer 333, and a capping layer 334 stacked on the substrate 300 sequentially, a spacer 335 disposed on two sides of the stacked layers, and a source/drain region 336 formed in the fin structure 301. The work function layer 332 may include materials such as tantalum nitride (TaN), titanium nitride (TiN), titanium aluminides (TiAl), or aluminum zirconium (ZrAl), for example. The metal conductive layer 333 may include materials such as tungsten (W) or aluminum (Al) for forming a metal gate of each of the gates 340, for example. The capping layer 334 may include materials such as silicon nitride (SiN) or silicon carbon nitride (SiCN). The spacer 335 may be a single layer or a multiple layer structure selectively, and the spacer 335 may include materials with high etching resistance and great coverage ability, such as high temperature oxide (HTO), silicon nitride, silicon oxide, silicon oxynitride, or HCD-SiN formed by hexachlorodisilane (Si2Cl6), but not limited thereto.
  • The semiconductor device further includes a plurality of contact slots 360 electrically connected to source/drain regions 336 of the gates 340 and a plurality of the plugs 380 electrically connected to the metal gates. The plugs 380 and the contact slots 360 are disposed in an interlayer dielectric layer 200. In an embodiment, the contact slots 360 and the plugs 380 may be formed together in the same interlayer dielectric layer 200 by one identical photolithography process, or the plugs 380 may also be formed after the step of forming the contact slots 360 at two sides of the gate 340. The contact slot 360 may be an extending stripe parallel to an extending direction of the gate 340 (i.e. the first direction D1) preferably. In other words, the stripe contact slot 360 in this embodiment extends above the source/drain region 336 for increasing the contact area between the contact slot 360 and the source/drain region 336. However, in an embodiment, for avoiding the influence of the contact slot 360 on the process of forming the plugs 380, at least one slot cut pattern (not shown) may be formed before the step of forming the contact slots 360 in advance for cutting some of the extending stripes of the contact slots 360 into a part 360 a and a part 360 b (as shown in FIG. 4). It should be realized easily for those skilled in the related field that the layout patterns, and the dimensions, the shapes, and the amounts of the plugs and the contact slots may be further modified in accordance with the process requirements and are not limited to the conditions described above. In some embodiments, a single opening may also be formed selectively.
  • It is worth noting that the plugs 380 cover the gates 341 and 343, and the plugs 380 are shifted slightly toward the second direction D2. Accordingly, the protruding portions 342 and 344 extending in the second direction D2 are formed on the gates 341 and 343 respectively for ensuring that the coverage ratio of the plugs 381 and 383 covering the gates 341 and 343 may be larger than or equal to a specific level, such as about 70%. Additionally, the shifting distance of the plug 383 is larger than the shifting distance of the plug 381. Therefore, as shown in FIG. 5, the protruding portion 344 of the gate 343 has a ladder-shape structure, and the length and the dimension of the protruding portion 344 is larger than those of the protruding portion 342 for ensuring that the plug 383 contacts the metal gate truly.
  • Accordingly, in the present invention, the protruding portions with different dimensions are formed at the left side or the right side of each of the gates in accordance with the shifting directions and the shifting distances of the plugs formed subsequently for being electrically connected to the gates. The coverage ratio of the plugs covering the corresponding gates may be enhanced. The coverage ratio of the plugs may be higher than or equal to 70%, and the process window of the plugs may also be enhanced accordingly.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

1. A semiconductor device, comprising:
a substrate;
a plurality of gates disposed on the substrate and extending in a first direction, the gates being symmetric to each other with respect to a symmetry axis, wherein the gates comprise a first gate and a second gate both disposed at one side of the symmetry axis, the first gate comprises a first protruding portion and the second gate comprises a second protruding portion, and the first protruding portion and the second protruding portion both extend in a second direction, wherein the first protruding portion of the first gate which is away from the symmetry axis has a greater length than the second protruding portion of the second gate which is closed to the symmetry axis; and
a plurality of plugs disposed parallel with one another on the substrate, wherein the plugs comprise a first plug and a second plug, and the first plug and the second plug cover the first gate and the second gate respectively, wherein a central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
2. The semiconductor device of claim 1, wherein a first pitch between the gates is different from a second pitch between the plugs.
3. The semiconductor device of claim 2, wherein the second pitch between the plugs is larger than the first pitch between the gates.
4. The semiconductor device of claim 1, wherein the plugs are disposed on an identical horizontal axis.
5. The semiconductor device of claim 1, wherein a shifting distance between the central axis of the first plug and the central axis of the first gate is larger than a shifting distance between the central axis of the second plug and the central axis of the second gate.
6. (canceled)
7. The semiconductor device of claim 1, wherein the first protruding portion has a ladder-shaped structure.
8. The semiconductor device of claim 1, wherein the first protruding portion comprises a first part and a second part, and a length of the first part is equal to a length of the second protruding portion.
9. The semiconductor device of claim 1, wherein the gates further comprise a third gate and a fourth gate both disposed at an opposite side of the symmetry axis, and the plugs further comprise a third plug and a fourth plug covering the third gate and the fourth gate respectively, wherein a central axis of the third plug is shifted from a central axis of the third gate toward a third direction, a central axis of the fourth plug is shifted from a central axis of the fourth gate toward the third direction, and the third direction is opposite to the second direction.
10. The semiconductor device of claim 9, wherein a shifting distance between the central axis of the third plug and the central axis of the third gate is larger than a shifting distance between the central axis of the fourth plug and the central axis of the fourth gate.
11. The semiconductor device of claim 9, wherein the third gate comprises a third protruding portion extending in the third direction.
12. The semiconductor device of claim 11, wherein the third protruding portion has a ladder-shaped structure.
13. The semiconductor device of claim 11, wherein the fourth gate comprises a fourth protruding portion extending in the third direction, and a length of the fourth protruding portion is less than a length of the third protruding portion.
14. The semiconductor device of claim 13, wherein the third protruding portion comprises a third part and a fourth part, and a length of the third part is equal to the length of the fourth protruding portion.
15. The semiconductor device of claim 1, wherein the gates further comprises a fifth gate, and the plugs further comprises a fifth plug covering the fifth gate, wherein a central axis of the fifth gate overlaps a central axis of the fifth plug.
16. A semiconductor device, comprising:
a substrate;
a plurality of gates disposed on the substrate and extending in a first direction, the gates being symmetric to each other with respect to a symmetry axis, wherein the gates comprise:
a first gate, disposed at one side of the symmetry axis, wherein the first gate comprises a first protruding portion, and the first protruding portion extends in a second direction, and
a third gate disposed at an opposite side of the symmetry axis, wherein the third gate comprises a third protruding portion, the third protruding portion extends in a third direction away from the second direction, and the first protruding portion and the third protruding portion are symmetric to each other with respect to the symmetry axis; and
a plurality of plugs disposed parallel with one another on the substrate, wherein the plugs comprise a first plug and a third plug, and the first plug and the third plug cover the first gate and the third gate respectively, wherein a central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the third plug is shifted from a central axis of the third gate toward the third direction.
17. The semiconductor device of claim 16, wherein a first pitch between the gates is smaller than a second pitch between the plugs.
18. The semiconductor device of claim 16, wherein the plugs are disposed on an identical horizontal axis.
19. The semiconductor device of claim 16, wherein the first protruding portion and the third protruding portion have a ladder-shaped structure.
20. A method of fabricating a semiconductor device, comprising:
providing a substrate;
forming a plurality of gates on the substrate, wherein the gates extend in a first direction, and the gates comprise a first gate and a second gate, wherein the first gate comprises a first protruding portion, and the first protruding portion extends in a second direction; and
forming a plurality of plugs parallel with one another on the substrate, wherein the plugs comprise a first plug and a second plug, and the first plug and the second plug cover the first gate and the second gate respectively, wherein a central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
US15/247,948 2016-08-08 2016-08-26 Semiconductor device and method of fabricating the same Active US9870996B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201610640986.8A CN107706233B (en) 2016-08-08 2016-08-08 Semiconductor element and manufacturing method thereof
CN201610640986 2016-08-08
CN201610640986.8 2016-08-08

Publications (2)

Publication Number Publication Date
US9870996B1 US9870996B1 (en) 2018-01-16
US20180040558A1 true US20180040558A1 (en) 2018-02-08

Family

ID=60935046

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/247,948 Active US9870996B1 (en) 2016-08-08 2016-08-26 Semiconductor device and method of fabricating the same

Country Status (2)

Country Link
US (1) US9870996B1 (en)
CN (2) CN107706233B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210167071A1 (en) * 2018-08-29 2021-06-03 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device
DE102019124526B4 (en) 2018-10-31 2023-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Design process for a manufacturing process for a semiconductor component

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416296B (en) * 2018-04-26 2021-03-26 苏州能讯高能半导体有限公司 Semiconductor device, semiconductor chip and semiconductor device manufacturing method

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030107094A1 (en) * 2001-12-11 2003-06-12 Ji-Young Kim Transistor structures having access gates with narrowed central portions
US20040127050A1 (en) * 2002-12-10 2004-07-01 Samsung Electronics Co., Ltd Method for manufacturing semiconductor device with contact body extended in direction of bit line
US20070241365A1 (en) * 2006-04-12 2007-10-18 Renesas Technology Corp. Semiconductor integrated circuit device
US20090085118A1 (en) * 2007-09-27 2009-04-02 Ji-Ho Hong Semiconductor memory device
US20130021839A1 (en) * 2010-05-21 2013-01-24 Panasonic Corporation Semiconductor memory
US20130037888A1 (en) * 2011-08-10 2013-02-14 Samsung Electronics Co., Ltd. Semiconductor device
US20130113112A1 (en) * 2010-10-26 2013-05-09 Panasonic Corporation Semiconductor device
US20130329487A1 (en) * 2012-06-08 2013-12-12 Renesas Electronics Corporation Semiconductor device
US20140035056A1 (en) * 2012-07-31 2014-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM Cell Connection Structure
US20140241027A1 (en) * 2013-02-25 2014-08-28 United Microelectronics Corp. Static random access memory unit cell structure and static random access memory unit cell layout structure
US20140252653A1 (en) * 2008-04-25 2014-09-11 Panasonic Corporation Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
US20160307882A1 (en) * 2015-04-16 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device layout, semiconductor device, and method of manufacturing memory device
US20170018302A1 (en) * 2015-07-15 2017-01-19 United Microelectronics Corp. Static random access memory unit structure and static random access memory layout structure

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194772B1 (en) * 1999-05-12 2001-02-27 United Microelectronics Corp. High-voltage semiconductor device with trench structure
JP2006216809A (en) * 2005-02-04 2006-08-17 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
KR100729122B1 (en) * 2005-12-29 2007-06-14 동부일렉트로닉스 주식회사 Transistor of semiconductor device and method for fabricating the same
JP5122762B2 (en) * 2006-03-07 2013-01-16 株式会社東芝 Power semiconductor device, manufacturing method thereof, and driving method thereof
JP5057739B2 (en) 2006-10-03 2012-10-24 株式会社東芝 Semiconductor memory device
KR101576033B1 (en) * 2008-08-19 2015-12-11 삼성전자주식회사 A precursor composition method of forming a layer method of manufacturing a gate structure and method of manufacturing a capacitor
JP5110153B2 (en) * 2010-11-08 2012-12-26 住友電気工業株式会社 Semiconductor device and manufacturing method thereof
JP2012104694A (en) * 2010-11-11 2012-05-31 Toshiba Corp Semiconductor memory device
JP2012182229A (en) * 2011-02-28 2012-09-20 Sumitomo Bakelite Co Ltd Semiconductor device manufacturing method, insulation film and semiconductor device
KR20230057484A (en) * 2011-12-22 2023-04-28 인텔 코포레이션 Semiconductor structure
TWI463663B (en) * 2011-12-30 2014-12-01 Ind Tech Res Inst Semiconductor device and method of forming the same
KR101979752B1 (en) * 2012-05-03 2019-05-17 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
CN104051614A (en) * 2013-03-15 2014-09-17 联华电子股份有限公司 Embedded resistor
CN111554659B (en) * 2013-03-29 2022-05-24 联华电子股份有限公司 Plug structure and manufacturing process thereof
CN104701150B (en) * 2013-12-05 2018-08-10 中芯国际集成电路制造(上海)有限公司 The forming method of transistor
CN104752502A (en) * 2013-12-30 2015-07-01 中芯国际集成电路制造(上海)有限公司 Metal-oxide -semiconductor (MOS) transistor and forming method thereof
CN104810369B (en) * 2014-01-23 2019-01-08 联华电子股份有限公司 The semiconductor structure and layout structure of memory component
CN105097649B (en) * 2014-05-04 2017-11-03 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
KR102295239B1 (en) * 2015-01-08 2021-09-01 삼성전자주식회사 Method of forming the semiconductor device

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030107094A1 (en) * 2001-12-11 2003-06-12 Ji-Young Kim Transistor structures having access gates with narrowed central portions
US20040127050A1 (en) * 2002-12-10 2004-07-01 Samsung Electronics Co., Ltd Method for manufacturing semiconductor device with contact body extended in direction of bit line
US20070241365A1 (en) * 2006-04-12 2007-10-18 Renesas Technology Corp. Semiconductor integrated circuit device
US20090085118A1 (en) * 2007-09-27 2009-04-02 Ji-Ho Hong Semiconductor memory device
US20140252653A1 (en) * 2008-04-25 2014-09-11 Panasonic Corporation Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
US20130021839A1 (en) * 2010-05-21 2013-01-24 Panasonic Corporation Semiconductor memory
US20130113112A1 (en) * 2010-10-26 2013-05-09 Panasonic Corporation Semiconductor device
US20130037888A1 (en) * 2011-08-10 2013-02-14 Samsung Electronics Co., Ltd. Semiconductor device
US20130329487A1 (en) * 2012-06-08 2013-12-12 Renesas Electronics Corporation Semiconductor device
US20140035056A1 (en) * 2012-07-31 2014-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM Cell Connection Structure
US20140241027A1 (en) * 2013-02-25 2014-08-28 United Microelectronics Corp. Static random access memory unit cell structure and static random access memory unit cell layout structure
US20160307882A1 (en) * 2015-04-16 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device layout, semiconductor device, and method of manufacturing memory device
US20170018302A1 (en) * 2015-07-15 2017-01-19 United Microelectronics Corp. Static random access memory unit structure and static random access memory layout structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210167071A1 (en) * 2018-08-29 2021-06-03 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device
US11810860B2 (en) * 2018-08-29 2023-11-07 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device with conductive structure and insulation layer of different width
DE102019124526B4 (en) 2018-10-31 2023-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Design process for a manufacturing process for a semiconductor component

Also Published As

Publication number Publication date
CN115172453A (en) 2022-10-11
US9870996B1 (en) 2018-01-16
CN107706233B (en) 2022-07-12
CN107706233A (en) 2018-02-16

Similar Documents

Publication Publication Date Title
US10971588B2 (en) Semiconductor device including FinFET with self-align contact
US10636790B2 (en) Semiconductor devices and methods for manufacturing the same
US10164034B2 (en) Semiconductor device and a method for fabricating the same
KR102320047B1 (en) Integrated circuit device and method of manufacturing the same
US9691721B2 (en) Jog design in integrated circuits
US10854504B2 (en) Semiconductor structure and manufacturing method thereof
US10861860B2 (en) Method of manufacturing a semiconductor device
US11776857B2 (en) Semiconductor device
US10211212B2 (en) Semiconductor devices
US20150008524A1 (en) Integrated circuit device structure and fabrication method thereof
CN106356299B (en) Semiconductor structure with self-aligned spacer and manufacturing method thereof
US10008409B2 (en) Method for fabricating a semiconductor device
JP2012199381A (en) Semiconductor device and method of manufacturing the same
KR20200000720A (en) Semiconductor device
CN112838070A (en) Interconnect structure, interconnect layout structure and method for fabricating the same
US9870996B1 (en) Semiconductor device and method of fabricating the same
CN111463215B (en) Memory structure and manufacturing method thereof
US7405450B2 (en) Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon
US10134838B2 (en) Semiconductor device
KR20200036980A (en) Semiconductor device and method of fabricating semiconductor device
JP2005175252A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUNG, CHING-WEN;HUANG, CHIH-SEN;REEL/FRAME:039549/0280

Effective date: 20160825

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4