JPH06125007A - Verifying method for layout data of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the amount of layout data which become the design rule checking object of a whole semiconductor device so as to reduce the design rule checking time. CONSTITUTION:A graphic data extracting area A0alpha having a width of a reference design value Pw is set from the outside frame of a functional block A0. Then extracted data are prepared by extracting pattern data, at least part of which are contained in the area A0alpha. Extracted data are also prepared from other functional blocks in the same way. A wiring data extracted area LBalpha having a width of the reference design value Pw is set from the boundary line of a wiring lock LB. Then wiring extracted data are prepared by extracting pattern data, at least part of which are contained in wiring data extracting area LBalpha. Finally, the design rule checking is performed on a whole semiconductor device based on all extracted data and wiring extracted data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device (LSI) layout data verification, and more particularly to design rule checking.

Generally, the design of a small variety of high volume production type LSI is
Mainly manual design by general-purpose interactive design system. This manual design can realize a layout with a high degree of perfection by fully utilizing the degree of freedom in design. On the other hand, it is inevitable that a mistake made by the layout operator, which is peculiar to manual design, is mixed.

In LSI manufacturing, a loss due to a design error becomes large, so it is important to verify the layout result and eliminate errors before the trial manufacture. or,
Even in the case of the automatic layout design, if the layout is not completed, the correction is added as in the manual design, and it is necessary to detect the error.

As one of the verifications of such layout design, there is a geometrical inspection, that is, a design rule check (hereinafter simply referred to as DRC) for detecting a violation of a design standard (design rule) such as a pattern dimension.

[0005]

2. Description of the Related Art Conventionally, layout data in an LSI is generally designed as graphic data having a hierarchical structure. To perform the DRC of the layout data, the graphic data having a hierarchical structure is fully developed on the semiconductor chip to create the actual layout data, and the DRC is performed on all the actual layout data.

However, while the amount of layout data is increasing as the functionality and integration of LSIs increase,
It is hoped that the development period will be shortened. Therefore, it is necessary to shorten the layout data creation period.

In order to shorten the period for creating layout data, various functional blocks that have already undergone each verification including DRC are created in advance in each functional block. Then, there is a method of laying out required function blocks according to the use of the LSI and combining wiring blocks in which wirings connecting terminals between the function blocks are laid out to create layout data of one LSI.

When performing the DRC of the layout data created in this way, a method is adopted in which the DRC is excluded from the DRC targets for the functional blocks that have already undergone each verification including the DRC. That is, the DRC is performed based on the remaining graphic data, excluding the graphic data of the functional blocks that have undergone each verification including the DRC from the actual layout data of the entire chip.

[0009]

However, according to the conventional method of removing lower layer graphic data after completion of each verification including DRC, in the overlapping portion when the lower layer graphic data is arranged, or in the upper layer. There is a possibility that an unverifiable part may occur in the DRC with the connection data.
Therefore, the DRC must be executed for all the actual layout data in which the graphic data and the wiring layout data forming the hierarchical structure are fully developed on the semiconductor chip. Therefore, the DRC requires a lot of time, and the LSI
Cannot shorten the development period.

The present invention has been made in order to solve the above problems, and it is possible to reduce the entire layout data amount subject to the design rule check in the layout data of the semiconductor device, and to reduce the design rule check processing time. The purpose is to be able to shorten.

[0011]

In order to achieve the above object, the present invention performs a design rule check in each functional block for each lower layer graphic data to create lower layer graphic data conforming to the design standard. In addition, a design rule check is performed on the wiring block within the same wiring block to create wiring layout data conforming to the design standard.

A graphic data extraction area having a width of a predetermined design reference value so as to be included in the lower layer graphic data is set from the boundary line for each lower layer graphic data conforming to the design standard. Among the graphic data in the lower layer graphic data, only the graphic data at least a part of which is included in the graphic data extraction area is extracted to create the extracted data.

Further, a wiring data extraction region having a width of a predetermined design reference value is set so as to be included in the wiring block boundary line which conforms to the design standard. Among the wiring layout data in the wiring block, only the graphic data at least a part of which is included in the wiring data extraction area is extracted to create the wiring extraction data.

After that, the design rule of the entire semiconductor device is checked based on the extracted data extracted from each lower hierarchy graphic data and the wiring extracted data extracted from the wiring block.

[0015]

Function: The design rule check of the wiring block is performed in the wiring block, and the design rule check of each lower layer graphic data is performed in the lower layer graphic data. Therefore, the target data of the design rule check in the entire semiconductor device is only the graphic data included in the graphic data extraction area of each lower hierarchy graphic data and the graphic data included in the wiring data extraction area of the wiring block. Therefore, the processing time of the design rule check in the entire semiconductor device is shortened as compared with the case where all the actual layout data for one chip is the target data.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an existing layout diagram designed by an LSI design support device (not shown) such as a CAD device. That is, the semiconductor chip 11 is designed with the respective lower hierarchy graphic data (hereinafter referred to as functional blocks) A0 to X0. DRC is executed in each of the functional blocks A0 to X0, and the functional blocks A0 to X0 conform to the design standard. The DRC includes, for example, the size of each pattern data, the interval between each pattern data, and the like. And
The layout data of this embodiment is created using the existing layout data shown in FIG.

FIG. 1 is a flow chart showing the layout data creating process of this embodiment. In the hierarchical graphic data file 1, for example, data of a large number of functional blocks A0 to X0 extracted from the layout data of the existing semiconductor device shown in FIG. 2 is registered. Further, in the hierarchical graphic data file 1, data of functional blocks AA and BB extracted from layout data of another existing semiconductor device is registered.

In the extraction process 2, the hierarchical graphic data file 1
From the data of each functional block, the boundary line of the functional block, that is, the outer frame is extracted. In the extraction process 2, the layout information of the input / output terminals is extracted from the data of each functional block. Outer frame of each functional block extracted in the extraction process 2,
The terminal arrangement information is registered in the extracted data file 3.

In the net data file 4, the number of input / output terminals of each functional block extracted based on the logical information of the layout data to be created, the destination of signals, and the connection information data are registered.

Extracted data file 3 for floor plan 5
The minimum chip size required for creating the layout data is determined based on the data of 1) and the data of the net data file 4. That is, the size of each functional block in the created layout data and the wiring block for laying out the wirings connecting between the functional blocks are estimated.

At this time, if there is a functional block to be newly created (not registered in the hierarchical graphic data file 1), the shape of the new functional block and the external input / output terminal are determined in the floor plan 5.

For example, as shown in FIG. 4, the layout data of the semiconductor chip 12 to be created now is the functional block A.
0, AA, AA1, AA2, AA3, E0-M0, O0
˜T0 and V0 to X0.
Of these, the functional blocks A0, AA, E0-M0, O0
-T0 and V0-X0 are the hierarchical figure data file 1
It is assumed that the function block is registered in. It is assumed that the functional blocks AA1, AA2, AA3 are newly created functional blocks.

New functional blocks AA1, AA2, AA3
The arrangement position and the input / output terminal position of (1) are determined based on the terminal positions of the existing functional blocks A0, AA, E0-M0, O0-T0 and V0-X0, and the connection information with each functional block. New function blocks AA1, AA2, AA3
Is calculated from the type and number of elements used in the functional block, and the wiring density (the ratio of the wiring area in the functional block).

The wiring order at this time is determined in the order of connection between existing function blocks, connection between existing function blocks and new function blocks, and connection between new function blocks. Therefore, for example, the wiring in the layout data shown in FIG.
1, k1, s1, v1 to x1 are connected to each other. next,
The terminals a5, i1, l1, m1, p1 to r1 are connected to each other. Finally, the terminals a4 and a6 are connected to each other.

Then, a wiring block LB is created as shown in FIG. 4 based on the above wiring order, the outline frame and terminal position information of the existing functional block, and the size and terminal position information of the new functional block. can do. In addition,
The layout of each new functional block AA1, AA2, AA3 can be performed by a plurality of workers in parallel. Further, the wiring layout work of the wiring block LB can be performed by another worker in parallel with the layout work of the new functional block.

The function block data file 6 has existing function blocks A0, AA, E0 to M used for layout data created from the hierarchical figure data file 1.
The layout data of 0, O0 to T0 and V0 to X0 are registered. In the functional block data file 7, the new functional blocks AA1 and AA created in the floor plan 5 are created.
2, the layout data of AA3 is registered. Then, DR for each new functional block AA1, AA2, AA3
Execute C. The layout data of the wiring block LB created in the floor plan 5 is registered in the wiring block data file 8, and the wiring block LB is set to D
Execute RC. Therefore, each existing function block A0,
AA, E0-M0, O0-T0 and V0-X0, the new functional blocks AA1, AA2, AA3 and the wiring block LB are each adapted to the design standard.

In the next DRC processing 9, the DRC of the entire chip is
Perform processing. At this time, the function block data file 6,
7, a graphic data extraction area having a width of a predetermined design reference value is set inward from the boundary line (outer frame) of the actual layout data of each functional block to the inside of the functional block.
Next, of the pattern data in the functional block, only the pattern data at least a part of which is included in the graphic data extraction area is extracted to create the extracted data.
Note that being included in the graphic data extraction area means being in contact with, included in, or straddling the graphic data extraction area.

For example, as shown in FIG. 5, in the existing functional block A0, the design reference value Pw is calculated from the outline frame indicated by the solid line.
The graphic data extraction area A0α (hatched portion) having the width of is set. At least a part of the pattern data in the functional block A0 is the graphic data extraction area A0.
Extracted data is created by extracting only the pattern data included in α. Other functional blocks AA and E shown in FIG.
The graphic data extraction areas are similarly set for 0 to M0, O0 to T0 and V0 to X0, and for each new functional block AA1, AA2, AA3. Then, only the pattern data at least a part of which is included in each figure data extraction region is extracted as extraction data.

Further, in the DRC processing 9, a wiring data extraction area having a width of a predetermined design reference value is set inward of the wiring block from the boundary line of the actual layout data of the wiring block of the wiring block data file 8. Next, among the pattern data in the wiring block, only the pattern data at least a part of which is included in the wiring data extraction area is extracted to create the wiring extraction data. Note that being included in the wiring data extraction area means being in contact with, included in, or straddling the wiring data extraction area.

For example, as shown in FIG. 5, in the wiring block LB, a wiring data extraction area LBα (hatched portion) having a width of the design reference value Pw from the solid line boundary is set. Then, among the pattern data in the wiring block LB, only the pattern data at least a part of which is included in the wiring data extraction region LBα is extracted to create the wiring extraction data.

The functional block data file 6,
The design rule check of the entire semiconductor chip 12 is performed based on the extracted data extracted from each of the functional blocks 7 and the wiring extracted data extracted from the wiring blocks. If there is no design standard violation in this DRC processing 9, the data of the functional block data files 6 and 7 and the data of the wiring block data file 8 are registered in the layout data file 10 as actual layout data.

As described above, in this embodiment, the layout data amount for performing the DRC of the entire semiconductor chip can be reduced to only the extracted data and the wiring extracted data extracted from each functional block. Therefore, the DRC processing time can be shortened, and the LSI development period can be shortened.

Further, in this embodiment, when the layout data of the semiconductor chip is created, the wiring block is created based on the wiring order of the existing or new functional block to be laid out and the size and terminal position information of each functional block. ing. Therefore, it is possible to reduce the time required for the entire wiring of the semiconductor chip and to realize a layout with extremely high wiring efficiency.

[0034]

As described in detail above, according to the present invention,
It is possible to reduce the total amount of layout data subject to the design rule check, and it is possible to shorten the processing time of the design rule check, which is an excellent effect.

[Brief description of drawings]

FIG. 1 is a flowchart showing a layout data creation process of an embodiment.

FIG. 2 is an existing layout diagram in one embodiment.

FIG. 3 is a diagram showing a configuration of a functional block extraction data file.

FIG. 4 is a layout diagram newly created in one embodiment.

FIG. 5 is a diagram showing a data extraction area in a functional block and a wiring block.

[Explanation of symbols]

1 Hierarchical figure data file 3 Extracted data file 4 Net data file 6, 7 Functional block data file 8 Wiring block data file 10 Layout data file 12 Semiconductor chip A0-X0, AA, AA1, AA2, AA3 Functional block A0α Graphic data extraction area LB Wiring block LBα Wiring data extraction area Pw Design reference value

Claims (1)

[Claims] 1. When performing a design rule check of layout data of a semiconductor device designed by a wiring block in which wirings for connecting the graphic data having a hierarchical structure and each lower hierarchical graphic data are laid out, A design rule check is performed in the lower layer graphic data to create lower layer graphic data that conforms to the design standard, and a wiring rule data that conforms to the design standard is checked in the same wiring block for the wiring block. Create and set a graphic data extraction area having a predetermined design standard value width so as to be included in the lower layer graphic data from the boundary line for each lower layer graphic data conforming to the design standard. At least the figure data in the lower hierarchy figure data Part extracts only the graphic data included in the graphic data extraction area to create the extracted data, and the design standard value that is determined in advance so that it is included in the same block from the boundary line of the wiring block that conforms to the design standard. Of the wiring layout data in the same wiring block, and at least a part of the graphic data whose wiring data extraction area is included in the wiring layout data extraction area is created to create the wiring extraction data. A layout data verification method for a semiconductor device, wherein a design rule check of the entire semiconductor device is performed based on the extracted data extracted from the lower hierarchical figure data and the wiring extracted data extracted from the wiring block.