JP2010097972A - Layouting device of semiconductor integrated circuit and layouting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layouting method of a semiconductor integrated circuit for uniformizing metal density with no requirement for layout correction, and for arranging dummy metal with no requirement for layout correction. <P>SOLUTION: The layouting method of a semiconductor integrated circuit includes: a step of arranging a dummy pattern 1 in a first region with a predetermined dimension X×X and interval 2X to provide a predetermined metal density at the time of floor planning; a step of arranging a logical circuit cell in the first region so as to meet a timing constraint by analyzing timing, for wiring; and a step of verifying whether a layout pattern generated by arranging the logical circuit cell for wiring meets a specification. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to DFM (Design For Manufacturing) of a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit layout apparatus and layout method for fill metal.

  In recent years, with the miniaturization of semiconductor integrated circuits, multilayer wiring has been progressing. In order to realize multilayer wiring, it is essential to flatten the wiring layer. In order to realize planarization, CMP (Chemical Mechanical Planarization) processing is performed. In the CMP process, in order to ensure flatness, it is necessary to set the wiring metal density ratio (hereinafter referred to as “metal density”) to a predetermined design reference value or more. When the metal density is less than the design standard value, there are problems that the thickness of the metal wiring is reduced and the metal wiring is disconnected. For this reason, a process of inserting a fill metal into a region with little metal wiring to make the metal density uniform is performed.

  For example, Japanese Patent Laid-Open No. 2001-274255 discloses an automatic placement and routing method for semiconductor integrated circuits. FIG. 1 is a flowchart showing an automatic placement and routing method disclosed in Japanese Patent Laid-Open No. 2001-274255. FIG. 2 is a plan view showing a layout pattern of a dummy pattern for CMP in Japanese Patent Laid-Open No. 2001-274255. This layout pattern includes a dummy pattern 102 that is the same as the above-described fill metal, a fixed potential wiring 103 or a fixed potential node 103 that is a node, a dummy wiring 101 that connects the dummy patterns 102 to each other and connects them to the fixed potential node 103, Wiring 104 is provided. The dummy wiring 101, the dummy pattern 102, and the actual wiring 104 are formed of a metal wiring such as aluminum through a manufacturing process.

  As shown in the flowchart of FIG. 1, first, each block is arranged in the arrangement step (ST1). At the same time, a dummy pattern 102 as shown in FIG. 2 is generated and placed at an appropriate position. Each block to be arranged here is a functional block or a block (logical functional unit) using a logic cell such as a NAND gate or a NOR gate, a flip-flop, other transistors, resistors, and a basic cell formed by combining these. The wiring pattern is designed in advance and prepared as a library. Next, in the schematic wiring step (ST2), the wiring area is divided into rectangular areas (channels) that do not overlap each other, and it is determined which channel the wiring path of each net passes through. In the detailed wiring step (ST3), a detailed wiring path in the channel is determined for each channel. Then, a dummy wiring 101 is generated as a wiring pattern and connected to a fixed potential node 103 such as a power supply or a ground. In the detailed wiring step (ST3), the wiring occupancy (density) is calculated for each wiring region where the circuit block is not arranged after the normal detailed wiring. Then, for a wiring region whose occupancy ratio is less than the value required by the CMP method, a dummy wiring 101 is generated toward a free region of the wiring, and this is connected to a fixed potential node.

  As a related technique, Japanese Unexamined Patent Application Publication No. 2007-128512 (corresponding US application No. 11/265641) discloses a method, a system, and a program for improving the manufacturing compatibility of a semiconductor device. This patent document discloses a method of performing verification by arranging logic cells so as to satisfy timing constraints.

JP 2001-274255 A JP 2007-128512 A

  In the automatic placement and routing method disclosed in Japanese Patent Laid-Open No. 2001-274255, the metal density (occupancy) is calculated after normal detailed wiring. Then, a dummy pattern is added to the wiring area in which the calculated metal density does not satisfy the metal density required by CMP. In this case, when a dummy pattern is added, a coupling capacitance is generated between the actual wiring and the added dummy pattern. Then, the timing of each signal changes due to the newly generated coupling capacitance. As a result, timing violation occurs due to the addition of a dummy pattern at a place where timing is satisfied during placement and wiring. At a place where such timing violation occurred, an iteration occurred in which layout correction was made after returning to the previous process such as buffer insertion or wiring correction. A technique for making the metal density uniform without requiring layout correction is desired. A technique for arranging fill metal (dummy metal) without requiring layout correction is required.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the best mode for carrying out the invention. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of the claims and the best mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

  According to the semiconductor integrated circuit layout method of the present invention and the program for causing a computer to execute the dummy pattern (1) with predetermined dimensions (X × X) and intervals (2X) so as to have a predetermined metal density during floorplanning. Generated by placing in the first area, placing logic circuit cells and wiring to satisfy timing constraints while performing timing analysis in the first area, and placing logic circuit cells and wiring Verifying whether the layout pattern satisfies the standard.

  In the present invention, the dummy metal (1) is arranged so as to satisfy a predetermined metal density at the time of the floor plan, and the arrangement / wiring is performed so as to satisfy the timing constraint while performing the timing analysis. That is, at the time of arrangement / wiring, the arrangement / wiring can be performed by incorporating the coupling capacitance between the dummy pattern and the wiring already arranged. As a result, timing violation does not occur after placement / wiring, so that it does not occur at the location where timing violation has occurred to perform layout correction that returns to the previous process such as buffer insertion or wiring correction.

  The semiconductor integrated circuit layout device of the present invention includes a floor plan section (21, 22), a placement / wiring section (24), and a verify section (25). The floor plan sections (21, 22) arrange dummy patterns in the first region with predetermined dimensions (X × X) and intervals (2X) so that a predetermined metal density is obtained during floor planning. The placement / wiring unit (24) arranges the logic circuit cells in the first region so as to satisfy the timing constraint while performing timing analysis, and performs wiring. The verify unit (25) verifies whether the layout pattern generated by arranging and wiring the logic circuit cells satisfies the standard.

  In the present invention, since the layout device functions like the above layout method, the same effect as the above layout method can be obtained.

  According to the present invention, it is possible to make the metal density uniform without requiring layout correction. Dummy metal can be placed without the need for layout modification.

  A semiconductor integrated circuit layout apparatus and layout method according to embodiments of the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
A semiconductor integrated circuit layout apparatus and layout method according to a first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a block diagram showing the configuration of the layout device of the semiconductor integrated circuit according to the first embodiment of the present invention. The layout device (system) includes a computer device 10 and a server 11 that are connected via a network 13 so as to be capable of bidirectional communication.

  The server 11 is an information processing apparatus that holds the storage medium 12 and is exemplified by a workstation. The recording medium 12 is a storage device that stores an execution program for the layout method and is exemplified by an HDD (Hard Disk Drive). The computer apparatus 10 is an information processing apparatus exemplified by an engineering workstation. The server 11 is connected to the computer apparatus 10 via a network 13 exemplified by the Internet. The computer device 10 downloads the program stored in the recording medium 12 of the server 11 via the network 13 and stores it in its own local HDD or memory. Then, the computer device 10 executes the downloaded program. The computer device 10 may include the storage medium 12. That is, the layout device may be a single information processing device.

  FIG. 4 is a block diagram showing the configuration of the storage medium 12 of the layout apparatus. The storage medium 12 stores a design program 15 for executing the layout method and a database 16 including data used for executing the design program 15. The database 16 includes a library 31, a circuit information file 32, and a design rule file 33.

  The library 31 stores data related to functional blocks or blocks (logical functional units). This is a logic circuit cell / block composed of logic gates such as NAND gates and NOR gates, flip-flops, other transistors, resistors, and basic cells combining these, and the wiring pattern is designed in advance. The circuit information file 32 stores logic circuit information obtained by logic design, such as logic connection data indicating connection relationships between blocks, positions, and terminals constituting the LSI to be designed. The design rule file 33 is a semiconductor process design standard, for example, metal density required in the manufacture of a semiconductor process, fill metal arrangement interval, fill metal dimension, wiring interval of each wiring layer (interval of wiring grid), Stores design rules related to semiconductor design and processes such as wiring width and minimum wiring spacing.

  The design program 15 includes a floor plan A section 21, a floor plan B section 22, a power supply wiring section 23, an arrangement / wiring section 24, a verify section 25, and a GDS creation section 26. The floor plan A section 21 places fill metal on the chip (floor plan 1 processing). The floor plan B unit 22 arranges a macro or the like on the chip (floor plan 2 process). The power supply wiring unit 23 arranges power supply wiring on the chip (power supply wiring processing). The arrangement / wiring unit 24 arranges logic circuit cells / blocks, performs wiring in each layer (placement / wiring processing), and generates a layout pattern. The verify unit 25 verifies whether the layout pattern satisfies a predetermined standard (layout verification process). The GDS creation unit 26 converts the layout pattern and generates a mask pattern in a predetermined data format.

  Next, the operation (layout method) of the semiconductor integrated circuit layout device according to the first embodiment of the present invention will be described. FIG. 5 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the first embodiment of the present invention.

  First, in step S1, the floor plan A unit 21 executes the processing of the floor plan 1. That is, the floor plan A unit 21 arranges peripheral blocks such as an IO buffer in the peripheral area 4 (described later) provided in the peripheral part of the chip based on the data of the library 31, the circuit information file 32, and the design rule file 33. . Further, the floor plan A unit 21 specifies an area excluding the peripheral area 4 from the entire chip based on the data in the circuit information file 32 (an internal area surrounded by the peripheral area 4), and the data in the design rule file 33 Based on the above, fill metal 1 (described later) is arranged. At that time, the fill metal 1 is arranged at an intersection of virtual wiring grids 2 (described later) having a lattice interval defined by the semiconductor process design standard.

  Regarding the arrangement of the fill metal 1, it is preferable to arrange the fill metal 1 so as to satisfy at least 20% or more, which is a metal density required in the manufacture of a semiconductor process. When the macro, actual wiring, and logic circuit cells are arranged and wired in the subsequent processes, the metal density is higher than that of the fill metal 1, so that the metal density of 20% or more can be surely satisfied.

Here, FIG. 6 is a conceptual diagram showing a method for arranging fill metal and actual wiring. As shown in FIG. 6, in the region where the fill metal 1 (dummy pattern), the actual wiring 3 (described later), and the like are arranged, 2X that is twice the value X that is uniquely determined by the semiconductor process design criteria. Wiring grids 2 are provided vertically and horizontally at intervals of. The pattern of the fill metal 1 has a square shape with the value X as one side. The wiring width of the actual wiring 3 is X. Fill metal 1 and actual wiring 3 are arranged on wiring grid 2. In particular, the fill metal 1 is disposed at an intersection (hereinafter also referred to as “lattice point”) of the wiring grid 2. In this way, one side of a square X, in relation to the adjacent square, square X ² is to be provided on the region of 4X ^2. Therefore, a metal density of 25% (= X ² / 4X ² × 100) is obtained. Further, the wiring attribute of the fill metal 1 can be identified by giving a different name to distinguish it from the actual wiring 3. However, in the present invention, one side of the pattern of the fill metal 1 is not limited to the value X as long as the metal density of 20% or more is satisfied.

FIG. 7 is a plan view showing an example of the layout pattern after the floor plan (S1). The area excluding the peripheral area 4 from the entire chip area (area in which the fill metal 1 and the actual wiring 3 are arranged) is 18X horizontal 14X vertical. However, the description of the virtual wiring grid 2 described in FIG. 6 is omitted. In this region, a fill metal 1 having a size of X × X (a square of one side X) is arranged at a lattice point of the wiring grid 2. In this example, 80 fill metals 1 are arranged at 80 (inside: 48 + 4 sides: 28 + 4 corners: 4) lattice points including each side and each corner. In this case, it is ^{(48 × X 2 + 28 ×} (X 2/2) + 4 × (X 2/4)) / 252X 2 × 100 = 25%. In this way, fill metal 1 is added after placement and wiring by achieving the metal density (25%) required for semiconductor process manufacturing at the stage of the floor plan (S1) before placement and wiring (S4) There is no need to do. Therefore, the placement / wiring incorporating the coupling capacitance of the fill metal 1 and the actual wiring 3 can be performed from the first time, and the timing violation after the placement / wiring does not occur.

  Next, in step S2, the floor plan B unit 22 executes the processing of the floor plan 2. That is, the floor plan B unit 22 creates a macro 5 (an internal region surrounded by the peripheral region 4) in the region excluding the peripheral region 4 from the entire chip based on the library 31, the circuit information file 32, and the design rule file 33. (To be described later). Specifically, the macro 5 created in units of functional blocks is arranged at a desired position in the area excluding the peripheral area 4 from the entire chip. However, since the fill metal 1 is arranged on the lattice points of the wiring grid 2 in the inner region surrounded by the peripheral region 4, the macro 5 overlaps the fill metal 1 without considering the fill metal 1. Are arranged as follows.

  FIG. 8 is a plan view showing an example of the layout pattern after the floor plan (S2). Following the state of FIG. 7, two macros 5 having a size of 5X × 5X are arranged in the area excluding the peripheral area 4 from the entire chip area so as to overlap the area where the fill metal 1 is arranged. Yes. As shown in this figure, the fill metal 1 is buried in the macro 5 at the place where the macro 5 is arranged. In the case of this figure, the metal density is not reduced by insertion of the macro 5, so that a metal density of 20% or more is achieved.

  Subsequently, in step S3, the power supply wiring unit 23 performs power supply wiring processing on the entire chip. That is, the power supply wiring unit 23 arranges power supply wiring on the chip based on the library 31, the circuit information file 32, and the design rule file 33. As the power supply wiring method, a conventional method can be basically used. Illustration of the power supply wiring is omitted.

  Next, in step S4, the placement / wiring unit 24 places logic circuit cells and the like, and executes placement / wiring for wiring in each layer. That is, the placement / wiring unit 24 is based on the library 31, the circuit information file 32, and the design rule file 33, in which the fill metal 1 is placed on the grid points of the wiring grid 2 in step S 1 (surrounded by the peripheral region 4. In the internal area, logic circuit cells are arranged so as to satisfy timing constraints while performing timing analysis, and wiring of each layer is performed. The wiring of each layer is performed based on the net information of the logic circuit information. The actual wiring 3 is arranged on the wiring grid 2 as described above. A layout pattern is generated by this placement / wiring process.

  However, since the fill metal 1 is arranged on the lattice points of the wiring grid 2 in the inner region surrounded by the peripheral region 4, the logic circuit cell and the actual wiring are arranged so as to overlap the fill metal 1. At this time, the timing analysis and the timing constraint are analyzed and arranged with respect to the overlapping portion while giving priority to the presence of the logic circuit cell and the actual wiring instead of the fill metal 1.

FIG. 9 is a plan view showing an example of the layout pattern after the placement / wiring (S4). As shown in this figure, the fill metal 1 is buried in the actual wiring 3 where the actual wiring 3 passes on the wiring grid 2. On the other hand, the place where the actual wiring 3 does not pass on the wiring grid 2 remains as the fill metal 1 as it is. In this arrangement / wiring process, wiring is performed while performing timing analysis in consideration of the coupling capacitance between the fill metal 1 and the actual wiring 3. Therefore, the placement / wiring is completed in a state where the timing constraint is satisfied.
In this figure, for the sake of easy understanding, the region where the macro 5 is arranged as shown in FIG. 8 is not shown. Alternatively, it can be seen that an example in which the macro 5 is not arranged in the illustrated region is shown.

Subsequently, in step S5, the verify unit 25 verifies whether the layout pattern satisfies the standard defined by the process.
That is, the verify unit 25 performs a layout check (for example, LVS, DRC) on the presence or absence of a metal wiring short-circuit with respect to the layout pattern based on the design rule file 33. Since the wiring attribute of fill metal 1 can be identified with a different name to distinguish it from actual wiring 3, an option is added to check that the overlap between fill metal 1 and actual wiring 3 is not treated as a short circuit. Do. This verification includes checking whether or not the metal density satisfies at least 25%, which is a metal density required for manufacturing a semiconductor process.

  Next, in step S6, a GDS2 format (Graphic Data System 2: a binary data format that is a global standard for describing mask patterns) is created. In other words, the GDS creation unit 26 converts the verified layout data into the GDS2 format.

A layout pattern is designed as described above.
Here, as shown in FIG. 6, the pattern of the fill metal 1 is a square shape having a value X uniquely determined by the semiconductor process design standard as one side, the interval of the wiring grid 2 is 2X, and the actual wiring 3 The wiring width is X. Accordingly, since the fill metal of ^{X 2} is provided in the region of 4X ^2, metal density ^{25% (= X 2 / 4X} 2 × 100) is obtained by simply fill metal. However, it is assumed that the value of X can be slightly increased or decreased as long as it satisfies the design criteria.

FIG. 10 is a plan view showing an example of a layout pattern in which fill metal is arranged. Here, a case where a square fill metal 1 having a side X is arranged at a lattice point of the wiring grid 2 in a square region having a side of 12X will be described as an example. The number of patterns of the fill metal 1 in a square region having a side of 12X is as follows. In a square region (area is 144X ² ) with a side of 12X, first, a total of 25 patterns of square fill metal 1 (area is X ² ) with a side X are arranged at the center. In addition, a total of 20 patterns of square fill metal 1 with one side X are arranged on the four sides of the square region. At this time, half of the fill metal 1 protrudes from the square area. Therefore, the area for one piece of the fill metal 1 is X ^2/2 in the square region. Further, a total of four patterns of square fill metal 1 with one side X are arranged at the four corners of the square region. At this time, 3/4 of the fill metal 1 protrudes from the square area. Therefore, the area for one piece of the fill metal 1 is X ^2/4 in square region. From the above, the total number of patterns of fill metal 1, 25 + 20 or + 4 pieces = 49 and becomes, the total area of the fill metal ^{1, 25 × X 2 + 20 ×} (X 2/2) + 4 × (X 2 / 4) = 36 × ² . Therefore, when calculating the occupancy rate of fill metal ^1, a ^{36X 2 / 144X 2 × 100 =} 25%. That is, “20% or more” is satisfied.

In the above layout method of a semiconductor integrated circuit of the present invention as described, when the arrangement step of fill metal 1 (step S1), the results in the square X ² is provided in the area of 4X ^2. Therefore, at least 25% (X ² / 4X ² ), which is a metal density required for manufacturing a semiconductor process, by placing the fill metal 1 at the lattice points of the wiring grid 2 before the placement / wiring (step S4). ) Satisfy the above. As a result, when the macro 5, actual wiring 3, and logic circuit cells are arranged and wired in the subsequent processes, the metal density is higher than that of the fill metal 1, so that the metal density of 20% or more is surely satisfied. Can do.

  In addition, it is not necessary to newly add the fill metal 1 after the placement / wiring process (step S4). Therefore, in the placement / wiring process, placement / wiring incorporating the coupling capacitance between the fill metal 1 and the actual wiring 3 can be performed from the first time. Thereby, timing violation after the placement / wiring process does not occur. As a result, it is possible to obtain an effect that no iterations such as buffer insertion, wiring correction, and the like that perform layout correction that returns to the previous process occur.

(Second Embodiment)
A layout apparatus and layout method for a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a block diagram showing a configuration of a layout device of a semiconductor integrated circuit according to the second embodiment of the present invention. The layout device (system) includes a computer device 10 and a server 11 that are connected via a network 13 so as to be capable of bidirectional communication. Since this configuration is the same as that of the first embodiment, the description thereof is omitted.

  FIG. 4 is a block diagram showing the configuration of the storage medium 12 of the layout apparatus. The storage medium 12 stores a design program 15 for executing the layout method and a database 16 including data used for executing the design program 15. In the present embodiment, in the configuration shown in FIG. 4, the functions of the floor plan A section 21, the floor plan B section 22 and the placement / wiring section 24 of the design program 15 are different from those in the first embodiment. That is, the floor plan A unit 21 executes the process of the floor plan 1 without performing the process of setting the wiring attribute of the fill metal 1 to a name different from that of the actual wiring 3 as the process of the floor plan 3 (S11). The floor plan B unit 22 executes a process (S7) of deleting the fill metal overlapping the macro in addition to the process of the floor plan 2 (S2). In addition to the placement / wiring process (S4), the placement / wiring unit 24 executes a process (S8) for deleting the fill metal overlapping the wiring.

  Next, the operation (layout method) of the layout device of the semiconductor integrated circuit according to the second embodiment of the present invention will be described. FIG. 11 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the second embodiment of the present invention.

  In the operation of the layout apparatus of the present semiconductor integrated circuit, the processing of the floor plan 1 (step S1) is changed from the processing of the floor plan 3 (step S11) as compared with the flowchart of FIG. 5 showing the operation in the first embodiment. In addition, a process (step S7) for removing the fill metal that overlaps the macro is added between the process of the floor plan 2 (step S2) and the process of the power supply wiring (step S3), and the arrangement / wiring process (step S4). ) And the verification process (step S5), a process (step S8) for deleting the fill metal overlapping the wiring is added. Other steps (processing) are the same as those in the first embodiment.

In step S <b> 11, the floor plan A unit 21 executes the processing of the floor plan 3.
The processing of the floor plan 3 (step S11) is different from the processing of the floor plan 1 (step S1) in that the processing for setting the wiring attribute of the fill metal 1 to a name different from that of the actual wiring 3 is unnecessary. . Others are the same as the processing of the floor plan 1 (step S1).

  In step S7, the floor plan B unit 22 executes a process of deleting the fill metal 1 that overlaps the arranged macro 5 with respect to the layout data after step S2. The overlapping portion is determined, for example, by comparing the coordinates of the macro 5 and the coordinates of the fill metal 1. Furthermore, in step S8, the placement / wiring unit 24 executes a process of deleting the fill metal 1 overlapping the placed actual wiring 3 after step S4. The overlapping portion is determined by comparing the coordinates of the actual wiring 3 and the coordinates of the fill metal 1, for example.

  FIG. 12 is a plan view showing an example of the layout pattern after the process (S8) of deleting the fill metal overlapping the wiring. As shown in the figure, the floor plan B section 22 deletes the fill metal 1 where the macro 5 and the fill metal 1 are arranged to overlap (S7). As a result, there is no fill metal 1 in the macro 5. In addition, the placement / wiring unit 24 deletes the fill metal 1 where the actual wiring 3 and the fill metal 1 overlap each other (S8). As a result, the fill metal 1 does not exist in the actual wiring 3.

  In the present embodiment, the fill metal 1 is deleted as much as the actual wiring 3 and the macro 5 and the fill metal 1 are arranged overlapping each other. Therefore, the data amount of the reduced fill metal is reduced, and the data processing time in verification (Verify: S5) can be shortened.

(Third embodiment)
A semiconductor integrated circuit layout apparatus and layout method according to a third embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a block diagram showing a configuration of a layout device of a semiconductor integrated circuit according to the third embodiment of the present invention. The layout device (system) includes a computer device 10 and a server 11 that are connected via a network 13 so as to be capable of bidirectional communication. Since this configuration is the same as that of the first embodiment, the description thereof is omitted.

  FIG. 4 is a block diagram showing the configuration of the storage medium 12 of the layout apparatus. The storage medium 12 stores a design program 15 for executing the layout method and a database 16 including data used for executing the design program 15. In the present embodiment, in the configuration shown in FIG. 4, the functions of the floor plan A section 21 and the floor plan B section 22 of the design program 15 are different from those in the second embodiment. That is, the floor plan A unit 21 arranges the peripheral blocks in the peripheral area 4 and the macro 5 in the area excluding the peripheral area 4 as processing of the floor plan 4. The floor plan B portion 22 is an area excluding the peripheral area 4, and the fill metal 1 is arranged on the entire area where the macro 5 is not arranged.

  Next, the operation (layout method) of the semiconductor integrated circuit layout device according to the third embodiment of the present invention will be described. FIG. 13 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the third embodiment of the present invention.

  In the operation of the layout apparatus of the present semiconductor integrated circuit, the processing of the floor plan 3 (step S11) and the processing of the floor plan 2 (step S2) are compared with the flowchart of FIG. 11 showing the operation in the second embodiment. Also, the process of deleting the fill metal that overlaps the macro (step S7) is replaced with the process of the floor plan 4 (step S9) and the process of placing the fill metal in the area where the macro is not arranged (step S10). Other steps (processes) are the same as those in the second embodiment.

  In step S9, the floor plan A unit 21 arranges peripheral blocks such as an IO buffer in the peripheral area 4 provided in the peripheral part of the chip based on the data of the library 31, the circuit information file 32, and the design rule file 33. . Subsequently, the floor plan A unit 21 arranges the macro 5 in an area excluding the peripheral area 4 from the entire chip based on the library 31, the circuit information file 32, and the design rule file 33.

  Further, in step S10, the floor plan B section 22 is an area in which the peripheral area 4 is excluded from the entire chip (an internal area surrounded by the peripheral area 4), and the wiring grid on the entire area where the macro 5 is not disposed. Fill metal 1 is arranged at two grid points.

  In the present embodiment, the fill metal 1 is deleted as much as the macro 5 and the fill metal 1 are arranged overlapping each other. Therefore, since the data amount of the reduced fill metal 1 is reduced, it is possible to shorten the data processing time in the process (S11) of arranging the fill metal 1.

(Fourth embodiment)
A semiconductor integrated circuit layout apparatus and layout method according to a fourth embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a block diagram showing a configuration of a layout device of a semiconductor integrated circuit according to the fourth embodiment of the present invention. The layout device (system) includes a computer device 10 and a server 11 that are connected via a network 13 so as to be capable of bidirectional communication. Since this configuration is the same as that of the first embodiment, the description thereof is omitted.

  FIG. 4 is a block diagram showing the configuration of the storage medium 12 of the layout apparatus. The storage medium 12 stores a design program 15 for executing the layout method and a database 16 including data used for executing the design program 15. In the present embodiment, in the configuration shown in FIG. 4, the function of the placement / wiring unit 24 of the design program 15 is different from that in the first embodiment. That is, the placement / wiring unit 24 inspects the density of the actual wiring 3 in addition to the function of the placement / wiring unit 24 of the first embodiment, and the fill metal 1 is applied to a portion where the density of the actual wiring 3 is low. Molded into a large solid fill metal.

  Next, the operation (layout method) of the layout device of the semiconductor integrated circuit according to the fourth embodiment of the present invention will be described. FIG. 14 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the fourth embodiment of the present invention.

In the operation of the layout apparatus of the present semiconductor integrated circuit, compared with the flowchart of FIG. 5 showing the operation in the first embodiment, between the placement / wiring process (step S4) and the verification process (step S5). The process of determining whether or not there is a region where the wiring interval is _{equal to} or greater than Y _Grid (step S12), the process of extracting the region of fill metal 1 that is more than X _Grid away from each wiring (step S13), and the extracted region A process (step S14) for forming the fill metal 1 into a solid shape (a state where the fill metal 1 spreads over the entire surface without any gap) is added. Other steps (processing) are the same as those in the first embodiment.

In step S12, after the placement / wiring process (S4), the placement / wiring unit 24 determines whether or not there is a region where the wiring interval between the actual wirings 3 is equal to or greater than the distance Y _Grid . When there is no such area (step S12: NO), in step S5, the verify unit 25 executes a verification process. If there is such a region (step S12: YES), in step S13, the placement / wiring unit 24 determines the distance from the wiring used for the determination with respect to the region where the wiring interval between the actual wirings 3 is equal to or greater than Y _Grid. An area of the fill metal 1 that is more than X _Grid is extracted. In step S14, the placement / wiring unit 24 shapes the fill metal 1 in the extracted region into a solid shape. In the solid molding, a plurality of fill metals 1 are integrated so as to spread over one surface without a gap. However, the used X _Grid uses the number of grids of the fill metal 1 that is not subject to coupling capacity extraction when extracting the coupling capacity in the placement / wiring process (step S4). Also, the value of Y _Grid is 2 × X _Grid or more. Thereafter, in step S5, the verify unit 25 executes a verification process. At this time, since X _Grid is set to a distance (interval) that is not a coupling capacity extraction target at the time of coupling capacity extraction, the solid fill metal 6 does not affect the coupling capacity. Other steps (processing) are the same as those in the first embodiment.

15 and 16 are plan views showing examples of layout patterns after placement and wiring (S4) and after the fill metal 1 is formed into a solid shape (S14), respectively. In both figures, Y _Grid = 7 lattice, distance X _Grid = 3 lattice, and Y _Grid > 2 × X _Grid is satisfied.

First, in FIG. 15, a region 8 in which the wiring interval between the actual wirings 3 is equal to or greater than the distance Y _Grid = 7 lattices is extracted (step S12: YES). Next, the region 9 of the fill metal 1 that is separated from the wiring used for the determination by a distance X _Grid = 3 grids or more is extracted (step S13). Subsequently, in FIG. 16, the fill metal 1 in the extracted region 9 is filled with the solid fill metal 6 (step S14).

  In the present embodiment, the individual fill metal 1 is made solid. Therefore, the metal density of the wiring metal can be improved accordingly. Further, at the time of creating the GDS2 format (step S6), it is possible to reduce the amount of data converted from the verified layout data to the binary data format for describing the mask pattern.

  As a first effect of the present invention, it is not necessary to add fill metal after placement and wiring. For this reason, by performing placement / wiring that incorporates coupling capacitance between fill metal and actual wiring, timing violation after placement / wiring does not occur, so it is possible to prevent the occurrence of iteration of layout correction. . As a second effect of the present invention, at least 25% or more can be satisfied as a metal density required in manufacturing a semiconductor process. As a third effect of the present invention, the amount of fill metal data is reduced by the amount of actual wiring and the overlap of macro and fill metal, and the verify data processing time can be shortened. As a fourth effect of the present invention, the amount of fill metal to be arranged is reduced by the macro occupied area as compared with the case where fill metal is arranged over the entire chip, and the fill metal arrangement data processing time can be shortened. As a fifth effect of the present invention, the metal density of the wiring metal can be improved by the amount of solid fill metal. As a sixth effect of the present invention, it is possible to reduce the amount of data to be converted into a binary data format for describing a mask pattern as a layout pattern when GDS2 is created.

  The present invention is not limited to the embodiments described above, and it is obvious that the embodiments can be appropriately modified or changed within the scope of the technical idea of the present invention.

  The program in the present invention may be recorded on a computer-readable storage medium and read from the storage medium into an information processing device (computer).

FIG. 1 is a flowchart showing an automatic placement and routing method in Japanese Patent Laid-Open No. 2001-274255. FIG. 2 is a plan view showing a layout pattern of a dummy pattern for CMP in Japanese Patent Laid-Open No. 2001-274255. FIG. 3 is a block diagram showing a configuration of the layout device of the semiconductor integrated circuit according to the embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the storage medium of the layout apparatus according to the embodiment of the present invention. FIG. 5 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 6 is a conceptual diagram showing a method for arranging fill metal and actual wiring. FIG. 7 is a plan view showing an example of the layout pattern after the floor plan (S1). FIG. 8 is a plan view showing an example of the layout pattern after the floor plan (S2). FIG. 9 is a plan view showing an example of the layout pattern after the placement / wiring (S4). FIG. 10 is a plan view showing an example of a layout pattern in which fill metal is arranged. FIG. 11 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 12 is a plan view showing an example of the layout pattern after the process (S8) of deleting the fill metal overlapping the wiring. FIG. 13 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 14 is a flowchart showing the operation of the layout device of the semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 15 is a plan view showing an example of the layout pattern after the placement / wiring (S4). FIG. 16 is a plan view showing an example of a layout pattern after the fill metal 1 is formed into a solid shape (S14).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Fill metal 2 Wiring grid 3 Real wiring 4 Peripheral area 5 Macro 6 Solid fill metal 10 Computer apparatus 11 Server 12 Storage medium 13 Network 15 Design program 16 Database 21 Floor plan A part 22 Floor plan B part 23 Power supply wiring part 24 Arrangement・ Wiring section 25 Verify section 26 GDS creation section 31 Library 32 Circuit information file 33 Design rule file 101 Dummy wiring 102 Dummy pattern 103 Fixed potential node 104 Actual wiring

Claims (19)

Arranging a dummy pattern in the first region at a predetermined size and interval so as to have a predetermined metal density at the time of floorplan;
Placing logic circuit cells in the first region and performing wiring so as to satisfy timing constraints while performing timing analysis; and
And a step of verifying whether a layout pattern generated by arranging and wiring the logic circuit cells satisfies a standard. The semiconductor integrated circuit layout method according to claim 1,
The dummy pattern is arranged at a grid point of a wiring grid in the first region. The semiconductor integrated circuit layout method according to claim 1,
The dummy pattern is a rectangle having a standard wiring width uniquely determined by a semiconductor process design standard. The semiconductor integrated circuit layout method according to claim 1,
The method for laying out a semiconductor integrated circuit, wherein the dummy pattern has a wiring attribute for identifying a difference from the wiring. The semiconductor integrated circuit layout method according to claim 1,
The step of arranging the dummy pattern includes:
After placing the dummy pattern, comprising placing a macro in the first region,
The dummy pattern does not have a wiring attribute for identifying the difference from the wiring,
Furthermore,
After the step of placing the dummy pattern, deleting the dummy pattern overlapping the macro;
A method for laying out a semiconductor integrated circuit, comprising: after the step of performing wiring, deleting the dummy pattern overlapping the wiring. The semiconductor integrated circuit layout method according to claim 1,
The step of arranging the dummy pattern includes:
Placing a macro in the first region;
Placing the dummy pattern in a region of the first region where the macro is not disposed,
Furthermore,
A method of laying out a semiconductor integrated circuit, comprising the step of deleting the dummy pattern overlapping the wiring after the step of performing the wiring. The semiconductor integrated circuit layout method according to claim 1,
After the step of performing the wiring, determining whether there is a second region in which the wiring interval of the wiring is equal to or greater than the first interval;
Extracting a third region of the dummy pattern separated from the wiring by a second interval smaller than the first interval in the second region; and
And further comprising the step of integrating the dummy patterns in the third region. The semiconductor integrated circuit layout method according to claim 7,
A layout method of a semiconductor integrated circuit having a relationship of Y = 2 × X, where Y is the first interval and X is the second interval. The semiconductor integrated circuit layout method according to claim 7,
The method of laying out a semiconductor integrated circuit, wherein the second interval uses the number of lattices of a dummy pattern that is not a coupling capacitance extraction target when coupling capacitance is extracted in the verification.   A program that causes a computer to execute the layout method of the semiconductor integrated circuit according to claim 1. A floor plan portion that arranges dummy patterns in the first region at predetermined dimensions and intervals so as to achieve a predetermined metal density during floor planning;
In the first region, a logic circuit cell is arranged so as to satisfy timing constraints while performing timing analysis.
A semiconductor integrated circuit layout apparatus comprising: a verify unit that verifies whether a layout pattern generated by arranging and wiring the logic circuit cells satisfies a standard. The semiconductor integrated circuit layout device according to claim 11.
The dummy pattern is arranged at a grid point of a wiring grid in the first region. A semiconductor integrated circuit layout device. The semiconductor integrated circuit layout device according to claim 11.
The dummy pattern is a rectangular with a standard wiring width uniquely determined by a semiconductor process design standard. The semiconductor integrated circuit layout device according to claim 11.
The layout pattern of a semiconductor integrated circuit, wherein the dummy pattern has a wiring attribute for identifying a difference from the wiring. The semiconductor integrated circuit layout device according to claim 11.
The floor plan section
A first floor plan portion in which the dummy pattern is disposed;
A second floor plan unit that arranges macros in the first region,
The dummy pattern does not have a wiring attribute for identifying the difference from the wiring,
The second floor plan unit deletes the dummy pattern overlapping the macro after the step of arranging the dummy pattern,
The layout / wiring unit, after performing the wiring, deletes the dummy pattern overlapping the wiring. A semiconductor integrated circuit layout device. The semiconductor integrated circuit layout device according to claim 11.
The floor plan section
A first floor plan unit for arranging macros in the first region;
A second floor plan unit for arranging the dummy pattern in a region where the macro is not arranged in the first region;
The layout / wiring unit, after performing the wiring, deletes the dummy pattern overlapping the wiring. A semiconductor integrated circuit layout device. The semiconductor integrated circuit layout device according to claim 11.
The placement / wiring section is
After performing the wiring, it is determined whether there is a second region where the wiring interval of the wiring is equal to or greater than the first interval,
In the second region, the third region of the dummy pattern that is separated from the wiring by a second interval smaller than the first interval is extracted,
A semiconductor integrated circuit layout device for integrating the dummy patterns in the third region. The semiconductor integrated circuit layout device according to claim 17.
A layout device of a semiconductor integrated circuit having a relationship of Y = 2 × X, where Y is the first interval and X is the second interval. The semiconductor integrated circuit layout device according to claim 17.
The semiconductor integrated circuit layout device uses the number of dummy pattern lattices that are not subject to coupling capacitance extraction when extracting the coupling capacitance in the verification.

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