JP3237991B2 - Path constraint generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path constraint generation method for designing a timing optimization of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as LSIs)
Is typically configured to synchronize operations with a synchronization signal (referred to as a clock) to ensure operation. For that purpose, the propagation time of a signal transmitted between storage elements (a flip-flop, hereinafter referred to as FF) needs to be within one clock cycle.

[0003] Verification of this is called timing verification, and there is a path analysis as its means. For path analysis, see F.A. F. Is connected to the virtual start point and the input terminal is connected to the virtual end point, and a path longer than the timing specification is extracted by searching for the longest path between the start point and the end point with a delay as a cost. Then, based on the information, it is necessary to automatically / manually make improvements and changes in the circuit configuration and circuit layout.

Recent advances in VLSI miniaturization techniques have made it possible to realize large-scale integrated circuits. When the circuit becomes large, the number of paths increases explosively. According to the invention of the present inventors, a path having the longest delay can be extracted by successively passing through the nets of the highest rank from the start point. A path can be represented by a quaternary set of (a parent path of a derivation source, a branch point cell, a branch destination cell, and a path delay), and the information amount is reduced by one in comparison with the conventional method of expressing a chain of cells and nets. / 2
It can be set to 0/1/100. Furthermore, in order to suppress the explosion of combination of paths, by marking a branch point once passed so that it is not selected twice, it is possible to suppress the number of paths from an exponential function order to a polynomial order. . However, even in this method, the number of critical nets is 1/4 to 1/2 of all nets, and the restrictions are considerably large.

As a constraint generation method for layout, Ze is used.
There is ro Slack Algorithm. (Ha
Uge, P .; S. Other, "Circuit Placem
ent for Predicable Perfo
rmance ", IEEE.ICCAD'87.) This method is an algorithm for allocating slack to a net so that all paths have the same actual delay as the specification, but propagates the allocated path delay before and after the path. Needed and not efficient.

[0006] Another method is that of our earlier invention. In this method, restrictions are formed by sequentially allocating delays to each net for the obtained critical path. This method also has a problem of propagation of the amount of delay reduction. Also, by adding restrictions to other paths, no special attention is paid to nets and paths that are no longer critical paths, and unnecessary restrictions are generated.

[0007]

However, there is a problem that the number of extracted paths explosively increases when the scale of a network to be handled increases. Further, there has been no known method of allocating a necessary delay reduction amount without transmitting the obtained delay reduction amount once set to the critical path to another path.

An object of the present invention is to provide a timing constraint generation method based on a critical path to be considered when performing timing optimization by automatic layout, logic synthesis, or the like with a sufficiently small number of paths to solve such a problem. Aim.

[0009]

In order to solve the above-mentioned problems, the present invention provides a means for executing a critical path extraction and a delay reduction amount α for each net from (path delay, timing specification, wiring delay in path). Is calculated for each path, means for sorting α in ascending order, and the sum of the delay reduction amounts of the already determined nets and the delay of the original path. Path constraint generation characterized by comprising means for determining whether or not to be excluded, and means for adjusting the amount of delay in the case of being subject to path delay reduction under the influence of delay reduction of other paths. Is the way.

[0010]

[Operation] A critical path having a delay equal to or longer than the timing specification is calculated, and then the delay reduction amount α is calculated as α =
(Path delay−timing specification) / inter-path wiring delay is calculated. Then, the paths are sorted in descending order of α, so that the delay reduction amount is determined in the order of the path in which the delay reduction request for each net is strict. Based on the path delay reduction amount determined before the processing of a certain path, it is determined whether or not the path is excluded from the critical path without being subjected to delay reduction. If the path becomes a target for path delay reduction, the path delay reduction amount is adjusted so that unnecessarily strict path restrictions are not added. As a result, it is possible to add a constraint only to a necessary portion without giving a constraint to an unnecessary path net.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention. Each block is executed according to the following steps.

Step 1: A critical path is extracted. Step 2: The ratio α of the delay reduction amount is calculated. α = (path delay−spec) / inter-path wiring delay.

Step 3: The paths are sorted in descending order of α. Step 4: The following processing is performed for each path. Step 4 (a): Calculate the delay amount A already determined to be reduced in the path.

Step 4 (b): The delay reduction amount Q is
Q = (path delay−spec−A) is calculated. Step 4 (c): If Q <0, no delay constraint is imposed on the net of the path.

Step 4 (d): If Q ≧ 0, the delay reduction ratio is recalculated based on Q for the net of the path, and the delay reduction amount of each net is determined.

Step 5: The process is repeated for each path. Each of these steps will be described in more detail. First, a critical path is extracted (step 1). The critical path is typically between flip-flops
This is a path that has a delay longer than the given specifications. As an example, a state of a critical path is shown in FIG. Next, a ratio α of the delay reduction amount is calculated for each path (step 2). This is, for example,

[0017]

Α = (delay amount to be reduced) / (reducible delay amount) = (path delay−spec) / (inter-path wiring delay).

Next, the paths are sorted in ascending order of α (step 3). This process is necessary to process the delay reduction amount of a certain net from the severer one. As can be seen from FIG. 3, the amount of delay reduction added to a certain net depends not only on how much the path delay exceeds the specification, but also on the amount of delay that can be reduced (here, the wiring delay in the path). . For example, FIG. 3 shows that delay of path 1 ≦ path 2
However, the amount of delay that can be reduced is larger in pass 2. Therefore, the ratio α of the delay reduction amount is larger in the pass 1 and the strictness of the constraint is more severe in the pass 1. Next, the amount of delay reduction is calculated for the net in the path having the largest α (step 4). This is, for example,

[0019]

## EQU2 ## (delay reduction amount of the net) = α × (wiring delay of the net). At this time, the delay amount reduced from a certain net to the end point of the path is provided as information of the net. It is calculated sequentially from the end point of the path.

Next, the processing after the pass having the second largest α will be described. What is performed here is to correct the delay reduction amount calculated from α calculated in step 2 in consideration of the net to which the constraint has already been assigned (giving a looser constraint), and to assign the constraint already. If it is anticipated that the path delay will be sufficiently small due to the net being obeyed the constraint, the path is deleted from the constraint generation target.

First, the delay amount A already deleted in the path is obtained (step 4 (a)). This is achieved by tracing the path and taking the sum of the reduced delay amounts of the nets for which constraints have already been set.

Next, Q = (delay of the path-A-spec) is calculated (step 4 (b)). If Q <0, no constraint is imposed on the unconstrained net of the path. If Q ≧ 0,

[0023]

Α ′ = Q / (delay of an unconstrained net in the path) and α ′ are calculated again.

[0024]

(Equation 4) (Delay reduction of unconstrained net) =
α ′ × (net delay). The process in step 4 is repeated until there are no more paths to be processed (step 5).

In the present invention, unnecessary restrictions are not imposed on the net, and when the restrictions are imposed, the effect of the delay reduction amount that has been applied to the net is not propagated in the network. It is possible to add a constraint only to a necessary net. The present invention is not limited to the above embodiment, and is appropriately designed and changed.
It can be carried out in an appropriate manner.

[0026]

According to the present invention, unnecessary nets are not constrained, and when the constraints are imposed, the effect of the existing delay reduction amount is not propagated in the network. It is possible to add constraints only to necessary nets at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a critical path.

FIG. 3 is a graph for explaining a ratio α of a delay reduction amount.

FIG. 4 is an explanatory diagram for explaining delay reduction according to the present technique.

[Explanation of symbols]

 Step 1: Critical path extraction step Step 2: α calculation step Step 3: Sort step Step 4: Delay reduction amount calculation step Step 5: Repeat step

Claims (1)

(57) [Claims] A step of calculating a critical path; a step of determining a ratio of a delay reduction amount of each net for each path; a step of sorting paths in descending order of a calculated ratio of a delay reduction amount; A step of determining whether or not to exclude the path from the critical path without making the path a target for delay reduction based on the sum of the delay reduction amounts of the nets for which the reduction amount is determined and the delay of the path; And adjusting the amount of delay under the influence of the delay reduction of another path.