JP2002313916A - Device and method for designing layout of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for designing the layout of a semiconductor integrated circuit in which enhancement in the performance of a logic circuit, high integration of placement and routing, high speed processing, and enhancement of productivity can be realized. SOLUTION: A layout section 11 performs the layout of a designed logic circuit. A delay analysis section 15 makes a decision whether a delay error is present or not from the layout results. If the delay error is present, a relay buffer insertion section 12 inserts a relay buffer so that the delay error is eliminated. When a block becoming an obstacle for routing is present at an insertion place, a relay buffer moving section 13 alters placement to the outside of the block. If no effect of a delay error improvement is attained, a relay buffer altering section 14 alters the number or the type of the relay buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout design apparatus and a layout design method for a semiconductor integrated circuit for automatically laying out a logic circuit such as an LSI (semiconductor integrated circuit).

[0002]

2. Description of the Related Art In general, layout of circuit elements in an LSI logic circuit, such as arrangement and wiring, is performed by CAD (Computer Aided Des) using a computer.
Ign) system. Usually, this kind of CAD system (hereinafter referred to as layout design device)
Has a function of designing the layout of a logic circuit and a function of verifying whether or not the designed logic circuit satisfies a request for a delay time based on various reasons such as synchronization.

[0003] The following is a specific description. A conventional layout design apparatus performs a layout design for the purpose of shortening the total wiring length and improving the wiring property based on the logical connection information of the logic circuit. Then, the layout design device performs a delay analysis based on the result of the layout design. Here, when a path delay error occurs, the delay error has been removed by manually modifying the placement and routing, or modifying the logical connection information and re-designing the layout.

In addition, gates on paths with strict delay constraints are manually arranged close to each other in advance so as not to violate the delay constraints.
Wiring was done manually to improve delay errors. In addition, a layout design apparatus that improves a delay error by using an automatic placement and routing unit having a delay analysis unit has also been proposed. In the layout design apparatus, without changing the logical connection relationship of the logic circuit, devising a method of arrangement and wiring processing of circuit elements, until the delay error is eliminated.
Placement and wiring were repeated.

[0005]

However, in such a layout design apparatus, the placement and routing is manually corrected, and the placement and routing is repeated again until the delay constraint is satisfied based on only the logical connection information. To take a long time. Therefore, a layout design apparatus that eliminates a delay error by adopting a method of inserting a relay gate has been proposed. Examples of this type of technology include:
JP-A-6-243199, JP-A-6-33404
No. 2, JP-A-9-293094 and the like.

Japanese Patent Application Laid-Open No. 6-243199 discloses that when a buffer gate is inserted, the buffer gate is inserted before the intermediate point between the former element and the latter element. As a method therefor, there is shown a method of setting a spare gate area irrelevant to logic in a specific area of a chip. In addition, Japanese Patent Application Laid-Open No. 6-334042 discloses a method in which a layout pattern is limited in order to make it unnecessary to secure a relay buffer insertion position. However, Japanese Patent Application Laid-Open
According to the prior art disclosed in Japanese Patent Application Laid-Open No. 243199/1994 and Japanese Patent Application Laid-Open No. 6-334042, there is a problem that the degree of freedom in layout must be limited in order to secure a spare area which may become unnecessary in advance. There is.

On the other hand, in Japanese Patent Application Laid-Open No. 9-293094, if a specific spare area is not provided and another circuit element is present at the position where the relay gate is arranged, the arrangement of the relay gate is prioritized. A method of shifting the position of a circuit element is shown. However, according to the prior art disclosed in Japanese Patent Application Laid-Open No. 9-293094, other circuit elements located at positions where relay buffers should be arranged include a RAM (random access memory), a ROM (read only memory), RF
(Register file) and other hard macros,
In the case of an element such as a clock generation / distribution system and a manually designed macro such as a data path, it cannot be operated automatically. In such a case, the relay buffer is moved to a position where the relay buffer can be arranged in the vicinity thereof. However, since such a circuit block is generally huge, the moving distance is 0.5 to 1 mm.
mm or more. Therefore, the increment of the wiring length due to the movement is
There is a problem that the delay cannot be improved even if a relay buffer is inserted.

A conventional buffer insertion process will be described below with reference to FIGS. As shown in FIG. 2, the layout design apparatus lays out a flip-flop 201, a flip-flop 206, and a gate 202 to a gate 205. Next, the layout design device performs a delay analysis process on the layout. As a result of this analysis, it is assumed that a delay error is detected between the flip-flop 201 and the flip-flop 206. The layout design apparatus specifies the number, arrangement position, and driving capability of the relay buffers for which the delay time is improved, and as shown in FIG. 3, replaces the relay buffers 501 and 502 with the same driving force as the gate 203,
The wiring 209 is inserted at a position where the wiring 209 is equally divided into three. Here, as shown in FIG. 2 described above, when another circuit block 401 that causes a wiring failure exists at the insertion position of the relay buffer, the layout design apparatus moves to an area where the relay buffer can be arranged. If the block 401 causing the wiring failure is a huge macro as described above, there is a problem that the delay time may not be improved.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to improve the performance of a designed logic circuit by effectively performing a placement and wiring correction process involving the insertion of a relay buffer. It is another object of the present invention to provide a layout design apparatus which enables high integration of arrangement and wiring and high-speed processing.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the invention according to claim 1 is based on logical connection information of a semiconductor integrated circuit to be designed. Layout means for arranging circuit elements and wiring the circuit elements; delay analysis means for performing delay analysis processing on a layout obtained by the layout means; If the delay characteristics of the relay buffer cannot be obtained, a buffer insertion unit that inserts a relay buffer into the wiring connecting the circuit elements and another insertion position of the relay buffer so that the delay characteristics are improved. When there is a circuit block, a buffer moving means for moving the relay buffer out of the other circuit block; and a layout obtained by moving the relay buffer. Then, a delay analysis process is performed, and when a desired delay characteristic cannot be obtained between the circuit elements, the electrical characteristic of the relay buffer or an element in the circuit is changed so that the delay characteristic is improved. A layout designing apparatus for a semiconductor integrated circuit, comprising: a buffer changing unit for changing the buffer.

The invention described in claim 2 is the first invention.
In the layout design apparatus for a semiconductor integrated circuit according to the above, the delay analysis means may include: an electrical characteristic storage unit that retains electrical characteristics of wiring and circuit elements; and a delay that retains a limit value of a delay time between the circuit elements. An information storage unit, based on the layout obtained by the layout unit, reads the electrical characteristics of the wiring and the circuit element from the electrical storage unit, and calculates a delay time between the circuit elements from the electrical characteristic. A delay analysis processing unit for calculating and reading the limit value from the delay information storage unit, comparing the delay time with the limit value, and detecting the presence or absence of a delay error between the circuit elements. And

Further, the invention described in claim 3 is the first invention.
Wherein the buffer insertion means selects the type, number, and arrangement position of the relay buffer so as to eliminate the delay error. According to a fourth aspect of the present invention, in the semiconductor integrated circuit layout designing apparatus according to the first aspect, the buffer moving means moves the circuit block in addition to moving the relay buffer. It is characterized by the following.

The invention described in claim 5 is the first invention.
Wherein the buffer changing means changes the type and the number of the relay buffers.

According to a sixth aspect of the present invention, there is provided a layout unit for arranging each circuit element and wiring the circuit element based on logical connection information of a semiconductor integrated circuit to be designed, and the layout unit. Delay analysis means for performing delay analysis processing on the obtained layout; and as a result of the delay analysis processing, when a desired delay characteristic cannot be obtained between the circuit elements, the circuit element is designed to improve the delay characteristic. A layout design apparatus for a semiconductor integrated circuit, comprising: a buffer deleting means for deleting a buffer in the semiconductor integrated circuit.

According to a seventh aspect of the present invention, a layout process for wiring each circuit element is performed based on logical connection information of a semiconductor integrated circuit to be designed, and a delay is applied to a result of the layout process. Performing an analysis process, if a desired delay characteristic is not obtained between the circuit elements as a result of the delay analysis process, a relay buffer is connected to a wiring connecting the circuit element so that the delay characteristic is improved. Insert
If there is another circuit block at the insertion position of the relay buffer, move the relay buffer out of the other circuit block and move the relay buffer to a layout obtained. And delay analysis processing,
When a desired delay characteristic cannot be obtained between the circuit elements,
A layout design method for a semiconductor integrated circuit, characterized in that electrical characteristics of the relay buffer are changed so that the delay characteristics are improved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A layout design apparatus according to the present embodiment will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the layout design apparatus according to the embodiment. Reference numeral 11 denotes a layout processing unit that arranges each circuit element based on logical connection information of a semiconductor integrated circuit to be designed and wires the circuit elements. Reference numeral 12 denotes a buffer insertion processing unit that inserts a relay buffer into a wiring in which a delay error has been detected so as to reduce the delay time.
Reference numeral 13 denotes a buffer movement processing unit that moves the relay buffer to an area where it can be arranged when another circuit block exists at the insertion position of the relay buffer. Reference numeral 14 denotes a buffer change processing unit that performs delay analysis again on the layout result after the buffer moving process, and changes the type and number of relay buffers when a delay error is detected. Reference numeral 15 denotes a delay analysis processing unit that performs a delay analysis on the layout obtained by the layout processing unit 11. The storage unit 16 includes a delay information storage unit 161 that stores a delay constraint that is an upper limit value of a delay time, and an electric characteristic storage unit 162 that stores electric characteristics of circuit elements and wirings.

FIG. 2 is a diagram showing a layout by the layout design processing unit 11 of the layout design apparatus according to the embodiment. FIG. 3 is a diagram showing a layout by the buffer insertion processing unit 12 of the layout design apparatus according to the embodiment. FIG. 4 is a diagram showing a layout by the buffer change processing unit 14 by the layout device of the embodiment. In FIG. 2, 201 and 206 are flip-flops, and 202 to 205 are gates. 40
1 is a wiring 20 connecting the gate 203 and the gate 204
9, which is a block that causes an arrangement failure. In FIG. 3, reference numerals 501 and 502 denote relay buffers for improving wiring delay.

The operation (method) of this embodiment will be described below. Based on the logical connection information of the semiconductor integrated circuit to be designed, the layout processing unit 11 performs a layout process of arranging each circuit element and wiring between the circuit elements. As shown in FIG. 2, the layout processing unit 11 arranges flip-flops 201 and flips 206, and gates 202 to 205, and connects each circuit element with a wiring 207 to a wiring 211.

On the basis of the layout obtained by the layout processing section 11, the delay analysis processing section 15 derives the wiring length between the individual circuit elements. Next, the delay analysis processing unit 1
Reference numeral 5 reads the wiring resistance and the wiring capacitance with respect to the wiring length and the output impedance of the gate for driving the wiring from the electrical characteristic storage unit 162 in the storage unit 16. Using these parameters, the delay analysis processing unit 15 calculates a delay time between each circuit element. Further, the delay analysis processing unit 15 reads the delay constraint from the delay information storage unit 161, compares the delay time with the delay constraint, and detects the presence or absence of a delay error.

Here, it is assumed that a delay error is detected between the flip-flop 201 and the flip-flop 206. The buffer insertion processing unit 12 selects an optimum type, number, and wiring position of the relay buffer in which the delay error is eliminated from the wiring resistance and the wiring capacity with respect to the wiring length and the driving force of the gate. Then, the buffer insertion processing unit 12 inserts the selected relay buffer between the circuit elements in which the delay error has been detected. In this case, the buffer insertion processing unit 12
A position where the arrangement position divides the wiring 209 into three equal parts is selected, and the relay buffer 501 having the same driving force as the gate 205 is selected.
Then, the relay buffer 502 is provisionally inserted.

With respect to the layout after the buffer insertion processing, the delay analysis processing unit 15 stores the driving force (for example, output impedance), the wiring resistance and the wiring capacitance with respect to the wiring length from the electrical characteristic storage unit 162 in the storage unit 16 Is read, and the delay time of the wiring is calculated. Further, the delay analysis processing unit 15 reads out the delay constraint from the delay information storage unit 161 in the storage unit 16. Then, the delay analysis processing unit compares the delay time with the delay constraint and detects the presence or absence of a delay error.

Next, it is assumed that there is a block 401, which is selected by the buffer insertion processing unit 12, and is located at the insertion position of the relay buffer 501 and the relay buffer 502, which is an obstacle to the arrangement. The buffer movement processing unit 13 moves to a region outside the block and in which the relay buffer can be arranged.
In this example, on the wiring path 209, the block 20
9 is moved to the vicinity of the relay buffer. Based on the layout changed by the buffer movement processing unit 13,
The delay analysis processing unit 15 calculates a delay time between the flip-flop 201 and the flip-flop 206 and detects whether or not there is a delay error.

Next, it is assumed that the delay analysis processing unit 15 detects a delay error because the block 401 is a huge macro. Then, the buffer change processing unit 14
Change the driving force and number of the moved relay buffers. More specifically, in FIG.
4 changes the relay buffer 501 to a high-drive buffer.
The delay analysis processing unit 15 performs a delay analysis process based on the layout changed by the buffer change processing unit 14, and detects the presence or absence of a delay error. When the delay error has been eliminated, the layout design apparatus determines the type, number, and arrangement position of the relay buffers. As described above, an optimal layout is obtained. When the final type, number, and arrangement position of the relay buffers are determined, the layout processing unit 11 performs the layout processing again. Further, in the above embodiment, the buffer moving processing unit 13 moves the relay buffer to the vicinity of the block 209. However, the present invention is not limited to this, and the buffer moving processing unit 13 may move the block 209 which is another circuit block. Is also possible. further,
Although the buffer change processing unit 14 has described the change to the inserted relay buffer, the present invention is not limited to this, and it is also possible to change the electrical characteristics of the circuit element.

Hereinafter, the delay analysis processing unit 15 of this embodiment will be described.
The method for improving the delay characteristics by the method will be described. However, the method of calculating the delay shown here is one example, and in practice, a calculation means suitable for the technology used and the analysis accuracy is used. The delay analysis processing unit 15 calculates the wiring delay time T from the layout result obtained by each means.
For each wiring, the delay analysis processing unit 15
The wiring capacitance CL, the wiring resistance RL, and the output impedance Ro of the gate to be driven are read from the electrical characteristic storage unit 162 in the memory 6. From these read parameters, the delay analysis processing unit 15 calculates the wiring delay time T by the following equation (1). T = K · CL (Ro + RL) (1) where K is a proportional constant.

For example, as a result of laying out by the layout design processing section 11, the wiring length between the arranged circuit elements is 1
When 0L (L is unit length), Cl is wiring capacity per unit length, and Rl is wiring resistance per unit length, equation (1) is expressed as the following equation (2). T1 = K · 10Cl (Ro + 10Rl) (2) T1 is a delay time of the wiring after the layout processing is performed, and has a magnitude proportional to 10Cl (Ro + 10Rl). It is assumed that the delay analysis processing unit 15 detects a delay error in the wiring. The buffer insertion processing unit 12 selects the optimum driving force, number, and insertion position for improving the delay time of the wiring.

Then, it is assumed that the buffer insertion processing unit 12 selects the driving force of the relay buffer equivalent to the gate driving the wiring, and inserts the relay buffer at a position where the wiring is divided into three. Wiring delay time T2 in this case
Is expressed by the following equation (3) using the equation (2). T2 = K · {3.3Cl (Ro + 3.3Rl) · 3} (3) The delay analysis processing unit 15 detects the presence or absence of a delay error of the wiring based on the result of Expression (3). .

Next, it is assumed that there is a block that causes a wiring failure at the insertion position of the relay buffer. The buffer movement processing unit 13 moves the relay buffer to an area outside the block and in which it can be arranged. From the layout result obtained by moving the buffer, the wiring length is 1: 5.7: 3.
When it becomes 3, the wiring delay time T3 is expressed by the following equation (4) using the equation (2). T3 = K ｛{Cl (Ro + R1) + 5.7Cl (Ro + 5.7R1) + 3.3Cl (Ro + 3.3Cl)} (4) The delay analysis processing unit 15 is based on the calculation result of Expression (4). Then, the presence or absence of the delay error of the wiring is detected.

Next, it is assumed that a delay error of the wiring is detected because the block causing the wiring is a huge macro. The buffer change processing unit 14 changes the type or number of the relay buffer to reduce the delay time. For example, when the driving force of a gate for driving a wiring having a longer wiring length is increased, the output impedance of the gate is reduced. Here, it is assumed that the relay buffer change processing unit 14 increases the driving force of the gate having the longest distance, and the output impedance of this gate is halved. The wiring delay time T4 at this time is expressed by the following equation (5) using the equation (2). T4 = K · {Cl (Ro + R1) + 5.7Cl (0.5Ro + 5.7R1) + 3.3Cl (Ro + 3.3Cl)} (5) The delay analysis processing unit 15 calculates the result of equation (5). , The presence or absence of a delay error is detected. As described above, the delay characteristics can be improved. Also, this layout design device
In each process, when the delay error is no longer detected, the layout processing unit 11 performs a layout design process.

In the above-described embodiment, a method for reducing the delay time with respect to the maximum constraint on the delay time is described. However, the method for increasing the delay time with respect to the minimum constraint is also the same. Taken by Also, the improvement is made by inserting a buffer.

[0030]

As described above, according to the present invention, layout processing is performed on a logic circuit to be designed,
By inserting a relay buffer into a path when a delay error occurs between circuit elements, the effect of improving delay characteristics can be obtained. In addition, if there is a block that causes a wiring failure at the position where the relay buffer is inserted, the relay buffer is automatically moved to an area where the relay buffer can be arranged outside this block, thereby minimizing a change in delay time. An effect that can be suppressed can be obtained. If the delay error has not been improved as a result of the buffer moving process, the effect of improving the delay characteristics can be obtained by changing the type and number of the relay buffers.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a structure of a layout design apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a layout result before delay analysis by the layout design apparatus according to the embodiment of the present invention;

FIG. 3 is a diagram showing a layout result after a relay buffer is inserted by the layout design apparatus according to the embodiment of the present invention;

FIG. 4 is a diagram showing a layout result after changing a relay buffer of the layout designing apparatus according to the embodiment of the present invention;

[Explanation of symbols]

11: layout processing unit, 12: buffer insertion processing unit,
13 buffer transfer processing unit, 14 buffer change processing unit, 15 delay analysis processing unit, 16 storage unit, 161 delay information storage unit, 162 electrical characteristic storage unit, 201, 2
06: flip-flop, 202, 203, 204, 2
05: gate, 401: block causing wiring failure, 50
1, 502... Relay buffer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA05 BA06 JA01 5F064 AA06 BB02 BB19 BB26 DD02 DD12 DD13 DD14 EE08 EE42 EE43 EE47 FF07 FF09 FF52 HH06 HH09 HH10

Claims (7)

[Claims] 1. A layout means for arranging each circuit element and wiring the circuit element based on logical connection information of a semiconductor integrated circuit to be designed, and a delay analysis for a layout obtained by the layout means. Delay analysis means for performing processing, as a result of the delay analysis processing, if a desired delay characteristic is not obtained between the circuit elements, so that the delay characteristic is improved,
Buffer inserting means for inserting a relay buffer into a wiring connecting the circuit elements; and buffer moving means for moving the relay buffer when another circuit block exists at the insertion position of the relay buffer. A delay analysis process is performed on a layout obtained by moving the relay buffer, and when a desired delay characteristic cannot be obtained between the circuit elements, the relaying is performed so that the delay characteristic is improved. And a buffer changing means for changing an electrical characteristic of an element in the circuit or a circuit in the circuit. 2. The delay analysis unit includes: an electrical characteristic storage unit that holds electrical characteristics of wiring and circuit elements; a delay information storage unit that holds a limit value of delay time between circuit elements; The electrical characteristics of the wiring and the circuit element are read from the electrical storage unit based on the layout obtained by the means, a delay time between the circuit elements is calculated from the electrical characteristic, and the delay information storage is performed. A delay analysis processing unit that reads the limit value from the unit, compares the delay time with the limit value, and detects whether or not there is a delay error between the circuit elements. A layout design apparatus for a semiconductor integrated circuit according to the above. 3. The layout of a semiconductor integrated circuit according to claim 1, wherein said buffer inserting means selects the type, number, and arrangement position of said relay buffers so as to eliminate said delay error. Design equipment. 4. The semiconductor integrated circuit layout designing apparatus according to claim 1, wherein said buffer moving means moves said circuit block in addition to moving said relay buffer. 5. The apparatus according to claim 1, wherein the buffer change unit changes the type and the number of the relay buffers.
2. A layout design apparatus for a semiconductor integrated circuit according to claim 1. 6. A layout unit for arranging each circuit element and wiring the circuit element based on logical connection information of a semiconductor integrated circuit to be designed, and a delay analysis for a layout obtained by the layout unit. Delay analysis means for performing processing; and buffer deletion means for deleting a buffer in the circuit element so as to improve the delay characteristic when a desired delay characteristic cannot be obtained between the circuit elements as a result of the delay analysis processing. A layout design apparatus for a semiconductor integrated circuit, comprising: 7. A layout processing for wiring each circuit element is performed based on logical connection information of a semiconductor integrated circuit to be designed, a delay analysis processing is performed on a result of the layout processing, and the delay analysis processing is performed. As a result, if a desired delay characteristic is not obtained between the circuit elements, a relay buffer is inserted into a wiring connecting the circuit elements so that the delay characteristic is improved, When another circuit block is present at the insertion position, the relay buffer is moved out of the other circuit block, and a delay analysis process is performed on a layout obtained by moving the relay buffer. And when the desired delay characteristics cannot be obtained between the circuit elements, the electrical characteristics of the relay buffer are changed so that the delay characteristics are improved. Layout design method of the body integrated circuit.