JPH04340173A - Scan pass logic verifying system - Google Patents

Abstract

PURPOSE:To surely execute the verification of scan pass logical connection in a CAD. CONSTITUTION:A model information storing means 1 stores a simulation model, scan pass wiring order indicating the order of flip flops(FFs) and scan pass control signal information defining a control signal for driving a scan pass. A simulation control instruction output means 2 applies codes inherent in respective FFs to respective FFs as respective initial status values based upon the stored information and forms an instruction for executing code propagation simulation for propagating respective codes on the scan pass. A code propagation simulation executing means 3 executes code propagation simulation in accordance with the instruction. An expected value comparing means 5 compares an expected value formed by an expected value generating means 4 with a simulation result obtained from the means 3 to discriminate whether the logical connection of the scan pass is invalid or not.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path logic verification method for checking logical connections of scan paths using a logic simulator.

0002

[Prior Art] When checking the logical connection of a scan path using a logic simulator, conventionally, the scan path is determined by using logical values (0, 1, undefined value X, high impedance Z) as state values of signals in the circuit. I was running a simulation to get it working.

0003

[Problems to be Solved by the Invention] As mentioned above, in the past, simulations were performed using logical values as state values of signals in the circuit, so the simulation result of a certain flip-flop on the scan path was not the expected value. Even if they match, it is not possible to determine whether the state value of that flip-flop is propagated from the flip-flop connected immediately before the scan path or from another part. That is, the conventional method described above has a problem in that the logical connection of scan paths cannot be guaranteed only by comparing expected values.

An object of the present invention is to enable reliable verification of the logical connections of scan paths.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a scan path logic verification method for verifying logical connections of scan paths, which includes a simulation model of a logic circuit including the scan path, and a simulation model of a logic circuit including the scan path. model information storage means storing a scan path wiring order indicating the order of flip-flops on the campus and scan path control signal information defining a control signal for operating the scan path; an instruction to give a symbol unique to each flip-flop as an initial state value to each flip-flop on the scan path, and a state value of the output terminal of the scan path, based on the scan path wiring order and scan path control signal information; a simulation control command output means for creating an observation command and a command for instructing execution of the simulation; a simulation model stored in the model information storage means; and each command created by the simulation control command output means. a symbol propagation simulation execution means for performing a symbol propagation simulation based on the model information storage means; an expected value creation means for creating an expected value at each time of the simulation based on the scan path wiring order stored in the model information storage means; Expected value comparison means for determining whether or not there is an irregularity in the logical connection of the scan path by comparing the simulation result by the symbol propagation simulation execution means and the expected value created by the expected value creation means. It is.

[0006]

[Operation] The simulation control command output means sets an initial state value to each flip-flop on the scan path based on the scan path wiring order and scan path control signal information stored in the model information storage means. An instruction to give a symbol, an instruction to observe the state value of the scan path output terminal, and an instruction to instruct execution of the simulation are created. The symbol propagation simulation execution means performs a symbol propagation simulation based on the simulation model stored in the model information storage means and the command created by the simulation control command output means, and outputs the simulation result. This simulation result is compared in the expected value comparing means with the expected value created by the expected value creating means, and it is determined whether or not there is an irregularity in the logical connection of the scan path.

[0007]

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a model information storage means 1, a simulation control command output means 2, a symbol propagation simulation execution means 3, an expected value creation means 4, and an expected value comparison means. It is composed of means 5.

FIG. 2 is a flowchart showing a processing example of the model information storage means 1, in which the model information storage means 1 performs a request reception process 11, a request determination process 12, a simulation model output process 13, and a scan path wiring order output. Processing 14 and scan path control signal information output processing 15 are performed.

FIG. 3 is a flowchart showing an example of processing by the simulation control command output means 2, in which the simulation control command output means 2 performs a scan path wiring order request process 21, a scan path wiring order input process 22, and a scan path control signal Information request processing 23, scan path control signal information input processing 24, and control signal status value setting command creation processing 2
5, scan path state value setting command creation processing 26, scanout observation command creation processing 27, simulation execution command creation processing 28, and command output processing 29 are performed.

FIG. 4 is a flowchart showing a processing example of the symbol propagation simulation execution means 3, in which the symbol propagation simulation execution means 3 performs the simulation model input processing 31.
, instruction input processing 32 , symbol propagation simulation execution processing 33 , and flip-flop (F/F) calculation processing 3
4, combinational circuit calculation processing 35, and simulation result output processing 36.

FIG. 5 is a flowchart showing an example of processing by the expected value creating means 4, in which the expected value creating means 4 performs a scan path wiring order request process 41, a scan path wiring order input process 42, a command input process 43, Expected value creation processing 44 and expected value output processing 45 are performed.

FIG. 6 is a flow chart showing a processing example of the expected value comparing means 5, in which the expected value comparing means 5 performs a simulation result input process 51, an expected value input process 52, an expected value comparison process 53, and a mismatch path output process. Processing 54 is performed.

The model information storage means 1 stores logic circuit design data (for example, netlist, etc.), scan path wiring order (order of flip-flops on the scan path), and scan path control signal information (for operating the scan path). the name of the scan path control terminal that inputs the scan path control signal, the state value set to the scan path control terminal when operating the scan path, and the name of the clock input terminal that inputs the clock pulse that operates the scan path). It is stored. In addition, the scan path wiring order,
The scan path control signal information is specified by the circuit designer.

Then, in response to reference requests from the simulation control command output means 2, the symbol propagation simulation execution means 3, the expected value creation means 4, and the expected value comparison means 5, the processing shown in FIG. 2 is performed. That is, a reference request is received by the request reception process 11, and the type of requested information is determined by the request determination process 12. Then, if the requested information type is a simulation model, the simulation model output process 13 is performed, if the requested information is the scan path wiring order, the scan path wiring order output process 14 is performed, and if the requested information is the scan path control signal information, the scan path output process 13 is performed. Control signal information output processing 15 is performed.

In the simulation model output process 13, a simulation model is created based on logic circuit design data (eg, a netlist, etc.), and the created simulation model is output. Note that it is also possible to store a simulation model in the model information storage means 1 in advance and omit the process of creating a simulation model from design data. In the scan path wiring order output process 14, the order of flip-flops connected to the scan path specified by the circuit designer is output as the scan path wiring order. Scan path control signal information output processing 1
5 shows the name of the scan path control terminal that inputs the scan path control signal to operate the scan path specified by the circuit designer, the state value to be set to the scan path control terminal when operating the scan path, and the scan path control terminal. Outputs scan path control signal information consisting of the name of the clock input terminal that inputs the clock pulse that operates the campus.

As shown in FIG. 3, the simulation control command output means 2 outputs a scan path wiring order reference request to the model information storage means 1 in the scan path wiring order request processing 21. In the next scan path wiring order input process 22, the scan path wiring order outputted by the model information storage means 1 in response to the reference request is received.

Next scan path control signal information request processing 2
3, a process is performed to output a reference request for scan path control signal information to the model information storage means 1,
In the scan path control signal information input process 24, a process is performed to receive the scan path control signal information output by the model information storage means 1 in response to the reference request.

In the control signal state value setting command creation process 25, based on the scan path control signal information received in the scan path control signal information input process 24, a command is sent to the scan path control terminal to operate the scan path in the logic simulation. Create an instruction to set a state value and an instruction to set a clock pulse for operating a scan path to a clock input terminal.

[0020] Scan path status value setting command creation process 26
Now, based on the scan path wiring order received in the scan path wiring order input process 22, a unique symbol is assigned to the scan path input terminal and each flip-flop on the scan path as the initial value of the state value used in the symbol propagation simulation. Create an instruction to configure.

In the scan-out observation command creation process 27, a command for observing the state value of the scan path output terminal during simulation is created based on the scan path wiring order received in the scan path wiring order input process 22.

In the simulation execution command creation process 28, the number of flip-flops on the scan path is calculated based on the scan path wiring order received in the scan path wiring order input process 22, and further, the number of flip-flops on the scan path is calculated by multiplying the period of the clock pulse by the number of flip-flops. Create an instruction to perform the simulation for a time corresponding to .

In command output processing 29, the commands created in control signal state value setting command creation processing 25, scan path state value setting command creation processing 26, scan out observation command creation processing 27, and simulation execution command creation processing 28 are output.

As shown in FIG. 4, the symbol propagation simulation execution means 3 performs a simulation model input process 31.
At this point, a simulation model reference request is output to the model information storage means 1, and in response to this reference request, the simulation model outputted by the model information storage means 1 is input.

Further, the symbol propagation simulation execution means 3 inputs each command outputted by the simulation control command output means 2 in the command input processing 32. In the next symbol propagation simulation execution process 33, a simulation is performed according to the input instructions. At this time, the flip-flop is simulated by the flip-flop calculation process 34, and the other logic elements are simulated by the combinational circuit calculation process 35. In the flip-flop calculation process 34, the state value of the signal held by the flip-flop is determined according to the state value of the signal input to the flip-flop. If the state value is a logical value, the logical value is retained; if the state value is a symbol, the symbol is retained. In addition, in the combinational circuit arithmetic processing 35, if all the state values input to the logic element are logical values, the value of the logic element is determined as is, and if the input state value includes a symbol, it is undefined. A value X is determined as the simulation state value of the logic element.

In the simulation result output processing 36, observed state values are output.

As shown in FIG. 5, the expected value creation means 4 outputs a scan path wiring order reference request to the model information storage means 1 through a scan path wiring order request processing 41, and in response to this reference request, The scan path wiring order outputted by the model information storage means 1 is received by the scan path wiring order input processing 42.

In the next command input process 43, the simulation control command output means 2 inputs the command created in the scan path status value setting command creation process 26, and sets each of the scan paths on the scan path as an initial value in the simulation. Obtain the symbol to be set to the flip-flop and scan path input terminal.

In the expected value creation process 44, the scan path wiring order received in the scan path wiring order input process 42 is referred to, and in the simulation, each period of the clock pulse input to the clock input terminal is set on the scan path. The symbols of each flip-flop on the scan path are propagated from the output of that flip-flop to the next flip-flop connected by the scan path, and the symbols of the flip-flops on the scan path are propagated from the output of that flip-flop to the next flip-flop connected by the scan path. The expected value of the scan path output terminal for each period of the clock pulse is created as the value to be output at the scan path output terminal. The expected value created by the expected value creation process 44 is outputted by the expected value output process 45.

As shown in FIG. 6, the expected value comparison means 5 inputs the simulation results outputted by the symbol propagation simulation execution means 3 in the simulation result input processing 51, and then inputs the simulation results outputted by the symbol propagation simulation execution means 3 in the next expected value input processing 52. Enter the expected value output by . In the subsequent expected value comparison process 53, the simulation results input in the simulation result input process 51 and the expected values input in the expected value input process 52 are compared, and if they match, it is guaranteed that the scan path is operating as designed. , in the case of mismatch, the mismatch path output processing 54 outputs the symbol unique to the flip-flop that is the expected value and the symbol unique to the flip-flop that is supposed to be connected to the subsequent stage of that flip-flop, that is, the scan path one clock ago. Outputs the expected value of the output terminal as a path with an invalid connection.

Next, the operation of this embodiment will be explained using the scan path shown in FIG. 7 as an example. The scan path shown in FIG. 7 includes three flip-flops A, B, and C, a scan path input terminal SIN, a scan path output terminal SOT, a scan path control terminal SFM, and a clock input terminal CLK.
It operates when the scan path control terminal SFM is set to "1".

The model information storage means 1 contains the netlist of the logic circuit having the scan path shown in FIG. 7 and the scan path connection order "SIN-A-B-" specified by the circuit designer.
C-SOT", the name of the scan path control terminal SFM that inputs the scan path control signal, and the value set to the scan path control terminal SFM to operate the scan path (
In this example, "1") and scan path control signal information consisting of the name of the clock input terminal CLK that inputs the clock pulse are stored.

When verifying the scan path, the simulation control command output means 2 performs the processes 21 to 24 shown in FIG. Enter the name of the scan path control terminal SFM, the state value (“1” in this example) to be set to the scan path control terminal SFM to operate the scan path, and the name of the clock input terminal CLK to which the clock pulse is input.

Next, the simulation control command output means 2
performs a control signal state value setting command creation process 25 to create an command to set the state value "1" to the scan path control terminal SFM and a command to set a clock pulse to the clock terminal CLK.

Thereafter, the simulation control command output means 2 performs a scan path state value setting command creation process 26 to control the flip-flops A, A, and A on the scan path.
An instruction is created to set symbols A, B, and C specific to B and C, and to set the symbol SIN specific to each scan path input terminal SIN as an initial value.

Next, the simulation control command output means 2 performs a scan-out observation command creation process 27 to create a command to observe the state value of the scan path output terminal SOT.

Thereafter, the simulation control command output means 2 performs a simulation execution command creation process 28, and creates an command to perform the simulation for a period of time during which three clock pulses, which is the number of flip-flops, are input.

Finally, the simulation control command output means 2 outputs the commands created in steps 25 to 28 to the symbol propagation simulation execution means 3 and the expected value creation means 4 (command output processing 29).

The symbol propagation simulation execution means 3 inputs the simulation model corresponding to FIG. 7 from the model information storage means 1 by performing a simulation model input process 31, and outputs a simulation control command by performing the next command input process 32. The command output by means 2 is input. After that, a simulation is executed to propagate the symbol according to the input command, and the state value of the scan path output terminal SOT observed during the simulation is output as a simulation result (symbol propagation simulation execution process 33).

The expected value creation means 4 performs a scan path wiring order request process 41 and a scan path wiring order input process 42 to obtain the scan path wiring order "SIN-A-B-C-SOT" from the model information storage means 1. Enter
By performing the command input process 43, the command output by the simulation control command output means 2 is input, and the initial values set in the scan path input terminal SIN and the flip-flops A, B, and C on the scan path are changed to symbols SIN, A. ，
B, C, and assuming that the state values of flip-flops A, B, and C on the scan path propagate to the next flip-flop every clock cycle, create the expected values shown in Figure 8, and Output.

The expected value comparison means 5 inputs the simulation results output by the symbol propagation simulation execution means 3 by performing the simulation result input processing 51, and receives the simulation results created by the expected value creation means 4 by performing the expected value input processing 52. Enter the expected value. Thereafter, expected value comparison processing 53 is performed, and if the two do not match, the expected value and the expected value one clock before are output (mismatch path output processing 54). For example, if the simulation result at the second clock is different from the expected value A in FIG. 8, the expected value A and the expected value B one clock before are output. That is, if the second clock simulation result is not the expected value A, it is considered that there is an irregularity in the path between the flip-flops A and B, so symbols A and B indicating this are output.

[0042]

[Effects of the Invention] As explained above, the present invention sets a symbol unique to each flip-flop as an initial state value for each flip-flop on a scan path, and performs a symbol propagation simulation in which the set symbol is propagated. This has the effect of verifying that the state value is reliably propagated from the flip-flop on the scan path to the scan path output terminal, and it is also possible to verify that the state value is reliably propagated from the flip-flop on the scan path to the scan path output terminal. This has the effect of allowing you to check the connection order.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a flow chart showing a processing example of a model information storage means.

FIG. 3 is a flow chart showing a processing example of a simulation control command output means.

FIG. 4 is a flowchart showing a processing example of a symbol propagation simulation execution means.

FIG. 5 is a flowchart showing an example of processing by expected value creation means.

FIG. 6 is a flowchart showing an example of processing by an expected value comparing means.

FIG. 7 is a diagram showing an example of a scan path.

FIG. 8 is a diagram showing an example of expected values.

[Explanation of symbols]

1...Model information storage means 2...Simulation control command output means 3...Symbol propagation simulation execution means 4...Expected value creation means 5...Expected value comparison means

Claims (3)

[Claims] 1. A scan path logic verification method for verifying logical connections of scan paths, comprising: a simulation model of a logic circuit including the scan path; and a scan path wiring order indicating the order of flip-flops on the scan path. , a model information storage means storing scan path control signal information defining a control signal for operating the scan path, and a model information storage means based on the scan path wiring order and scan path control signal information stored in the model information storage means. and an instruction to give each flip-flop on the scan path a symbol unique to each flip-flop as an initial state value, an instruction to observe the state value of the output terminal of the scan path, and an instruction to instruct execution of the simulation. symbol propagation simulation execution means for performing a symbol propagation simulation based on a simulation control command output means to be created, a simulation model stored in the model information storage means, and each instruction created by the simulation control command output means; Expected value creating means for creating an expected value at each time of simulation based on the scan path wiring order stored in the model information storing means; Simulation results by the symbol propagation simulation executing means and the expected value creating means By comparing the expected value created by
1. A scan path logic verification method, comprising: expected value comparison means for determining whether or not a logical connection of a scan path is incorrect. 2. The symbol propagation simulation execution means causes the flip-flop to hold the logical value when the state value taken in by the flip-flop is a logical value, and causes the flip-flop to hold the symbol when the state value is a symbol. The scan path logic verification method according to claim 1. 3. The scan path logic verification method according to claim 1, wherein the expected value comparing means outputs the expected value when the comparison does not match.