KR100767957B1 - Design Verification Method Using Mixed Emulation, Simulation, and Formal Verification - Google Patents

Abstract

The present invention relates to a design verification method for design verification of a designed multi-million-gate or more digital circuit.

In the present invention, the input / output / input / output probe is possible by adding a probe additional circuit which enables the design verification system software of the present invention to be performed on an arbitrary server computer to enable the input / output / input / output probe to the design verification target circuit. Allows you to create extended circuits in an automated manner. It also allows for automated ABV-based verification on a hardware basis, allowing automated generation of additional circuitry with inspection or monitor modules as needed. In addition, the design verification interface module (means) of the present invention comprises a hardware board and the server computer in which the extended circuit capable of input / output / input / output probe is implemented with one or more programmable elements and is mounted together with other hardware components. Designing the server computer and the at least one programmable element by performing input / output / input / output probes for the at least one programmable element on the hardware board at a specific point in time or under certain conditions while controlling the execution of the hardware board. It enables to quickly exchange performance result information about the whole circuit or partial circuit to be verified. In addition, by using the server computer and any one or more simulation computers that simulate only the entire circuit or partial circuit to be designed and verified, emulation and simulation are alternately performed one or more times in an automatic method, and the design verification target circuit is verified through design verification. It is possible to quickly eliminate one or more design errors present in the.

Description

Design Verification Method Using Mixed Emulation, Simulation, and Formal Verification

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows an example of a design verification apparatus for the design verification method of the present invention.

Fig. 2 is a diagram schematically showing an example in which an output probe additional circuit is added to a design verification target circuit.

3 is a diagram schematically showing an example of adding an input probe additional circuit to a design verification target circuit;

4 is a diagram schematically showing an example in which a tester or a monitor is built in the input probe addition circuit;

<Description of the symbols for the main parts of the drawings>

12: RFPD 20: Computer for Server

26: interface module 28: interface cable

30: Component other than one or more RFPD in which the design verification target circuit on any prototyping board is implemented.

32: Design verification system software 34: Arbitrary simulator

35: random computer

44: random prototyping board 74: multiplexer

73: Single Input Flip-Flop with Asynchronous Set / Reset and Synchronous Enable

75: dual input D flip flop 76: single input D flip flop

77: dual input flip-flop with asynchronous set and asynchronous reset

78: Single Input Flip-Flop with Asynchronous Set and Asynchronous Reset

79: Tri-state buffer

86: output probe target signal line

87: flip-flops forming a shift register of an additional circuit for the output probe

88: flip-flops forming the shift register of the additional circuit for the input probe

90: simulation circuit for design verification

92: Inspector or monitor implemented in hardware

The present invention relates to a technology for design verification of millions of gate-class digital circuits designed and implemented by emulation, simulation, and formal verification techniques. The present invention relates to a design verification method for quickly eliminating one or more design errors present in the multi-million-gate or more digital circuit.

With the recent rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuit design has grown from at least millions of gates to tens of millions of gates, and its composition has become extremely complicated. As the trend is expanding, more than 100 million gate designs are expected in the near future. However, competition in the market is getting fiercer, and therefore, a good product must be developed in a short time, and there is an increasing need for an effective method for efficiently designing and verifying a circuit designed in an automated manner in a short time.

Until now, the simulator, which is a software approach, has been mainly used to design and verify the designed digital circuit. However, the simulator has to sequentially execute the software code composed of sequential instruction sequences that model the circuit to be designed and verified on a computer. Design verification time for designs beyond millions of gates is extremely long, beyond the imagination, and physically integrated with other surrounding hardware environments to limit the entire system (called ICE, In-Circuit Emulation). . In addition, in order to perform design verification using simulation, an input pattern sequence for design verification should be generated in a design verification target circuit. However, as the size of the circuit for design verification increases, the size of the input pattern sequence increases in proportion to the exponential function, and in most cases, a large amount of time and cost must be invested.

In contrast, a hardware emulation-based design verification method using a designed circuit as a real chip is to verify the digital circuit in a situation where all components of the designed digital circuit are actually operated in parallel on the implemented chip. Design verification can be up to one million times faster than that, and the ICE environment can be physically configured and integrated with other surrounding hardware environments. In addition, in the case of performing design verification using the ICE method by integrating with other peripheral hardware environments, the process of manually generating the input pattern sequence from the surrounding hardware environment is supplied to the design verification target circuit. However, emulation has a disadvantage that it is very inconvenient to perform debugging compared to simulation, and its main cause is the visibility that can know the logic value of numerous signal lines in the design verification circuit implemented in the programmable chip or the custom semiconductor chip. This is because visibility falls far short of the simulation. In addition, if emulation using programmable chips or custom semiconductor chips is used, the execution can be performed at extremely high speed. However, if one or more design errors exist in the circuit under design verification, these errors can be corrected. In this case, it is necessary to reprogram the programmable chip or to manufacture the custom semiconductor chip again. This process requires a very long time and sometimes a high cost. In general, the design is not verified at the initial stage of design. Many design errors exist, and these design errors are usually corrected from several times to tens of times. Therefore, design verification using emulation is not desirable in such a situation.

The patent application "Rapid input / output probe device and input / output probe method using the same and a mixed emulation / simulation method based on the same" (Patent Application No. 10-2000-0034628) is a reusable field programmable device (programmable chips) Design validation for digital systems using any emulation and arbitrary simulation with custom semiconductor devices such as Devices (hereinafter referred to as "RFPD"), application specific integrated circuits (ASICs), or application specific standard products (ASSPs) It suggests how to do this effectively.

However, in addition to any emulations and simulations, as well as any other patents, not only the previously filed patents, but also any formal verification or any semi-formal verification can be used in the digital system. It does not present a way to effectively perform design verification. Formal verification or semi-formal verification enables white-box verification or gray-box verification using assertions, resulting in circuit malfunction due to design errors. It is possible to automatically detect design errors by using a checker or monitor that checks whether the assertions are satisfied or violated even if the output of the test is not delivered. Investigating whether a claim is satisfied or violated by investigating whether the claim is satisfactory or violated, the design error associated with the particular claim and the time of occurrence thereof can be determined in an automated way, which is ABV (Assertion-based). Also called Verification method. However, the disadvantage of formal verification or semi formal verification is that the verification execution time is very slow compared to the normal simulation when the verification target is large.

Accordingly, it is an object of the present invention to provide an arbitrary emulation and any simulation of any large scale digital system implemented in hardware using one or more RFPDs for ultra-scale design verification and any formal verification or any semi- By using a combination of semi-formal verification and design verification using both hardware input / output probe method and software input / output probe method in design verification, it is possible to minimize the detection and elimination of numerous design errors in the design verification target. It is to provide a design verification method that can be performed quickly with time and cost. Specifically, white-box verification or gray-box verification using assertions can be enabled in the emulation / simulation hybrid method, thereby verifying the emulation / simulation hybrid process. A checker or monitor, consisting of assertion statements, examines claims in real time to see if they are satisfactory or violated, and quickly determine when a particular claim is satisfied or violated, and when that particular claim is satisfied or violated. By providing a high visibility of the design verification target in the vicinity through the simulation to provide a design verification method that can quickly determine the design error associated with the particular claim, and when and the cause of its occurrence.

In order to achieve the above object, a design verification apparatus for a design verification method of the present invention provides a design verification system software and a design verification interface module (means). The design verification interface module (means) may be composed of an interface module 26 and an interface cable 28, or in a separate manner, a server computer and one or more computers in which the design verification system software is performed. One or more hardware boards or prototyping hardware platforms or emulation hardware platforms carrying RFPDs may be connected. The design verification system software runs on a server computer and the server computer has any simulator (e.g., an HDL simulator, a logic simulator, or a cycle-based simulator), or any other one or more computers and computers that perform the above simulator. The one or more of the computers may have any formal verification tool or semi formal verification tool as needed. The design verification interface module (means) is one or more hardware boards or prototyping hardware platforms or emulation hardware platforms equipped with server computers with design verification system software and one or more RFPDs implemented with millions of gate-class digital circuits designed. This will be referred to as an arbitrary prototyping board or an arbitrary PCB in the future, and another important function of the design verification interface module (means) is the system clock required for the input / output probe of the circuit to be verified and the system clock. Probe clock, and operation mode control signal, probe mode control signal, probe memory read / write signal, etc. are generated under the control of design verification system software and supplied to any prototyping board or PCB as needed. Circuit environment It controls any prototyping board or any PCB operation that operates in an in-circuit environment. To this end, the design verification interface module (means) may have its own FPGA or CPLD, or a microprocessor or microcontroller, or a dedicated ASIC / ASSP chip. Alternatively, the rest of the design verification interface module (means) except for the physical connection means may be implemented together in the FPGA or CPLD together with the design verification target circuit or the design verification target HDL code. 1 is a design verification system software and a design verification interface module (means) running on a server computer and one or more arbitrary computers with arbitrary simulators through the server computer and computer network (e.g. LAN, WAN, ATM, etc.). Figure 1 schematically shows an example of the design verification apparatus for the design verification method of the present invention configured. Specifically, the design verification interface module (means) 26 is mounted in a PCI slot or connected to a secondary computer bus (PCI) bus of a server computer or another secondary system bus (e.g. It is common to connect to the S-bus of a SUN workstation, etc., but if high speed is required, it can be connected to the main bus, which is the primary system bus of the server computer. If so, it can be connected via USB (Universal Serial Bus), parallel port or serial pod, which connects any server computer, any prototyping board or any PCB.

The design verification system software uses the design verification interface module (means) to provide the total number of millions of gate-class design verification circuits implemented on any prototyping board or PCB at any point or situation desired by the user during the design verification process. Alternatively, the complete state information or the partial state information of the part may be read from the prototyping board at any time or situation, or vice versa. Here, state information refers to the values of the memory elements (flip-flops or latches) of the digital circuit and the contents of the memory (RAM or ROM). Complete state information refers to the values and all the values of all the memory elements of the circuit for design verification. The partial state information refers to the value of the memory elements of the portion of the design verification target circuit and / or the contents of the portion of the memory. In addition, the memory device is different from the memory, and the memory device means flip-flop or latch, and the memory refers to all kinds of random access memory (RAH), PROM, EPROM such as SRAM, DRAM, SDRAM, Rambus DRAM, etc. In other words, logical information refers to a binary logic sequence appearing on any one or more signal lines of a digital circuit. The logic value information is different from the state information, which means that the logic value information may include not only the values of the memory elements and the contents of the memory but also output values or input values of the combined logic gates.

The design verification system software includes a probe circuit synthesizer that converts input probes or output probes or input / output probes to specific signal lines present in the design verification circuit in an automated manner, such as a probe circuit synthesizer. By adding the additional circuit to the design verification target circuit, a completed circuit (which is called an extended design verification target circuit) is generated in an automated manner. The role of the probe additional circuit included in the extended design verification target circuit is that in the case of the output probe, the circuit part formed by adding the additional circuit has a shift register structure to shift the shifting operation synchronized with the probe clock just before the shifting operation. The logic values of the registers have the logic values of the signal lines in the circuit to be output probe.In the case of the input probe, the circuit part formed by adding an additional circuit has a shift register structure to perform the shifting operation. By using a specific logic value can be displayed after the shifting operation is completed on the signal lines in the circuit that is the input probe target, in the case of input and output probes, each of the input probe and the output probe can be performed at a desired time point, When normal operation is required, the additional circuit The even to to operate in functional properties logic circuit that (logical functional behavior) anji not a variation of the circuit design verification. Alternatively, if the design verification object is dictated by a hardware oral language (hereinafter referred to as HDL) code, the HDL code that is completed by adding the HDL code representing the behavior of the probe additional circuit to the HDL code to be verified by design is completed. In the case of the output probe, the HDL part formed by adding the additional HDL code expresses the shift register behavior. The signal values of the signal line have the logic values of the signal lines of the HDL code to be the output probe target, and in the case of the input probe, the HDL code part formed by adding the additional HDL code has a shift register structure and is synchronized with the probe clock. Shifting operation and using this shifting operation, H which is the target of input probe After the shifting operation is completed on the signal lines in the HDL code, which is the target of DL probe output probe, specific logic values can be displayed.In case of input / output probe, each of the input probe and output probe can be performed at the desired time. For example, when normal operation is required, the functional logical behavior of the design verification HDL code is not modified even if an additional circuit is added.

In addition, when the signal lines to be probed are the outputs of the memory device, the role of the probe additional circuit included in the extended design verification target circuit is that in the case of the output probe, the circuit portion formed by adding the additional circuit has a shift register structure. A shifting operation synchronized with the probe clock is performed. The logic values of the shift register immediately before the shifting operation are used to determine the logic values of all or a part of the memory elements in the circuit to which the output probe is targeted. A synchronous set or reset operation, or an asynchronous set or reset operation, followed by an asynchronous set or reset operation on the signals of the HDL code being represented. This is followed by a synchronous disable operation that inputs the logical value of the signals that are the target of the input probe. In the case of input / output probes, each of the input probe and the output probe can be performed at a desired time point, and when normal operation is required, the behavior of the design-proven target HDL code is not modified even if the probe additional circuit is added. .

Examples of the specific implementation method for the additional circuit for the probe for the above-described probe is the "fast rapid input and output probe device and input and output probe method using the same and the mixed emulation / simulation method based on the same" (PCT application number: PCT / Since much of KR01 / 01092 is already mentioned in detail, this patent will only mention some cases of additional ones.

FIG. 2 is a diagram schematically showing an example of an implementation of a probe additional circuit that performs an output probe on arbitrary signal lines existing in a design verification target circuit.

FIG. 3 is a view schematically showing an example of an additional circuit for a probe that performs an input probe on an arbitrary signal line that is an input or an output of a combination circuit existing in a design verification target circuit; in this case, a memory device Since the input probe should be performed on the signal lines other than the output of the circuit, the circuit portion formed by adding the additional circuit has a shift register structure to perform the shifting operation, and the input probe data forms the shift register structure using the shifting operation. After storage in flip-flops, the select input of the multiplexer 74 is controlled so that the input probe data appears on each of the corresponding signal lines.

Additionally, the design verification target circuit includes memory such as RAM or ROM, and these memories are also provided on-chip memory (specifically, for example, distributed RAM or block RAM of Xilinx FPGA). In the case of using an embedded array block of Altera FPGA, a memory read / write additional circuit is additionally included in the IOP probe additional circuit. The memory read / write additional circuit is controlled by the design verification system software, and in the output probe mode, the output probe is read out by reading all the contents of the memory or the specific region in the design verification target circuit implemented in the RFPD in a predetermined order. It can be read through the interface module and the interface cable through the design verification system software in an automated manner.In the input probe mode, the data of the design verification system software is transferred to the RFPD input probe through the interface cable and the interface module. Through the RFPD, the write operation is performed in a predetermined order in all regions or specific regions of the writable memory in the design verification target circuit implemented in the RFPD. A specific example of the implementation of such a memory read / write additional circuit is already described in the "quick input / output probe apparatus and input / output probe method using the same and a mixed emulation / simulation method based on the same" (PCT application number: PCT / KR01 / 01092). Since it is mentioned in detail, it will be omitted in the present patent.

In the present invention, the output probe line and the input probe line may exist as separate independent unidirectional probes, or may exist as bidirectional probes in which the output probes and the input probes are combined. In addition, the probe clock used in the present invention may generate and use a clock separate from the user clocks used in the design verification target circuit from the system clock, or may use one of the user clocks (for example, the fastest clock).

The design verification system software may be configured to manually receive or automatically determine the signal phase signals and memory blocks present in the circuit to be verified, or the signal phase signals and memory blocks present in the HDL code to be verified. In order to implement the design verification circuit in one or more RFPDs mounted on any prototyping board or any PCB. Arbitrary and non-prototyping boards or arbitrary logic so that logic values appear sequentially on the output probe only for a certain period of time, and the signal lines on the input probe or the memory area to be written can have logic values applied to the input probe at specific times. Verification assignments assigned to one or more RFPDs mounted on the PCB Adding an additional circuit for the probe circuit further comprises the step of generating the extended design verification circuit. In addition, for the signal lines on the output probe and the memory area to be read, the logic values and the contents of the memory at specific time points on the signal lines on the output probe are displayed on the output probe of the corresponding RFPD using the probe additional circuit. The value shown in the line is transmitted to the server computer through the design verification interface module (means). For the signal lines on the input probe and the memory area to be written, the input probe data is generated from the state information obtained from the server computer. Through the verification interface module (means), the signal lines on the input probe of the corresponding RFPD are applied while being synchronized with the probe clock only, or synchronized with the probe clock, and the probe mode is input through the probe mode control signal line. By changing the liver appropriately Setting the status information of the design verification target circuit implemented in the RFPD to be the same as the status information obtained from the server computer by having the logical values of the wires and the contents of the memory area to be written have the logical values transmitted through the input probe line. Include.

By using the above design verification method, any prototyping board or any PCB and any simulator equipped with one or more semiconductor chips in which an extended design verification target circuit in which a probe additional circuit is added to the design verification target circuit are implemented. Using together, you can perform design verification by temporally or spatially mixing emulation and simulation. In other words, such emulation and simulation mixed verification may be performed by the design verification system software. The design verification system software may manually designate the signal signals and memory blocks present in the design verification circuit, or the signals and memory blocks present in the design verification target HDL code from the designer. A signal line on the output probe on the entire design verification circuit or part of the design verification circuit implemented in one or more RFPDs mounted on any prototyping board or any PCB. The logic values at specific time zones or at specific times in the memory area to be read are sequentially displayed on the output probe only for a certain period of time. To have logical values applied at specific times Expanded design verification circuits or extended circuits by adding probe additional circuits to all the design verification circuits or to the design verification circuits assigned to one or more RFPDs mounted on any prototyping board or any PCB. The method may further include generating a design verification target circuit part. In addition, for the signal lines on the output probe and the memory area to be read, the logic values and the contents of the memory at specific time points on the signal lines on the output probe are displayed on the output probe of the corresponding RFPD using the probe additional circuit. The value displayed on the line is transmitted to the server computer through the design verification interface model so that the simulator can calculate the current status information or the logic information of the current probe signal lines of the entire design verification circuit or the part of the design verification circuit. For the signal lines on the input probe and the memory area to be written, the input probe data is generated from the state information or logic value information obtained through the simulation on any computer, and then the interface module and the interface cable are connected. Input probe of the corresponding RFPD Apply to the target signal lines while synchronizing only with the probe clock, or by synchronizing with the probe clock and changing the probe mode between the input probe mode and the output probe mode through the probe mode control signal line. By making the logic value and the contents of the memory area to be written have the logic values transmitted through the input probe line, the state information or logic value information of the entire design verification circuit or part of the design verification circuit implemented in the RFPD is stored for a certain period of time in the simulator. And setting the same as the state information or logic value information generated through the simulation. The exchange of state information or logic value information between any one or more RFPDs mounted on any prototyping board or any PCB and any simulator can be accomplished by using a foreign language interface (FLI) or a programming language interface (PLI) provided in the simulator. This can be done at the API (Application Program Interface) level, with minimal overhead.

In addition, in the above-mentioned simulation process, the AVB method can be adopted by incorporating a tester or monitors in the design verification target circuit if necessary, and in the emulation process, when the design verification target circuit is implemented in one or more programmable devices, A tester or monitor can be implemented together in a programming device to adopt a hardware-based AVB approach. The simulation / emulation hybrid method mentioned in the future is based on the use of AVB on the simulation side or AVB on the emulation side.

As described above, in order to perform mixed verification in an automated manner between emulation and simulation by using the design verification method of the present invention, performance switching between emulation and simulation should be automatically performed. Such a method is called execution mode switching. The same execution mode switching can be done every clock, or when a certain condition is satisfied (for example, when a specific value is written twice to a specific register in the circuit). This condition is called the execution mode switching condition. The execution mode switching condition may be two or more times temporally related to the entire verification process. In such a case, when the condition is satisfied, the condition is listed in the order of the first setting from the first to the later setting. Mode switching is performed in a logic emulation is to occur in the simulation in the simulation, or illustration. To do this, it is necessary to store the execution mode switching conditions in a queue, which is called the execution mode switching condition queue, and maintains it in the form of a data structure in the design verification system software.

Through this I / O probe, it is possible to perform an emulation using an arbitrary prototyping board or an arbitrary PCB and a simulation performed by a server computer one or more times. In particular, when there is no combinatorial feedback loop in the circuit under design verification, the output probe signal lines are the output lines of all memory elements (flip-flops or latches) present in the circuit under design verification (output at this time). The values of all probed memory elements are referred to as complete state information.) Even when the output probe target signal lines are output lines of partial memory elements present in the design verification target circuit, one or more clock cycles are output from the output line values of these partial memory elements. If it is possible to determine all the values of the remaining memory devices (the values of the output probed partial memory devices at this time are called fully-capable partial state information), the logic values of the output probed signal lines are transferred to the simulator in the computer for emulation. The ion simulation can proceed continuously. If more than one combinational closed circuit is included in the design verification target circuit, each of the combinational signal lines present in the combined closed circuit that can cut the closed circuit in each combination closed circuit is also the output probe target signal line. Should be included in If the above emulation and simulation can be performed one or more times, alternately, there are numerous advantages in performing design verification using an arbitrary prototyping board or an arbitrary PCB.

First, design validation in current system on a chip (SoC) environments requires a great deal of time and money to create test benches for simulation. It is very difficult for designers to create their own test benches, which account for up to 80% of the overall design code size. In addition, it is very difficult for designers to create their own test benches in all SoC designs, considering all the many cases in which the actual designed chip is actually operated in a real environment. On the other hand, the ICE-based design verification method is capable of prototyping the design verification target circuit and integrating it with the real environment, so that not only a test bench needs to be created but also actual situations are produced by the actual operation in the real environment. As a result, it is possible to perform verification that is much more reliable than using a test bench. In order to verify the design by prototyping, the design verification circuit is implemented by one or more programmable elements (FPGA or CPLD or Boolean processor). Must be present However, in general, many design errors exist, and these design errors must be corrected at least several times to several tens of times. At the initial stage of design verification, the design verification target circuit is designed to correct the design errors for the design verification by prototyping. The chip implemented must also be modified, which is very time-consuming and expensive, which cannot be used in the early stages of design, ie even when using the lowest programmable device (eg FPGA). To re-implement the error-corrected design verification target circuit, a re-compile process of several hours to several tens of hours is necessary, which greatly increases the overall design verification time.

However, by using the design verification method proposed in this patent, it is possible to effectively solve such problems and perform design verification with minimum effort in a short time. That is, as already mentioned, emulation and simulation are performed using an extended design verification circuit or an extended design verification circuit that adds a probe additional circuit or a probe additional HDL code to a design verification circuit or a design verification target HDL code. Time and space in a systematic and automated way, when design validation is performed quickly using a mix of online and offline methods, it is not necessary to manually create a test bench from the early stage of the design. It is possible to use the results as they are, allowing for much more reliable design verification with much less time and cost. In addition, unlike other methods, the emulation method proposed in this patent uses an extended design verification target circuit with a probe additional circuit, thereby providing perfect observability of signal lines present in the design verification circuit even during emulation. It is also important to have controllability.

Now, a method of having a high degree of observation and control during emulation as described above will be described in more detail, and FIG. 4 will be used for this purpose. 4 is a view schematically showing an example of a situation in which the entire design verification target circuit is performed by emulation. As described above, not only the design verification target circuit but also an inspector or a monitor are emulated in a programmable device for emulation. It can be implemented in hardware to enable the ABV verification scheme.

In addition, similar to the "fast input / output probe device and input / output probe method using the same and a mixed emulation / simulation method based on the same" (PCT application No. PCT / KR01 / 01092), which is previously applied for the design verification method, the simulation is performed through simulation. Re-compiling RFPD for all other signal lines, as well as signal lines that can be probed through the output probe in any design verification circuit implemented in one or more RFPDs on any prototyping board or any PCB. 100% probe is possible without compile process. The omission of this recompilation process is of utmost importance in the debugging process, since the time required to compile the latest multi-million-gate RFPD requires as little as tens of minutes to hours. Therefore, one of the most important things in the debugging process for the circuit implemented in the RFPD is to enable rapid debugging by maximally suppressing the recompilation of the RFPD. When design verification is performed using the above simulation and emulation, perfect observability and controllability of signal lines existing in the design verification target circuit necessary during debugging without recompiling the RFPD is required. It is also an important advantage.

Also, during the emulation process, the probe is obtained from one or more timeframes (assuming N timeframes) for which state information is desired in the design verification target circuit, and between the N timeframes. The input sequence applied in the circuit environment also obtains N through the probe, divides the simulation session following N into N, and executes in parallel with any M (M equal or less than N) simulators in parallel to speed up the simulation. Can increase. In addition, the emulation process obtains one or more timeframes (assuming N timeframes) for which state information is desired in the design verification target circuit through the probe process, and randomly divides the formal verification session following the emulation into N. M (M is less than or equal to N) can be performed in parallel with the formal verification tools to speed up formal verification.

Other objects and advantages of the present invention in addition to the above object will be apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 schematically shows an example of a design verification apparatus for a verification method according to the present invention composed of one or more arbitrary computers having a design verification system software and a simulator running on a server computer, and a design verification interface module (means). Figure is shown.

2 is a diagram schematically showing an example in which an output probe addition circuit is added to a design verification target circuit, and FIG. 3 is a diagram schematically showing an example in which an input probe addition circuit is added to a design verification target circuit.

The extended design verification target circuit generated by adding the probe additional circuit to the design verification target circuit is implemented in one or more RFPDs on an arbitrary prototyping board or an arbitrary PCB. In the process of performing the verification, when the transition to simulation is necessary at a certain time or when a certain situation occurs, the design verification system software detects this and stops emulation and the one or more RFPDs under normal control of the design verification system software are normal. When the probe clock is applied to the RFPD after switching from mode to output probe mode, the logic on the signal lines that are probed through one or more output probes connected to the output of one flip-flop in each of the one or more shift register array structures Values are sent to the design verification interface module By the way, the input / output probe point can be statically determined before emulation and can be determined dynamically such as when a specific situation occurs during emulation. In order to determine the input / output probe point which is dependent on the situation, the external device such as a logic analyzer can be observed and the input / output probe point can be determined, or the input / output probe point detector that detects the operation state inside the RFPD ( By adding an additional detector circuit, the I / O probe status can be output and the design verification system software can detect and start the I / O probe. When the input / output probe point detector circuit is additionally added to the design verification circuit along with the probe additional circuit inside the RFPD, the automatic generation and addition of the input / output probe point detector circuit is also in charge of the design verification system software.

In the case of input probes, the design verification system software generates input probe data for one or more RFPDs on the prototyping board, then switches the operation mode to the input probe mode under the control of the design verification system software, and then the probe clock One or more input probe data transmitted from the server computer through the design verification interface model through one or more input probes logically connected to the input of one flip-flop present in each of the one or more shift register array structures applied to the RFPD. The input probe data stored in the flip-flops existing in each shift register array structure, and thus the input probe object is the output of the memory device (in the case of a latch, it is converted into an equivalent circuit using a flip-flop and a multiplexer). After applying it, For further details, see PCT Application No .: PCT / KR01 / 01092). Following a synchronous set or reset, or asynchronous set or reset operation, a synchronous disable operation allows input probes to be made on one or more RFPDs mounted on any prototyping board or any PCB. If the input probe target signal lines are an output or an input of a combination circuit, the shift register array such that each of the outputs of the flip-flops existing in the shift register array structure in which the input probe data is stored is connected to the corresponding input probe target signal lines. An arbitrary prototype that controls the selection input of the multiplexer at the output of the flip-flops in each structure. Allows input probes to be made on one or more RFPDs mounted on an etching board or any PCB.

4 is a diagram schematically illustrating an example of a situation in which an inspector or a monitor is embedded in a design verification target circuit or a design verification target HDL code, and emulation is performed by implementing the design verification target circuit and an inspector or monitor together in hardware. Enables verification using the ABV method. Specifically, the process of executing in-circuit emulation by enabling white-box verification or gray-box verification using the hardware-implemented assertion when performing in-circuit emulation. In the tester or monitor, whether the assertion satisfies or violates the design verification circuit or the design verification target HDL code operates at high speed (the design verification circuit or the design verification target HDL code and the inspector or monitor are implemented in hardware. In the process of real-time investigation to find out the point of satisfaction or violation of a particular claim, and then the design verification target circuit or design verification target HDL code collected in real time near the point of satisfaction or violation of the specific claim. When the specific assertion is satisfied through a simulation using state information and an input sequence By quickly obtaining 100% visibility into the design verification target circuit or design verification target HDL code near a point or violation point, it is possible to quickly determine the cause of the design error associated with the particular claim and the exact time of occurrence thereof. have.

As described above, an object of the design verification method according to the present invention is to perform design verification using emulation, simulation, and formal verification of a large-scale digital system implemented in hardware for ultra-scale design verification. Even if the scale exceeds the limit of simulation, the design verification method using the emulation, the simulation and the formal verification is applied to enable the design verification quickly. Specifically, it is not only possible to quickly find design errors, but also to fix these found design errors quickly.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (8)

In a design verification method using a design verification system software consisting of a design verification system software performed on any computer, at least one simulator and any prototyping board or any PCB equipped with at least one programming element connected to the arbitrary computer. , The design verification system software is a probe or additional circuit or probe for a part or whole of a design verification target circuit or a design verification target HDL code implemented in one or more programmable elements mounted on the arbitrary prototyping board or any PCB. Generate the HDL code representing the behavior of the additional circuit, and add the HDL code representing the behavior of the probe additional circuit or the probe additional circuit to the design verification target circuit or the design verification target HDL code, Input or output probes or input / output probes are enabled for one or more specific signal lines present in part or all of the HDL code subject to design verification, A design verification target circuit implemented in the one or more programmable devices or a circuit capable of input probe or output probe or input / output probe for specific signal lines present in part or all of the design verification target HDL code is provided in the one or more programmable devices. At the same time, a tester or monitor for an ABV is implemented in hardware in the at least one programmable device to enable emulation of the design verification target circuit. In the process of emulation, the design verification target using one or more simulators on one or more arbitrary computers after emulation by using one or more status information about the design verification target circuit obtained through the probe and information on input sequences for one or more execution intervals. A design verification method comprising performing a simulation of all or part of a circuit or design verification target HDL code. In a design verification method using a design verification system software consisting of a design verification system software performed on any computer, at least one simulator and any prototyping board or any PCB equipped with at least one programming element connected to the arbitrary computer. , The design verification system software is a probe for additional design or part of the design verification target circuit or part of the design verification target HDL code implemented on one or more programmable devices mounted on any prototyping board or PCB. Generating an HDL code representing the behavior of the additional circuit, and adding the HDL code representing the behavior of the probe additional circuit or the probe additional circuit to the design verification target circuit or the design verification target HDL code, Design verification target circuit or part of design verification target HDL code implemented in one or more programmable elements by enabling input probe, output probe or input / output probe with respect to one or more specific signal lines existing in part or all of the target HDL code. Or input probes or outputs for specific signal lines present throughout It is possible the needle or probe output circuit to be implemented to allow for emulation, Design using one or more simulators that are performed on one or more arbitrary computers following emulation using one or more status information about the design verification target circuit obtained through the probe in the emulation execution process and information on input sequences in one or more execution intervals. In performing the simulation of all or part of the circuit to be verified or the design verification target HDL code, the inspectors or monitors for the ABV are embedded together with the circuit or the design verification target HDL code to perform the simulation. Design verification method comprising the step. The method according to claim 1 or 2, The at least one state information and the at least one execution period input sequence for the design verification target circuit obtained by performing the emulation are the at least two state information and the at least two input sequence input information, Design verification method comprising the step of performing in parallel a simulation performed using two or more simulators performed on a computer. Design verification apparatus having design verification system software executed on any computer, one or more formal verification tools, and an interface means for connecting the arbitrary computer with any prototyping board or any PCB equipped with one or more programmable elements. In the design verification method using The design verification system software is a probe or additional circuit or probe for a part or whole of a design verification target circuit or a design verification target HDL code implemented in one or more programmable elements mounted on the arbitrary prototyping board or any PCB. Generate the HDL code representing the behavior of the additional circuit, and add the HDL code representing the behavior of the probe additional circuit or the probe additional circuit to the design verification target circuit or the design verification target HDL code, Design verification target circuit or design verification target HDL code implemented in one or more programmable devices by enabling input probes, output probes, or input / output probes on one or more specific signal lines existing in part or all of the design verification target HDL code. Input probes for specific signal lines present in part or all of A circuit capable of an output probe or an input / output probe is implemented in the at least one programmable element, and at the same time, a checker or monitor for an ABV is also implemented in hardware in the at least one programmable element to enable emulation of the circuit to be verified. and, All or all of the design verification target circuit or design verification target HDL code using the one or more formal verification tools on one or more computers, followed by emulation using one or more state information of the design verification target circuit obtained through the probe during emulation execution. Design verification method comprising the step of performing a formal verification of the part. Design verification apparatus having design verification system software executed on any computer, one or more formal verification tools, and an interface means for connecting the arbitrary computer with any prototyping board or any PCB equipped with one or more programmable elements. In the design verification method using The design verification system software is a probe for additional design or part of the design verification target circuit or part of the design verification target HDL code implemented on one or more programmable devices mounted on any prototyping board or PCB. Generating an HDL code expressing the behavior of the additional circuit, and adding the HDL code expressing the behavior of the probe additional circuit or probe additional circuit to the design verification target circuit or design verification target HDL code, A design verification target circuit or a design verification target HDL code implemented in the at least one programmable element by enabling an input probe, an output probe, or an input / output probe with respect to one or more specific signal lines existing in part or all of the verification target HDL code. Input probes or outputs for specific signal lines present in part or in whole It is possible the needle or probe output circuit to be implemented to allow for emulation, In the emulation execution process, using one or more state information on the design verification target circuit obtained through the probe, the emulation of the design verification target circuit or the design verification target HDL code using one or more formal verification tools performed on one or more arbitrary computers. In performing the formal verification of all or part of the design verification method, a checker or monitor for the ABV is included with all or part of the design verification target circuit or the design verification target HDL code to perform formal verification. The method according to claim 4 or 5, One or more state information of the design verification target circuit obtained by performing the emulation is two or more state information, and performs formal verification in parallel using two or more formal verification tools performed on two or more arbitrary computers. Design verification method that includes the process. delete delete

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