KR20040063846A - Verification Apparatus Supporting the Use of Unifying Different Verification Platforms, and the Verification Method Using the Same - Google Patents

Abstract

PURPOSE: A verification device supporting the unified use of various verification platforms and a verification method using the same are provided to increase verification speed and efficiency by heterogeneously using simulation, formal verification, simulation acceleration, hardware simulation, and prototyping on a strongly unified environment, and quickly find/debug design errors. CONSTITUTION: While performing the first verification on more than one verification platform by adding an additional code or circuit to a netlist, a verification software automatically collects the information, which is needed to perform the verification for the verification cycle time sections or the blocks existing in the netlist on the verification platform differed from the verification platform of the first verification, from the first verification process. While performing the first verification on the first verification platform, the verification software collects the minimum information and performs the verification after the first verification on the other verification platform quickly by using the collected information.

Description

Verification Apparatus Supporting the Use of Unifying Different Verification Platforms, and the Verification Method Using the Same}

The present invention relates to a technique for verifying the design of a multi-million-gate or more digital system that has been designed, and to verify the digital system of the multi-million-gate or more designed system through simulation, formal verification, simulation acceleration, hardware emulation, and prototyping. The present invention relates to a verification apparatus for increasing performance and efficiency and a verification method using the same.

With the recent rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuit design has grown from at least millions of gates to tens of millions of gates, and its composition has become extremely complicated. As the trend is expanding, more than 100 million gate designs are expected in the near future. However, competition in the market is getting fiercer, and therefore, a good product must be developed in a short time, and there is an increasing need for an effective method for efficiently designing and verifying a circuit designed in an automated manner in a short time.

In the early stages of design using the Hardware Description Language (hereinafter referred to as HDL) to design-verify the designed digital circuits, HDL simulators (such as Verilog simulators, VHDL simulators, or SystemC simulators) are software approaches. This is mainly used. In such a simulator, software code consisting of a sequential instruction sequence modeling a design verification circuit in software must be sequentially executed on a computer. Therefore, the simulation performance is reduced in proportion to the size of the design target for the design of the millions or more gates. What happens is a problem. For example, when simulating more than 10 million gates with HDL simulator, such as in System On a Chip (hereafter referred to as SOC) design, it is designed as the corresponding HDL simulator on a computer equipped with the existing fastest processor. Simulation speed is difficult to exceed 10 cycles / sec when using the register transfer level (abbreviated as RTL), and 1-2 cycles / sec when performing simulation at the gate level. It is very common that it is difficult. However, the simulation cycles required to verify the design require from millions of cycles to billions of cycles, so the total simulation time is beyond imagination. In addition, in recent years, the difficulty in creating testbenches that can detect and eliminate all design errors when verifying such complex digital system designs using simulation is increasing.

In order to reduce such a long verification time and solve the difficulty of writing a test bench, the following techniques are used. First, a hardware-based verification system (for example, a simulation accelerator, a hardware emulator, a prototyping system, etc.) is used. Or second, formal verification such as property checking or model checking or equivalence checking. However, using a hardware-based verification system is not applicable early in the design, the synthesis or compilation process takes longer than using HDL simulation, it is much more difficult to use than the HDL simulator, and Not only is the maintenance cost very high, but above all, designers and verification engineers have a higher preference for HDL simulators than these hardware based verification systems. Often not performed in a verification system, these hardware-based verification systems are used only in limited situations and in limited users. In addition, these hardware-based verification systems do not provide the same level of controllability and observability as simulators and are present in Design Under Verification (hereinafter abbreviated as DUV). If all the signal lines are probed, the performance speed is also increased by more than 200%. In addition, using the formal verification tool not only adds an equivalent inspection but also requires additional work to apply the characteristic inspection or model inspection, thereby placing a new burden on the designers. As they grow in size, there is a fatal weakness that the technique cannot be performed on a computer due to the problem of state explosion.

Another problem is that to perform verification, the verification run using the design code must occur during a certain verification cycle (for example, from 0 nanosecond simulation cycle to 10,000,000 nanosecond simulation cycle when performing verification by simulation). It is essential to verify that this designer is going as intended. What is needed in this verification process is the probing of signals or variables that exist in the design code. Through such a probe, the visibility of the design ensures the location of the errors in the design code. It is necessary to confirm and remove. However, the problem with these probes is that there are a large number of signals or variables in the design code. Among them, the design error is located before the actual execution of the verification using the design code. It is very difficult to select signals or variables that require a probe to produce and remove. Currently, one method is to select all the signals and variables present in the verification target before the execution of the simulation, the simulation acceleration, the emulation, or the prototyping, and then execute the simulation, the simulation acceleration, the emulation, or the prototyping. However, if all the signals and variables present in the verification target are in the coveted shape, the execution speed is at least 2 to 5 times higher than that of the simulation, the acceleration, the emulation, or the prototyping without specifying the coveted shape. There is a problem that increases over.

Another challenge is the efficient verification of multi-million-gate or more digital systems, which requires verification using two or more verification techniques from simulation, acceleration, emulation, prototyping, and formal verification. Even when used together, two or more levels can be found in one simple technique (eg simulation) to find and correct as many design errors as possible, and then another technique (eg formal validation) to find and correct remaining design errors. It remains at the level of using verification technology together.

Accordingly, an object of the present invention is to provide a verification apparatus and a verification method using the same to improve the performance and efficiency of verification for verification of a large scale digital system design. Specifically, the combination of simulation, formal verification, simulation acceleration, hardware emulation, and prototyping in a highly integrated environment increases the speed of verification, increases efficiency, and provides visibility for probes. It enables rapid discovery and debugging of design errors without causing performance degradation.

Figure 1 (a) schematically shows an example of the design verification apparatus according to the present invention.

1 (b) to 1 (s) schematically show still another example of the design verification apparatus according to the present invention.

FIG. 2 is a diagram illustrating a design verification apparatus according to an embodiment of the present invention, in which a first verification execution is performed in a hardware emulator, a simulation accelerator, or a prototyping system, and a verification operation after the first is performed in parallel by one or more simulators. A schematic drawing of the process.

Fig. 3 shows a first verification execution in a hardware emulator, a simulation accelerator, or a prototyping system in an example of a design verification apparatus according to the present invention, wherein the verification execution after the first step is performed in parallel with one or more model inspectors or property inspectors. Figure schematically showing the process of performing.

FIG. 4 shows a first verification execution in a hardware emulator, a simulation accelerator, or a prototyping system in an example of a design verification apparatus according to the present invention, and the verification execution after the first is performed by two or more simulators and model inspectors or characteristic inspectors. Schematic diagram showing the process of performing parallel use together.

5 is a process of performing a first verification execution in a hardware emulator, a simulation accelerator, or a prototyping system in an example of a design verification apparatus according to the present invention, and performing the verification operation after the first order by one simulator in sequence. Schematically showing.

Fig. 6 shows a first verification execution in a hardware emulator, a simulation accelerator, or a prototyping system in an example of the design verification apparatus according to the present invention, and the verification execution after the first order is performed by one model inspector or characteristic inspector. Figure schematically showing the process of performing.

FIG. 7 illustrates a method of performing a first verification in a hardware emulator, a simulation accelerator, or a prototyping system in an example of a design verification apparatus according to the present invention, and performing verification after the first in parallel with two or more FPGA boards. A schematic drawing of the process.

8 is a flow chart schematically illustrating a process of finding and correcting one or more design errors present in a design using the verification device of the present invention.

9 is a flow chart schematically showing a process of performing design verification using the verification apparatus in the present invention.

<Description of the code | symbol about the principal part of drawing>

28: system software components of the prototyping system

29: System Software Component of Simulation Accelerator

30: system software component of the hardware emulator

31: A software module that automatically adds additional code or additional circuitry to the gate-level netlist generated by design code or synthesis in the verification software and prepares for verification.

32: model inspector or property inspector 33: simulator

34: Software that enables the transfer of files or data between one or more computers during the verification run in the verification software, the first verification run, the preparation for the subsequent verification run, and the subsequent verification run. module

35: computer

36: Hardware components of the hardware emulator platform

37: Hardware Components of Simulation Accelerator Platform

38: hardware components of the prototyping system platform

39: System software component of hardware-based verification platform

40: Arbitrary FPGA board, a type of prototyping system

In order to achieve the above objects, the verification apparatus according to the present invention comprises at least one computer installed with verification software, at least one HDL simulator or at least one formal verification tool, at least one hardware emulator, at least one simulation accelerator, or at least one prototyping. It consists of a system. Alternatively, the verification apparatus according to the present invention includes verification software, one or more computers with one or more HDL simulators installed, one or more computers with one or more formal verification tools installed, one or more hardware emulators, one or more simulation accelerators, or one or more prototypes. It consists of a system. The verification software of the present invention is executed on a computer, and if there are two or more computers in the design verification apparatus, these two or more computers are connected by a network to enable the movement of files between the computers.

The verification apparatus and verification method proposed in the present invention can be used not only for functional verification for verifying the design code itself, but also for gate-level verification using a gate-level netlist by synthesizing the design code. Alternatively, it may be used in timing verification in which placement and routing and extracted timing information are back-annotated to a gate-level netlist. However, in the future, the functional verification for verifying the design code itself will be described. The same method can be applied to the gate level verification or the timing verification, and thus the detailed description will be omitted.

The verification software reads design code written using HDL (eg Verilog, VHDL, System Verilog, System C, etc.) and adds additional code to it. The added code enables an automated method to perform the process of verifying the design code by performing one or more combinations of other verification techniques such as simulation acceleration, hardware emulation, prototyping, simulation, or formal verification. In addition, the verification software prepares for other verification executions (eg, compiling, loading, etc.) and controls overall verification execution. The process performed by mixing the other verification methods more than once means that the verification results obtained by performing one verification method (for example, simulation) are different from other verification methods (for example, hardware), unlike existing verification methods that independently use other verification methods. Emulation). Specifically, to perform verification, a verification run using design code on a specific verification platform (e.g. HDL simulator) must occur during a certain verification cycle (for example, from 0 nanosecond simulation cycle to 10,000,000 nanosecond simulation cycle when performing verification by simulation). In this process, the design code or other RTL / gate-level netlist / function equivalent code is read and compiled to perform the design verification, such as the verification platform (simulator, simulation accelerator, hardware emulator, prototyping system, or formal verification tool). Software or hardware system) to ensure that the execution of the design code proceeds as intended by the designer. In the case of a hardware-assisted verification system, such as a simulation accelerator, a hardware emulator, or a prototyping system, the verification platform is composed of hardware components and system software components. What is needed in this verification process is the probing of signals or variables present in the design code. The visibility of the design through these probes is essential to the identification and removal of errors in the design code. However, the problem with these probes is that there are a large number of signals or variables in the design code. Among them, the design error is located before the actual execution of the verification using the design code. To eliminate this, it is very difficult to select signals or variables that require a probe. Currently, one method is to select all the signals and variables present in the verification target before the execution of the simulation, the simulation acceleration, the emulation, or the prototyping, and then execute the simulation, the simulation acceleration, the emulation, or the prototyping. However, if all the signals and variables present in the verification target are in the coveted bed, the execution speed is at least 2 to 5 times higher than that of the simulation, the acceleration, the emulation, or the prototyping without specifying the coveted bed. There is a problem that increases over.

Unlike existing verification runs for design verification using only one verification platform repeatedly, the verification runs in the present invention are alternately made using two or more different verification platforms. To this end, the verification apparatus proposed by the present invention is verification software that performs additional verification on a specific verification platform by adding additional code to the design code through an automated method, and then performs verification execution on another verification platform after the first simulation. It is possible to automatically collect the minimum information necessary for the verification executions to be limited to specific verification cycle sections or specific blocks existing in the design code in the first verification execution process. The minimum information is collected while performing the first verification run, and it is possible to use this collected information to quickly perform a post-primary verification run on another verification platform. In order to quickly perform the post-primary verification run, if necessary, the post-primary verification run may be performed using one or more verification platforms using information collected while performing the first verification run using the primary verification platform. This can be done in parallel, using a hardware-based verification platform (such as an FPGA board), or by limiting only certain blocks that exist in the verification code to enable rapid verification.

Next, specific examples of the verification apparatus and the verification methods according to the present invention will be described with reference to examples.

As a first example, the verification device proposed by the present invention comprises verification software, one or more hardware emulators, one or more computers, and one or more simulators installed on the one or more computers, wherein the one or more hardware emulators and one or more computers are computers. It is connected by network. In the verification apparatus, the verification apparatus performs the first verification execution using the hardware emulator, performs the first verification execution using the hardware emulator, and performs the verification verification after the first one or more simulators. The advantage of this method is that it can increase the utilization rate of the very expensive hardware emulator, which is more than billions, and also speed up the verification. First of all, it is possible to increase the utilization rate of the hardware emulator. In the case of performing the design verification using only the hardware emulator, all signals and variables present in the design code are selected as the coveter to detect and correct design errors. By specifying 100% visibility into the design code and proceeding with hardware emulation, the speed of emulation is about two times or more slower than otherwise. Therefore, instead of the conventional method, the method of the present invention performs the first verification by using a hardware emulator and probes only the minimum signals and variables necessary for the verification after the first step in the verification execution process. Minimize the slowdown of emulation and at the same time, enable the hardware emulator to be used for other verification of the same design or verification of another design as soon as the first verification run is completed, thereby increasing the utilization of expensive hardware emulators. The verification run after the first phase is performed using one or more simulators. The following methods are used as methods to speed up the verification execution in the case where the verification execution after the first step is performed through the simulation using one or more simulators. One method can be used to run two or more simulations in parallel using two or more simulators, and, if necessary, integrate the results of these two or more simulations to use as a result of the entire verification run. To do this, the hardware emulator collects the minimum information necessary to execute two or more simulation runs in parallel after the first step in the first verification run. There can be two minimum pieces of information needed to run these simulations in parallel. One is to store all the information present in the DUV at the same time as the first verification run (emulation run) at a certain interval (e.g. once every 50,000 nanoseconds for verification time) or at one or more points of time desired by the user. Information obtained by performing a probe on the entire interval of the verification execution for the input / output and storing the same. Here, the status information of the DUV refers to the values of all memory devices (such as flip-flops, latches, RAMs, ROMs, and logic gates with combinational feedback) present in the DUV at any verification execution time. Point. If a large amount of memory (such as SDRAM or DDR-RAM) is present in a very complex system such as an SOC, it is possible to select the design target as DUV except for such a memory. In this case, the signal lines applied to the remaining design targets in the memory excluded from the verification target will also be input or input / output of the DUV, and thus, these signal lines should be selected as the targets for performing the probe for the entire verification execution region. (This information is referred to as time parallelizable information and will be used later). Storing the state information of the DUV at any point in the verification run is mostly performed by the hardware emulators currently in use (eg Cadence's Palladium or Cobalt, Mentor's Celaro or V-Station, Axis' Extreme-II, etc.). Any signal line that exists can be probed without problems. Also, probing and storing all the inputs and inputs and outputs of the DUV over the entire verification run can be done using the large amount of memory present in the hardware emulators or the main memory present in the computer used in conjunction with the hardware emulator platform. Main memory and hard disk are available. Using the state information has a very important advantage that it is not necessary to start the verification run after the first one from the start of the first verification run (hereinafter referred to as "0 verification cycle time"). The other is information obtained by performing a probe on the entire verification execution interval for all inputs and inputs and outputs present in each of the two or more blocks present in the DUV during the first verification execution (emulation execution). (This information is called spatial parallelism possible information and will be used in the future). In addition, probing and storing all inputs and inputs and outputs in each of the two or more blocks present in the DUV over the entire pre-validation interval can be performed using the large amount of memory present in the hardware emulators or connected to the hardware emulator platform. You can use the main memory in the computer you are using, or you can use the main memory and hard disk.

The time parallelizable information can be divided into a first verification execution interval (0, Τ ) into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ ). Each of these sections can be independently performed in parallel in each of the two or more simulators in the first and subsequent simulation runs. The spatially parallelizable information enables the entire DUV to be divided into two or more blocks Β ₁ , Β ₂ , ... Β _n , and these blocks are each independently parallel to each other in two or more simulators in the post-first simulation run. It is possible to be performed with. In addition, the temporal parallelism and the spatial parallelism information are collected at the same time in the verification execution through the first emulation, and then (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ) using two or more simulators in the first and subsequent simulations. , ... ( Τ _n-1 , Τ ) and Β ₁ , Β ₂ , ... Β _{n can} all be performed in parallel.

In a second example, the verification device proposed by the present invention comprises verification software, one or more simulation accelerators, one or more computers, and one or more simulators installed on the one or more computers, wherein the one or more simulation accelerators and one or more computers are computers. It is connected by network. In the verification apparatus, the verification verification is performed using the first verification execution platform as a simulation accelerator, and the verification is performed after the first verification using one or more simulators. The advantage of this method is that it can not only increase the utilization rate of simulation accelerator which is very expensive, but more than hundreds of millions of dollars, and also speed up the execution of verification. First of all, it is possible to increase the utilization rate of the simulation accelerator. In the case of performing the design verification with the simulation accelerator only, all signals and variables existing in the design code are selected as a tampon to detect and correct design errors. In this way, if the design code is to have 100% visibility and simulation acceleration is performed, the execution speed of the simulation acceleration is about twice or more than that of the other cases. Therefore, instead of the conventional method, the method of the present invention performs the first verification run using a simulation accelerator, and probes only the minimum signals and variables necessary for the verification run after the first probe in the verification execution process. Simultaneously, it is possible to increase the utilization rate of expensive simulation accelerators by minimizing the reduction in the execution speed of the simulation acceleration and enabling the simulation accelerator to be used for other verification of the same design or verification of another design as soon as the first verification execution is completed. do. The verification run after the first phase is performed using one or more simulators. The following methods are used as methods to speed up the verification execution in the case where the verification execution after the first step is performed through the simulation using one or more simulators.

One method can be used to run two or more simulations in parallel using two or more simulators, and, if necessary, integrate the results of these two or more simulations to use as a result of the entire verification run. For this purpose, the simulation accelerator is used to perform the minimum information necessary to perform two or more simulation runs in parallel after the first step in the first verification run. There can be two minimum pieces of information needed to run these simulations in parallel. One is that all inputs present in the DUV at the same time, while storing the state information present in the DUV at regular intervals (e.g. once every 50,000 nanoseconds for verification time) or at the time of the user's desired 1st verification run (simulation acceleration run). The time parallelism information obtained by performing a probe on the entire interval of the verification execution with respect to the input / output and the input / output. If there is a large amount of memory (such as SDRAM or DDR-RAM) in a very complex system such as an SOC, it is possible to select the design target as DUV except for such memory. In this case, the signal lines applied to the remaining design targets from the memory excluded from the verification target will also be input or input / output of the DUV, and thus, these signal lines should be selected as a target for performing the probe for the entire section of the verification execution. do. Storing the state information of the DUV at any point in the verification run is mostly performed inside the DUV, such as the NSX or ARES of Mentor, Excite-II of Axis, Hammer of Tharas, V400 of Pittsburgh Simulation, etc. Any signal line present in the probe can be probed without any problem. Also, probing and storing all the inputs and inputs and outputs of the DUV over the entire verification run can be done using the large amount of memory present in the simulation accelerators, or the main memory present in the computer used in conjunction with the simulation accelerator platform. Main memory and hard disk are available. The other is a space obtained by performing a probe for the entire verification execution interval for all inputs and inputs and outputs present in each of the two or more blocks present in the DUV during the first verification execution (simulation acceleration execution). Parallel information. Probing and storing all inputs and inputs and outputs in each of the two or more blocks present in the DUV over the entire period of the verification run utilizes a large amount of memory present in the simulation accelerators or is connected to the simulation accelerator platform. You can use the main memory that exists on your computer, or you can use the main memory and hard disk.

The time parallelizable information can be divided into a first verification execution interval (0, Τ ) into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ ). Each of these sections can be independently performed in parallel in each of the two or more simulators in the first and subsequent simulation runs. The spatially parallelizable information enables the entire DUV to be divided into two or more blocks Β ₁ , Β ₂ , ... Β _n , and these blocks are each independently parallel to each other in two or more simulators in the post-first simulation run. It is possible to be performed with. In addition, at the time of verification execution through the first simulation acceleration, temporal parallelism information and spatial parallelism information can be collected at the same time, and two or more simulators can be used in the post-first simulation to use (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ ) and Β ₁ , Β ₂ , ... Β _{n can} all be performed in parallel.

As a third example, the verification device proposed by the present invention comprises verification software, one or more prototyping systems, one or more computers, and one or more simulators installed on the one or more computers, and the one or more prototyping systems and one or more computers. Is connected to a computer network. In the verification device, the verification is performed using the primary verification execution platform as a prototyping system, and the verification is performed using the at least one simulator. The advantage of such a method is that not only can the utilization of the prototyping system be increased, but also the speed of verification can be increased. First of all, it is possible to increase the utilization rate of the prototyping system. In the case of performing the design verification using the prototyping system alone, all signals and variables in the design code are selected on the tamper to detect and correct design errors. . In this way, if the design code is to have 100% visibility and the simulation acceleration is performed, the execution speed of the prototyping system is about twice or more than that of the case where it is not. In the case of a prototyping system, if you want to get visibility with probes using the read-back capability of Xilinx FPGAs, the execution speed will be more than 100,000 times.) Therefore, instead of the conventional method, the method of the present invention uses the prototyping system to perform the first probe and probe only the minimum signals and variables necessary for the first and second verifications in the verification execution process. Increase the utilization of the prototyping system by minimizing the slowing down of the prototyping system, while simultaneously allowing the prototyping system to be used for other verifications of the same design or verification of another design as soon as the first verification run is completed. To be able. The verification run after the first phase is performed using one or more simulators. The following methods are used as methods to speed up the verification execution in the case where the verification execution after the first step is performed through the simulation using one or more simulators. One method can be used to run two or more simulations in parallel using two or more simulators and, if necessary, integrate the results of these two or more simulations into the results of a full verification run. To this end, the prototyping system is used to collect the minimum information necessary to perform two or more simulation runs in parallel after the first step in the first verification run. There can be two minimum pieces of information needed to run these simulations in parallel. One is to execute the first verification run (prototyping system execution) and save all the state information present in the DUV at a certain interval (for example, once every 50,000 nanoseconds for verification time) or at one or more points of time desired by the user. Time parallelism information obtained by performing a probe on the entire verification execution section for input and input and output. If there is a large amount of memory (such as SDRAM or DDR-RAM) in a very complex system such as an SOC, it is possible to select the design target as DUV except for such memory. In this case, the signal lines applied to the remaining design targets from the memory excluded from the verification target will also be input or input / output of the DUV, and thus, these signal lines should be selected as the targets for performing the probe for the entire verification execution section. do. Storing DUV's state information at any point in the verification run is not only built by prototyping systems (such as Aptix's System Explorer or Pathfinder IP Validation Station, but also by designers or verification engineers). Any FPGA-based prototyping board can be called a prototyping system. Most of the time, it is possible to probe any signal line inside the DUV without problems (for example, using the FPGA read-back technology). Or the technique proposed in US Pat. No. 6,701,491). Probe and store all the inputs and inputs and outputs of the DUV over the entire verification run using the large amount of memory present in the prototyping systems or the main memory present in the computer used in conjunction with the platform of the prototyping system. You can use either main memory or hard disk. The other is obtained by performing a probe on the entire verification execution interval for all inputs and inputs and outputs present in each of the two or more blocks present in the DUV during the first verification execution (prototyping system execution). Space parallelizable information. Probing and storing all inputs and inputs and outputs in each of the two or more blocks present in the DUV over the entire verification run utilizes the large amount of memory present in the prototyping systems or connects to the platform of the prototyping system. So, you can use the main memory in the computer that is used together, or use the main memory and hard disk.

The temporal parallelism information is such that the first verification execution interval (0, Τ ) can be divided into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ ). Each of these sections can be independently performed in parallel in each of the two or more simulators in the first and subsequent simulation runs. The spatially parallelizable information enables the entire DUV to be divided into two or more blocks Β ₁ , Β ₂ , ... Β _n , and these blocks are each independently parallel to each other in two or more simulators in the post-first simulation run. It is possible to be performed with. In addition, at the time of verification execution by performing the first prototyping system, time parallel and spatial parallel information can be collected at the same time, and two or more simulators can be used in the post-first simulation to use (0, Τ ₁ ), ( Τ ₁ , It is also possible to perform parallel operations on Τ ₂ ), ... ( Τ _n-1 , Τ ) and Β ₁ , Β ₂ , ... Β _n .

In these three cases, it is advantageous to perform the first-order simulations in parallel with two or more simulators, but if there is one simulator available, the two or more simulations are performed sequentially instead of in parallel. It is also possible. In this sequential process, if time parallelizable information consists of (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ ), the ( Τ _{n -1} , Τ ) through ( Τ _n-1 , Τ _n-2 ) ... ( Τ ₁ , Τ ₂ ), and the leading (0, Τ ₁ ), and so on. Once the location and cause are known, it is possible to omit subsequent simulations.

As a fourth example, the verification apparatus proposed by the present invention comprises verification software, at least one hardware emulator, at least one computer, and at least one formal verification tool (model inspector or characteristic inspector) installed in the at least one computer. The hardware emulator and the one or more computers are connected by a computer network. In the verification apparatus, the verification operation is performed using the hardware emulator using the primary verification execution platform as the hardware emulator, and the verification operation after the primary is performed using one or more formal verification tools. The advantage of this method is that it can increase the utilization rate of the very expensive hardware emulator, which is more than billions, and also speed up the verification. First of all, it is possible to increase the utilization rate of the hardware emulator. In the case of performing the design verification using only the hardware emulator, all signals and variables present in the design code are selected as the coveter to detect and correct design errors. By specifying 100% visibility into the design code and proceeding with hardware emulation, the speed of emulation is about two times or more slower than otherwise. Therefore, instead of the conventional method, the method of the present invention performs the first verification by using a hardware emulator and probes only the minimum signals and variables necessary for the verification after the first step in the verification execution process. Minimizing the slowdown of emulation, the hardware emulator can be used for other verifications of the same design or verification of another design as soon as the first verification run is completed, thereby increasing the utilization of expensive hardware emulators. Post-primary verification runs are conducted using one or more formal verification tools. The following methods can be used to speed up the verification execution in the case where the verification execution after the first step is performed through the model inspection or the characteristic inspection process using one or more formal verification tools. One method is to use two or more formal verification tools to perform two or more model checks or feature checks in parallel, and, if necessary, integrate the results of these two or more model checks or feature checks as a result of the entire verification run. It is available. To do this, the hardware emulator collects the minimum information necessary to perform two or more formal verification executions in parallel after the first verification process in the first verification execution. The minimum information required to perform this simulation run in parallel is one or more state information present in the DUV. This is time parallelizable information obtained by storing the state information present in the DUV at a predetermined interval (for example, once every 50,000 nanoseconds for verification time) in the first verification execution (emulation execution), or at one or more times desired by the user.

The time parallelizable information is obtained by dividing the _first verification execution interval (0, Τ _n ) into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ _n ) Or use all of the states S ₀ , S ₁ , S ₂ , ... S _n-1 , S _n at each of the time points 0, Τ ₁ , Τ ₂ , ... Τ _n-1 , Τ _n It is possible to perform a model test or a characteristic test by using specific states among them, in parallel, by setting the initial state to one of each of two or more formal verification tools. In addition, when the DUV is configured by dividing one or more blocks, such as Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , the specific state S _i of the DUV at the specific verification point is divided into these blocks S _i1 , S _i2 , ... S _in which one or more block states of S _in are reconfigured, and each of these block states is set to the initial state, one for each of the two or more formal verification tools, and then performed in parallel for each block. It is possible.

As a fifth example, the verification apparatus proposed by the present invention comprises verification software, at least one simulation accelerator, at least one computer, and at least one formal verification tool (model inspector or characteristic inspector) installed in the at least one computer. The simulation accelerator and one or more computers are connected by a computer network. In the verification apparatus as described above, the first verification execution platform is used as the simulation accelerator, and the first verification execution is performed using the simulation accelerator, and the verification execution after the first stage is performed using one or more formal verification tools. The advantage of this method is that it can not only increase the utilization rate of simulation accelerator which is very expensive, but more than hundreds of millions of dollars, and also speed up the execution of verification. First of all, it is possible to increase the utilization rate of the simulation accelerator. In the case of performing the design verification with the simulation accelerator only, all signals and variables existing in the design code are selected as a tampon to detect and correct design errors. In this way, if the design code is to have 100% visibility and simulation acceleration is performed, the execution speed of the simulation acceleration is about twice or more than that of the other cases. Therefore, instead of the conventional method, the method of the present invention performs the first verification run using a simulation accelerator, and probes only the minimum signals and variables necessary for the verification run after the first probe in the verification execution process. Simultaneously, it is possible to increase the utilization rate of expensive simulation accelerators by minimizing the reduction in the execution speed of the simulation acceleration and enabling the simulation accelerator to be used for other verification of the same design or verification of another design as soon as the first verification execution is completed. do. Post-primary verification runs are conducted using one or more formal verification tools. The following methods can be used to speed up the verification execution in the case where the verification execution after the first step is performed through the model inspection or the characteristic inspection process using one or more formal verification tools. One method is to use two or more formal verification tools to perform two or more model checks or feature checks in parallel, and, if necessary, integrate the results of these two or more model checks or feature checks as a result of the entire verification run. It is available. For this purpose, the simulation accelerator is used to collect the minimum information necessary to perform two or more formal verifications in parallel after the first step in the first verification run. The minimum information required to perform this simulation run in parallel is one or more state information present in the DUV. This is time parallelizable information obtained by storing state information present in the DUV at a predetermined interval (for example, once every 50,000 nanoseconds for verification time) or at a time desired by the user during the first verification execution (simulation acceleration execution).

Time parallelizable information is obtained by dividing the _first verification execution interval (0, Τ _n ) into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ _n ) Or use all of the states S ₀ , S ₁ , S ₂ , ... S _n-1 , S _n at each of the time points 0, Τ ₁ , Τ ₂ , ... Τ _n-1 , Τ _n Among them, it is possible to perform the model test or the property test by using specific states selectively, one by each of two or more formal verification tools, and set them to the initial state in parallel. In addition, when the DUV is configured by dividing one or more blocks, such as Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , the specific state S _i of the DUV at the specific verification point is divided into these blocks S _i1 , S _i2 , ... S _in which one or more block states of S _in are reconfigured, and each of these block states is set to the initial state, one for each of the two or more formal verification tools, and then performed in parallel for each block. It is possible.

As a sixth example, the verification apparatus proposed by the present invention comprises verification software, one or more prototyping systems, one or more computers, and one or more formal verification tools (model inspector or characteristic inspector) installed in the one or more computers. One or more prototyping systems and one or more computers are connected by a computer network. In the verification apparatus, the first verification execution platform is used as the prototyping system, and the first verification execution is performed by using the prototyping system, and the subsequent verification execution is performed by using one or more formal verification tools. do. The advantage of such a method is that not only can the utilization of the prototyping system be increased, but also the speed of verification can be increased. First of all, it is possible to increase the utilization rate of the prototyping system. In the case of performing the design verification using the prototyping system alone, all signals and variables in the design code are selected on the tamper to detect and correct design errors. . In this way, if the design code is to have 100% visibility and the prototyping system is executed, the execution speed of the prototyping is about 2 times or more compared to the case where it is not. Therefore, instead of such a conventional method, the method of the present invention performs the first verification by using a prototyping system, and probes only the minimum signals and variables necessary for the verification after the first step in the verification execution process. Increase the utilization of the prototyping system by minimizing the performance degradation of the prototyping system and by allowing the prototyping system to be used for other verifications or verification of the same design as soon as the first verification run is completed. To be able. Post-primary verification runs are conducted using one or more formal verification tools. The following methods can be used to speed up the verification execution in the case where the verification execution after the first step is performed through the model inspection or the characteristic inspection process using one or more formal verification tools. One method is to use two or more formal verification tools to perform two or more model checks or feature checks in parallel, and if necessary, integrate the results of these two or more model checks or feature checks as a result of the entire verification run. It is available. To this end, the prototyping system is used to collect the minimum information necessary to perform two or more formal verification runs in parallel after the first verification process. The minimum information required to perform this simulation run in parallel is one or more state information present in the DUV. This is time parallelizable information obtained by storing state information present in the DUV at a predetermined interval (for example, once every 50,000 nanoseconds for verification time) or at a time desired by the user during the first verification execution (prototyping system execution).

The time parallelizable information is obtained by dividing the _first verification execution interval (0, Τ _n ) into two or more intervals (0, T ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 , Τ _n ) Or use all of the states S ₀ , S ₁ , S ₂ , ... S _n-1 , S _n at each of the time points 0, Τ ₁ , Τ ₂ , ... Τ _n-1 , Τ _n It is possible to perform a model test or a characteristic test by using specific states among them, in parallel, by setting the initial state to one of each of two or more formal verification tools. In addition, when the DUV is configured by dividing one or more blocks, such as Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , the specific state S _i of the DUV at the specific verification point is divided into these blocks S _i1 , S _i2 ... to reconfigure one or more of s in the block state _in the model to test or test to the characteristics of each block of the state thereof to the initial state in one of two or more formal verification tools can be respectively to be performed in parallel for each block Do.

In these three other cases, it is advantageous to perform a post-primary model test or feature test in parallel with two or more formal verification tools, but if there is only one formal verification tool available, two or more model tests or features It is also possible to perform the tests sequentially instead of performing the tests in parallel. In this sequential process, if time parallelizable information consists of (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ), the ( Τ _{n- 1} , Τ ) through ( Τ _n-1 , Τ _n-2 ) ... ( Τ ₁ , Τ ₂ ) and the leading (0, Τ ₁ ), etc. It is possible to omit the formal verification process after this and the cause is identified.

As a seventh example, the verification device proposed by the present invention comprises verification software, one or more hardware emulators, one or more computers, and one or more FPGA boards installed on the one or more computers. It is connected by computer network. In the verification apparatus, the verification operation is performed using the hardware emulator using the primary verification execution platform as the hardware emulator, and the verification operation after the first verification is performed using one or more FPGA boards. The advantage of this method is that it can increase the utilization rate of the very expensive hardware emulator, which is more than billions, and also speed up the verification. First of all, it is possible to increase the utilization rate of the hardware emulator. In the case of performing the design verification using only the hardware emulator, all signals and variables present in the design code are selected as the coveter to detect and correct design errors. By specifying 100% visibility into the design code and proceeding with hardware emulation, the speed of emulation is about two times or more slower than otherwise. Therefore, instead of the conventional method, the method of the present invention performs the first verification by using a hardware emulator and probes only the minimum signals and variables necessary for the verification after the first step by the probe. At the same time minimizing the slowdown of the emulation, the hardware emulator can be used for other verification of the same design or verification of another design as soon as the first verification run is completed, thereby increasing the utilization of expensive hardware emulators. Post-primary verification runs are performed using one or more FPGA boards. The following methods can be used to speed up the verification run in the case of performing the post-primary verification using more than one FPGA board. One possible method is to use two or more FPGA boards to run two or more verification intervals in parallel and, if necessary, integrate the results of these two or more FPGA boards as a result of the entire verification run. To do this, the hardware emulator collects the minimum information needed to perform parallel execution of two or more FPGA boards after the first step in the first verification run. There can be two types of minimum information needed to perform verification using these FPGA boards in parallel. One is to store all the information present in the DUV at the same time as the first verification run (emulation run) at a certain interval (e.g. once every 50,000 nanoseconds for verification time) or at one or more points of time desired by the user. Time parallelism information obtained by performing a probe on the entire interval of the verification execution for the input / output and storing the same. The other is the spatial parallelism obtained by performing a probe for the entire verification execution interval for all inputs and inputs and outputs present in each of the two or more blocks present in the DUV during the first verification execution (emulation execution). Possible information.

The time parallelizable information allows the first verification execution interval (0, Τ ) to be divided into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ) Each of these intervals can be independently performed in parallel on each of two or more FPGA boards in execution through the first and subsequent FPGA boards. The spatially parallelizable information allows the entire DUV to be divided into two or more blocks Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , and these blocks are each independently paralleled on each of the two or more FPGA boards in the post-first verification run. To be performed as In addition, the temporal parallelism and the spatial parallelism information are collected at the same time during the verification run through the first emulation, and two (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ) and Ｂ ₁ , Ｂ ₂ , ... Ｂ _n are all possible in parallel.

As an eighth example, the verification device proposed by the present invention comprises verification software, one or more simulation accelerators, one or more computers, and one or more FPGA boards installed in the one or more computers. It is connected by computer network. In the verification apparatus, verification is performed using a simulation accelerator using the primary verification execution platform as a simulation accelerator, and the verification after the first phase is performed using one or more FPGA boards. The advantage of this method is that it can not only increase the utilization rate of simulation accelerator which is very expensive, but more than hundreds of millions of dollars, and also speed up the execution of verification. First of all, it is possible to increase the utilization rate of the simulation accelerator. In the case of performing the design verification with the simulation accelerator only, all signals and variables existing in the design code are selected as a tampon to detect and correct design errors. In this way, if the design code is designed to have 100% visibility and the simulation acceleration is performed, the execution speed of the simulation acceleration is about twice or more than that of the case where it is not. Therefore, instead of the conventional method, the method of the present invention performs the first verification run using a simulation accelerator, and probes only the minimum signals and variables necessary for the verification run after the first probe in the verification execution process. Simultaneously, it is possible to increase the utilization rate of expensive simulation accelerators by minimizing the reduction in the execution speed of the simulation acceleration and enabling the simulation accelerator to be used for other verification of the same design or verification of another design as soon as the first verification execution is completed. do. Post-primary verification runs are performed using one or more FPGA boards. The following methods can be used to speed up the verification run in the case of performing the post-primary verification using more than one FPGA board. One possible method is to use two or more FPGA boards to run two or more verification intervals in parallel and, if necessary, integrate the results of these two or more FPGA boards as a result of the entire verification run. To do this, the simulation accelerator is used to collect the minimum amount of information needed to perform parallel execution of two or more FPGA boards after the first step in the first verification run. There can be two types of minimum information needed to perform verification using these FPGA boards in parallel. One is that all inputs present in the DUV at the same time, while storing the state information present in the DUV at regular intervals (e.g. once every 50,000 nanoseconds for verification time) or at the time of the user's desired 1st verification run (simulation acceleration run). The time parallelism information obtained by performing a probe on the entire interval of the verification execution with respect to the input / output and the input / output. The other is a space obtained by performing a probe for the entire verification execution interval for all inputs and inputs and outputs present in each of the two or more blocks present in the DUV during the first verification execution (simulation acceleration execution). Parallel information.

The time parallelizable information allows the first verification execution interval (0, Τ ) to be divided into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ) Each of these intervals can be independently performed in parallel on each of two or more FPGA boards in execution through the first and subsequent FPGA boards. The spatially parallelizable information allows the entire DUV to be divided into two or more blocks Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , and these blocks are each independently paralleled on each of the two or more FPGA boards in the post-first verification run. To be performed as In addition, in the process of verifying execution through the 1st simulation acceleration execution, the temporal parallelism information and the spatial parallelism information are simultaneously collected and two or more FPGA boards are used in the post-primary verification execution (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ) and Ｂ ₁ , Ｂ ₂ , ... Ｂ _n are all possible in parallel.

As a ninth example, the verification device proposed by the present invention comprises verification software, one or more prototyping systems, one or more computers, and one or more FPGA boards installed in the one or more computers. Computers are connected by a computer network. To perform verification in such a verification device, the first verification execution platform is used as the prototyping system, and the first verification execution is performed using the prototyping system, and the first and subsequent verification execution is performed using one or more FPGA boards. . The advantage of such a method is that not only can the utilization of the prototyping system be increased, but also the speed of verification can be increased. First of all, it is possible to increase the utilization rate of the prototyping system. In the case of performing the design verification using the prototyping system alone, all signals and variables in the design code are selected on the tamper to detect and correct design errors. . By specifying 100% visibility of the design code and executing the prototyping system, the execution speed of the prototyping system is about 2 times or more slower than the case where it is not. Therefore, instead of the conventional method, the method of the present invention uses the prototyping system to perform the first probe and probe only the minimum signals and variables necessary for the first and second verifications in the verification execution process. Increase the utilization of the prototyping system by minimizing the performance degradation of the prototyping system, and simultaneously allowing the prototyping system to be used for other verifications or verification of the same design as soon as the first verification run is completed. To be able. Post-primary verification runs are performed using one or more FPGA boards. The following methods can be used to speed up the verification run in the case of performing the post-primary verification using more than one FPGA board. One possible method is to use two or more FPGA boards to run two or more verification intervals in parallel and, if necessary, integrate the results of these two or more FPGA boards as a result of the entire verification run. For this purpose, the prototyping system is used to collect the minimum amount of information needed to perform parallel execution of two or more FPGA boards after the first step in the first verification run. There can be two types of minimum information needed to perform verification using these FPGA boards in parallel. One is to execute the first verification run (prototyping system execution) and save all the state information that exists in the DUV at the same time (for example, once every 50,000 nanoseconds for verification time) or at the one or more points of time desired by the user. Time parallelism information obtained by performing a probe on the entire verification execution section for input and input and output. The other is obtained by performing a probe on the entire interval of the verification execution for all the inputs and inputs and outputs present in each of the two or more blocks present in the DUV during the first verification execution (prototyping system execution). Space parallelizable information.

The time parallelizable information allows the first verification execution interval (0, Τ ) to be divided into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ) Each of these intervals can be independently performed in parallel on each of two or more FPGA boards in execution through the first and subsequent FPGA boards. The spatially parallelizable information allows the entire DUV to be divided into two or more blocks Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , and these blocks are each independently paralleled on each of the two or more FPGA boards in the post-first verification run. To be performed as In addition, during the verification run through the execution of the primary prototyping system, the temporal parallelism and the spatial parallelism information are simultaneously collected and two or more FPGA boards are used in the subsequent verification run (0, Τ ₁ ), ( It is also possible to perform parallel execution on Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ) and Ｂ ₁ , Ｂ ₂ , ... Ｂ _n .

As a tenth example, the verification device proposed by the present invention includes verification software, one or more simulators, one or more computers, and one or more FPGA boards installed in the one or more computers, wherein the one or more simulators and one or more computers are computer networks. Is connected. To perform the verification in such a verification apparatus, the first verification execution is performed by using the simulator using the first verification execution platform as one or more simulators (if the two or more simulators are used, distributed simulation is performed), 1 Subsequent verification runs are performed using one or more FPGA boards. The advantage of such a method is that not only can the utilization rate of one or more simulators be increased, but also the execution speed of the verification can be increased. First of all, in order to increase the utilization of the simulator, when design verification is performed only by simulation, all signals and variables existing in the design code are selected as a probe to detect and correct design errors. In this way, if the design code is designed to have 100% visibility and the simulation is performed, the execution speed of the simulation is approximately twice or more compared to the case where it is not. Therefore, instead of the conventional method, the method of the present invention performs the first verification run by using a simulation by probing only the minimum signals and variables necessary for the verification run after the first probe during the verification execution process. At the same time, it is possible to increase the utilization rate of the simulator by minimizing the degradation of the execution speed of the simulation and at the same time allowing the one or more simulations to be used for another verification of the same design or verification of another design as soon as the first verification execution is completed. Post-primary verification runs are performed using one or more FPGA boards. The following methods can be used to speed up the verification run in the case of performing the post-primary verification using more than one FPGA board. One possible method is to use two or more FPGA boards to run two or more verification intervals in parallel and, if necessary, integrate the results of these two or more FPGA boards as a result of the entire verification run. To do this, the simulator collects the minimum amount of information needed to perform parallel execution of two or more FPGA boards after the first step in the first verification run. There can be two types of minimum information needed to perform verification using these FPGA boards in parallel. One is to run the first verification run (simulation run) and save all the state information present in the DUV at a certain interval (for example, once every 50,000 nanoseconds for verification time) or at one or more points of time desired by the user. Time parallelism information obtained by performing a probe on the entire interval of the verification execution for the input / output and storing the same. The other is a spatial parallel obtained by performing a probe on the entire interval of the verification execution for all inputs and inputs and outputs present in each of the two or more blocks present in the DUV during the first verification execution (simulation execution). Possible information.

The time parallelizable information enables the first verification execution interval (0, T ) to be divided into two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ ) Each of these intervals can be independently performed in parallel on each of two or more FPGA boards in execution through the first and subsequent FPGA boards. The spatially parallelizable information allows the entire DUV to be divided into two or more blocks Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , and these blocks are each independently paralleled on each of the two or more FPGA boards in the post-first verification run. To be performed as In addition, the temporal parallelism and the spatial parallelism information are collected at the same time during the verification run through the first simulation run, and two or more FPGA boards are used in the subsequent verification run (0, Τ ₁ ), ( Τ ₁ , 수행 ₂ ), ... ( Τ _n-1 Τ ) and Ｂ ₁ , Ｂ ₂ , ... Ｂ _n are all possible in parallel.

To use time-parallel information when using the FPGA board for post-primary verification runs, write probes to all flip-flops, latches, and memory present in all or part of the DUV implemented in one or more of the FPGAs on the FPGA board. And in some cases read probes. The method of performing the read probe or the write probe on the verification target implemented in the FPGA is described in detail in US Pat. No. 6,701,491 and PCT patent pending (PCT / KR01 / 01092). It is also possible to use the US patent US 6,701,491 and the PCT pending patent (PCT / KR01 / 01092) to have 100% visibility of the DUV implemented on the FPGA board.

In the examples described above, it is advantageous to perform post-primary simulations in parallel using two or more FPGA boards, but if there is one FPGA board available, two or more section- or block-by-block design verifications in parallel It is also possible to perform sequentially instead of performing. In such a piecewise sequential execution process _{(0, Τ 1), (} Τ 1, Τ 2), ... when the time information can be configured in parallel to the _(n-1 Τ Τ) has on the back at the verification time (T _n-1 , T ) through ( T _n-1 , T _n-2 ) ... ( T ₁ , T ₂ ) and the leading (0, T ₁ ) Once the location and cause of the circuit is known, it is possible to bypass design verification with subsequent FPGA boards. In addition, when the logic capacity of one or more FPGA boards mounted on one or more FPGA boards is smaller than the gate capacity of the DUV, the one or more FPGAs may be applied to each of the blocks or blocks generated by arbitrarily partitioning the DUV. Implement and run verification runs sequentially.

As a last example, the verification apparatus proposed by the present invention comprises verification software, at least one simulator, at least one computer, and at least one formal verification tool (model inspector or characteristic inspector) installed in the at least one computer. In the verification apparatus, the verification is performed using the simulator using the first verification execution platform as at least one simulator, and the verification after the first is performed using at least one formal verification tool. The advantage of this method is that not only can the utilization of the simulator be increased, but the speed of the verification can be increased. First of all, in order to increase the utilization of the simulator, when design verification is performed only by simulation, all signals and variables existing in the design code are selected as a probe to detect and correct design errors. In this way, if the design code is designed to have 100% visibility and the simulation is performed, the execution speed of the simulation is approximately twice or more compared to the case where it is not. Therefore, instead of the conventional method, the method of the present invention performs the first verification using one or more simulators, and probes only the minimum signals and variables necessary for the verification after the first step in the verification execution process. It is possible to increase the utilization of the simulator by minimizing the execution speed reduction of the simulation by the same time, and at the same time, allowing the one or more simulators to be used for another verification of the same design or verification of another design as soon as the first verification execution is completed. . Post-primary verification runs are conducted using one or more formal verification tools. The following methods can be used to speed up the verification execution in the case where the verification execution after the first step is performed through the model inspection or the characteristic inspection process using one or more formal verification tools. One method is to use two or more formal verification tools to perform two or more model checks or feature checks in parallel, and, if necessary, integrate the results of these two or more model checks or feature checks as a result of the entire verification run. It is available. To this end, at least one simulator is used to collect the minimum information necessary to perform two or more formal verifications in parallel after the first step in the first verification run. The minimum information required to perform this simulation run in parallel is one or more state information present in the DUV. This is time parallelizable information obtained by storing state information present in the DUV at a predetermined interval (for example, once every 50,000 nanoseconds for verification time) or at a time desired by the user during the first verification execution (simulation execution).

The time parallelizable information is divided by the first verification execution interval (0, T _n ) divided by two or more intervals (0, Τ ₁ ), ( Τ ₁ , Τ ₂ ), ... ( Τ _n-1 Τ _n ). _{, Τ 1, Τ 2, ...} Τ n-1 Τ n time are all using the states _{s 0, s 1, s 2} , ... s n-1, s n in each or certain among these Using states selectively, it is possible to perform model tests or feature tests in parallel by setting the initial state to one of each of two or more formal verification tools. In addition, when the DUV is configured by dividing one or more blocks, such as Ｂ ₁ , Ｂ ₂ , ... Ｂ _n , the specific state S _i of the DUV at the specific verification point is divided into these blocks S _i1 , S _i2 , ... S _in which one or more block states of S _in are reconfigured, and each of these block states is set to the initial state, one for each of the two or more formal verification tools, and then performed in parallel for each block. It is possible.

If the first verification run is a simulation using the simulator as a verification platform, additional code added to the design code may directly extract the status information to obtain status information at a specific point in time of one or more verification cycles required in the time parallelizable information. (See US Pat. No. 6,701,491 and PCT Patent Application No. PCT / KR01 / 01092, which are pending in PCT for details.) Using the save command of the HDL simulator, saving the simulation state first and extracting the state information later If there is a command to enable the state information storage in the HDL simulator, it is also possible to use it.

Other objects and advantages of the present invention in addition to the above object will be apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Figure 1 (a) is a diagram schematically showing an example of a design verification apparatus according to the present invention composed of two or more verification platforms and a computer different from the verification software of the present invention running on a computer.

1 (b) and (c) schematically show still another example of the design verification apparatus according to the present invention, which is composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer. .

Figure 1 (d) is a view schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computer different from the verification software of the present invention running on a computer, specifically The platform for the first verification execution is configured with a hardware emulator, and the platform for the verification execution after the first is a diagram schematically showing an example in which one or more simulators are configured.

Figure 1 (e) is a diagram schematically showing another example of the design verification apparatus according to the present invention composed of two or more verification platforms and computer different from the verification software of the present invention running on a computer, specifically The platform for the first verification execution is configured as a simulation accelerator, and the platform for the verification execution after the first is a diagram schematically showing an example in which one or more simulators are configured.

Fig. 1 (f) is a diagram schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer.

Figure 1 (g) schematically shows another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically The platform for the first verification execution is configured as a simulation accelerator, and the platform for the verification execution after the first is a diagram schematically showing an example in which one or more model inspectors or characteristic inspectors are configured.

Figure 1 (h) is a diagram schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computer different from the verification software of the present invention running on a computer, specifically The platform for the first verification execution is configured with a hardware emulator, and the platform for the verification execution after the first is a diagram schematically showing an example in which one or more model inspectors or characteristic inspectors are configured.

Fig. 1 (i) is a diagram schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically, The platform for the first verification run is configured with a prototyping system, and the platform for the verification after the first is a diagram schematically illustrating an example in which one or more simulators are configured.

1 (j) is a diagram schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically, The platform for the first verification execution is composed of a prototyping system, and the platform for the verification execution after the first is a diagram schematically showing an example in which one or more model inspectors or characteristic inspectors are configured.

FIG. 1 (k) is a diagram schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically The platform for the first verification execution is configured with a hardware emulator, and the platform for the verification execution after the first is a diagram schematically showing an example in which one simulator is configured.

1 (1) schematically shows another example of the design verification apparatus according to the present invention, which is composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically The platform for the first verification execution is configured with a simulation accelerator, and the platform for the verification execution after the first is a diagram schematically showing an example in which one simulator is configured.

Figure 1 (m) is a diagram schematically showing another example of the design verification apparatus according to the present invention composed of two or more verification platforms and computer different from the verification software of the present invention running on a computer, specifically The prototype for the first verification run is configured with a prototyping system, and the platform for the first and subsequent verification runs is a diagram schematically showing an example in which one simulator is configured.

1 (n) is a diagram schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically FIG. 1 is a diagram schematically illustrating an example in which a platform for performing first verification is configured by a hardware emulator, and a platform for performing verification after the first is configured by one model inspector or a feature inspector.

Fig. 1 (o) schematically shows another example of the design verification apparatus according to the present invention, which is composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically, The platform for the first verification execution is configured as a simulation accelerator, and the platform for the verification execution after the first is a diagram schematically showing an example in which one model inspector or a characteristic inspector is configured.

Fig. 1 (p) schematically illustrates another example of a design verification apparatus according to the present invention, which is composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, specifically, The prototype for the first verification run is configured as a prototyping system, and the platform for the first and subsequent verification runs is a diagram schematically illustrating an example in which a model inspector or a property inspector is configured.

Figure 1 (q) is a diagram schematically showing another example of the design verification apparatus according to the present invention composed of two or more verification platforms and computer different from the verification software of the present invention running on a computer, specifically The platform for performing the first verification is composed of a hardware emulator, a simulation accelerator, or a prototyping system, and the platform for the verification after the first is schematically illustrated as an example of configuring one or more FPGA boards.

Figure 1 (r) is a diagram schematically showing another example of the design verification apparatus according to the present invention composed of two or more verification platforms and computer different from the verification software of the present invention running on a computer, specifically The platform for the first verification execution is configured with one or more simulators, and the platform for the verification after the first is a schematic diagram of an example in which an FPGA board is configured.

Figure 1 (s) is a diagram schematically showing another example of a design verification apparatus according to the present invention composed of two or more verification platforms and computer different from the verification software of the present invention running on a computer, specifically The platform for performing the first verification is composed of one or more model inspectors or characteristic inspectors, and the platform for performing verification after the first is an example of an FPGA board.

FIG. 2 is a diagram illustrating a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, in a hardware emulator, a simulation accelerator, or a prototyping system. The first and subsequent verification runs are schematically illustrated in a process performed in parallel by two or more simulators.

FIG. 3 illustrates a method of performing a first verification in a hardware emulator, a simulation accelerator, or a prototyping system in an example of a design verification apparatus according to the present invention, which is composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer. Performing the verification after the first stage is a diagram schematically illustrating a process of performing in parallel with two or more model inspectors or characteristic inspectors.

4 is a diagram illustrating a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, in a hardware emulator, a simulation accelerator, or a prototyping system. The first and subsequent verification runs are schematically illustrated to be performed in parallel using two or more simulators and a model inspector or a characteristic inspector together.

Fig. 5 shows the first verification execution in a hardware emulator, a simulation accelerator or a prototyping system in an example of a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer. The first and subsequent verification runs are schematically illustrated in a process of sequentially performing one simulator.

FIG. 6 is a diagram illustrating a design verification apparatus according to the present invention, which is composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, in a hardware emulator, a simulation accelerator, or a prototyping system. The verification after the first step is a diagram schematically illustrating a process of sequentially performing one model inspector or a characteristic inspector.

7 is a diagram illustrating a design verification apparatus according to the present invention composed of two or more verification platforms and computers different from the verification software of the present invention running on a computer, in a hardware emulator, a simulation accelerator, or a prototyping system. The first and subsequent verification runs are schematically illustrated in parallel with two or more FPGA boards.

8 is a flowchart schematically illustrating a process of finding and correcting one or more design errors existing in a design using the verification apparatus of the present invention.

9 is a flowchart schematically illustrating a process of performing design verification using the verification apparatus according to the present invention.

As described above, the purpose of the verification apparatus and the design verification method using the same according to the present invention is to perform verification verification for ultra-scale design verification by using different verification platforms such as simulators, simulation accelerators, hardware emulators, prototyping systems, and formal verification tools. The mixed process is performed by collecting the minimum information necessary to proceed very quickly and effectively after the first step through the verification execution using the first specific verification platform, and using this information after the first execution. The verification execution of the process proceeds in parallel or sequentially using a platform different from the first specific verification platform, thereby increasing the performance of the verification, the utilization of the verification platform and the efficiency of the verification, and enabling rapid debugging.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (17)

In a design verification device having verification software and two or more different verification platforms, The verification software adds additional code or additional circuitry to the gate-level netlist generated by design code or synthesis in an automated manner to perform a primary verification run on one or more of the other verification platforms. At least one verification platform used for the first verification run after the first verification run, and at least one other verification platform performed on one or more other verification platforms. It is possible to automatically collect the minimum information necessary for the verification executions to be performed on the blocks existing in the level netlist in the first verification execution process, and to perform the primary verification using the one or more primary verification platforms. Collect the minimum information while doing, Using this collected information, it is possible to quickly perform one or more verification runs after the first phase on at least one verification platform different from at least one specific verification platform used for the first verification run. Design Verification Device. The method of claim 1, On at least one verification platform different from at least one other verification platform used for the first verify run after the first verify run while performing a first verify run on a particular verify platform of the at least two other verify platforms. Automatically collect the minimum information necessary to ensure that verification runs can be performed on the verification cycle time intervals of the verification runs performed or on blocks in the gate-level netlist generated by design code or synthesis. And collect the minimum information while performing the first verification run using the one or more verification platforms for the first verification run, and by using the collected information, one or more used in the first verification run. One or more swords that differ from one or more than a specific verification platform Design verification device that may enable verification by that need not be started after the first one or more verification of the execution from zero verify cycle time on the platform quickly. The method of claim 1, At least one verification platform that is different from at least one other verification platform used for the first verify run after the first verify run while performing the first verify run on a particular verify platform of at least two other verify platforms. Verify cycle time intervals of the verification run performed on the system or the minimum information necessary to ensure that the verification runs can be performed on blocks in the gate-level netlist generated by the design code or synthesis. Enable the collection, perform the first verification run using the first verification platform, collect the minimum information, and use the collected information to use the first or more verification platforms for the first verification run. At least one specific verification platform used to run the verification As described above, verification can be performed quickly by allowing only one or more specific blocks present in the gate-level netlist generated by the design code or the synthesis in one or more verification executions after the first stage. Design verification device that makes it possible to do. In the design verification method that locates and corrects a design error existing in the gate-level netlist generated by the design code or the synthesis by performing a design verification using a mixture of two or more verification platforms, The design verification run may be at least one different from at least one specific verification platform used for the first verification run and the first verification run on one or more specific verification platforms of the two or more verification platforms. It is divided into one or more verification runs on the verification platform, and the verification cycle time intervals or design codes of one or more verification runs performed on another verification platform after the first verification execution while performing the first verification execution. It is possible to automatically collect the minimum information necessary to allow verification executions to be performed on blocks existing in a synthetically generated gate-level netlist, and to provide the at least one primary verification platform. Collect the minimum information while performing the first verification run using By using this collected information, a particular verification cycle time period of a verification run in at least one verification run after the first phase on at least one verification platform different from at least one verification platform used in the first verification run. Verification method that enables verification to be performed quickly by performing verification only on one or more specific blocks in the gate-level netlist generated by the network, the design code, or the synthesis. The method of claim 4, wherein In the design verification method that locates and corrects a design error existing in the gate-level netlist generated by the design code or the synthesis by performing a design verification using a mixture of two or more verification platforms, The at least one verification platform that differs from the at least one verification platform used for the first verification run on one or more of the two or more verification platforms and the one or more specific verification platforms used after the first verification run. Specific verification cycle time periods or design codes of a verification run in one or more verification runs performed on another verification platform after the first verification run while performing the primary verification run. (B) to automatically collect the minimum information necessary for the verification executions to be performed on one or more specific blocks present in the gate-level netlist generated by the synthesis, and the one or more Performing the first verification run using the first verification platform. Collect one piece of information, and use this collected information to verify that the subsequent verification run has a zero verification cycle time on at least one verification platform different from at least one particular verification platform used in the first verification run. Verification methods that enable faster verification by eliminating the need to start from scratch The method according to claim 4 or 5, Fast verification by performing parallel execution on two or more verification platforms, each of one or more verification runs on one or more verification platforms, different from one or more specific verification platforms used for post-primary verification runs. Verification methods that make it possible to perform The method of claim 6, Two or more verification platforms configured to perform each of one or more verification runs on at least one verification platform different from at least one particular verification platform used for the first verification run after the first. Verification method that consists of different different verification platforms and makes it possible to perform verification quickly by performing them in parallel The method according to claim 4 or 5, Verification method that enables verification by sequentially performing each of one or more verification runs on a verification platform different from one or more specific verification platforms used for the first verification run after the first. The method according to claim 4, 5, 6, 7, or 8, In one or more verification runs after the first phase, the entire verification cycle section or verification cycle specific section to be executed in each verification execution starts from two or more status information collected in the first verification run using one or more specific verification platforms. In the process of setting up one or more verification platforms different from one or more specific verification platforms used for executing the first verification, and executing the other verification platform in order two or more times, 1 At the time of executing the next verification, the state information at which the state information is stored at the end of the verification time is first set in the one verification platform to proceed with the status information. Subsequent executions are also performed as the one verification platform. In the process of performing the first verification, the time when the state information is saved is followed by the verification time. The gate level generated by the design code or the synthesis is made by setting the one verification platform in the order of priority and performing each of the first and subsequent verification executions using the two or more state information in the order from the rearmost to the verification time. Design verification method to perform probe on signals and variables in netlist The method according to claim 1, 2, 3, 4, or 5, Design verification method that includes minimum information collection to store all DUV status information and input / output information of DUV in the form of one or more files at regular intervals or at specific time points during the first verification process. The method according to claim 1, 2, 3, 4, or 5, In the case where the verification platform used for the first verification run is one or more simulators, the minimum collection of information includes storing the simulation state in the form of one or more files at regular intervals or at specific points in time during the first verification run. Design verification method The method of claim 11, Using the save command of the simulator to save the simulation state at one or more time points during the first verification execution using the one or more simulators, and the first and subsequent verification runs are extracted from the selected one or more simulation states. Verification methods to get you started The method according to claim 1 or 2 to 3 or 4 to 5, Minimal collection of information involves continuously probing and storing the inputs and inputs and outputs of specific blocks in the gate-level netlist generated by the design code or synthesis during the first verification process and storing them in one or more files. Design verification method. The method according to claim 6 or 7, Two or more verifications installed on two or more computers connected to the computer network by converting each subsequent verification run into two or more partial verification runs using each of two or more DUV status information stored in the first verification run. Platforms are used to set each of the at least two status information to each of the at least two verification platforms so that at least two partial verification runs can be executed in parallel with the at least two verification platforms independently of each other, Design verification method that uses computer network to transmit to one computer and integrates it as a whole verification result The method according to claim 6 or 7, Two or more executable files obtained by compiling two or more blocks obtained through the first verification run after each first verification run, and two or more probe files that probe all inputs and inputs and outputs of each of these blocks during the first verification run. Are independently executed in parallel using two or more verification platforms installed on two or more computers connected by a computer network, and the two or more executed results are transferred and integrated into one computer using a computer network to provide a total verification result. Design verification method The method of claim 3, wherein The verification used in the first verification run to select one or more status information among the one or more status information stored at one or more time points during the first verification run so that the design verification after the first step can be started from the selected one or more status information. Design verification method that performs a probe on signals and variables in the gate-level netlist generated by design code or synthesis while performing verification at least once after setting up verification platform different from platform at least once The method of claim 4, wherein At least one of the one or more probe files that are stored by probing and storing inputs and inputs and outputs for one or more blocks in the gate-level netlist generated by the design code or synthesis during the first verification run. Is selected from among one or more files generated by compiling for the verification platform different from the verification platform used in the first verification run using the selected one or more probe files and the corresponding one or more blocks. Design verification method for performing the additional probe by using a file associated with the corresponding one or more blocks having signals and variables present in the gate code netlist generated by the design code or the synthesis that requires the additional probe