KR20030023485A - Design Verification Apparatus Using Mixed Emulation, Simulation, and Formal Verification - Google Patents

Abstract

PURPOSE: A device for a design verification is provided to remove design errors existing in a design verification-objected circuit rapidly using a hardware input/output probe method and a software input/output probe method by mixing an emulation and a simulation of a large scale digital system with a formal verification or a semi-formal verification. CONSTITUTION: A design verification system software is executed in a server computer. The server computer is connected to at least one computer having a simulator(for example, an HDL simulator, a logic simulator, or a cycle-based simulator) through a computer network. A design verification interface module(26) connects the server computer having the design verification system software to at least one hardware board including an RFPD(Reusable Field Programmable Devices) having a high capacity digital circuit. The design verification interface module(26) creates a system clock necessary for an input/output probe with respect to a design verification-objected circuit, at least one user clock and probe clock being created from the system clock, an operation mode control signal, a probe mode control signal, and a probe memory read/write signal based on a control of the design verification system software, supplies the signals to a prototyping board or a PCB, if necessary, and controls the prototyping board or the PCB.

Description

Design Verification Apparatus Using Mixed Emulation, Simulation, and Formal Verification

The present invention relates to a technology for design verification of a multi-million-gate or more digital circuit designed. The present invention relates to a real hardware implementation of a multi-million-gate or more digital circuit designed as a programmable chip or a custom semiconductor chip, using a combination of emulation and simulation techniques. The present invention relates to a design verification method for quickly eliminating one or more design errors present in the multi-million gate class or more digital circuit, and a design verification apparatus for the same.

With the recent rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuit design has grown from at least millions of gates to tens of millions of gates, and its composition has become extremely complicated. As the trend is expanding, more than 100 million gate designs are expected in the near future. However, competition in the market is getting fiercer, and therefore, a good product must be developed in a short time, and there is an increasing need for an effective method for efficiently designing and verifying a circuit designed in an automated manner in a short time.

Until now, the simulator, which is a software approach, has been mainly used to design and verify the designed digital circuit. However, the simulator has to sequentially execute the software code composed of the sequential instruction sequences that model the circuit to be verified. Design verification times for designs beyond millions of gates are extremely long and unprecedented, and there is a limit to integrating with other surrounding hardware environments to verify the entire system (called ICE, In-Circuit Emulation). In addition, in order to perform design verification using simulation, an input pattern sequence for design verification should be generated in the design verification target circuit. However, as the size of the design verification circuit increases, the size of the input pattern sequence increases in proportion to the exponential function, and in most cases, a large amount of time and cost must be invested.

In contrast, a hardware emulation-based design verification method using a designed circuit as a real chip is to verify the digital circuit in a situation where all components of the designed digital circuit are actually operated in parallel on the implemented chip. Compared to other hardware environments, it is possible to verify the design up to 1 million times faster than the integrated environment. In addition, when design verification is performed by integrating with other surrounding hardware environments using the ICE method, since the actual input pattern sequence is supplied to the design verification target circuit in the surrounding hardware environment, the process of manually generating it may be omitted. However, emulation has a disadvantage that it is very inconvenient to perform debugging compared to simulation, and its main cause is the visibility that can know the logic value of numerous signal lines in the design verification circuit implemented in the programmable chip or the custom semiconductor chip. vlsibility is much lower than that of simulation. In addition, if emulation using programmable chips or custom semiconductor chips is used, the execution can be performed at extremely high speed. However, if one or more design errors exist in the circuit to be verified, the design errors can be corrected. In this case, it is necessary to reprogram the programmable chip or to manufacture the custom semiconductor chip again. This process requires a very long time and sometimes a high cost. In general, the design is not verified at the initial stage of design. Many design errors exist, and these design errors are usually corrected from several times to tens of times. Therefore, design verification using emulation is not desirable in such a situation.

The patent application "Rapid input / output probe device and input / output probe method using the same and a mixed emulation / simulation method based on the same" (Patent Application No. 10-2000-0034628) is a reusable field programmable device (programmable chips) Design validation for digital systems using any emulation and arbitrary simulation with custom semiconductor devices such as Devices (hereinafter referred to as "RFPD"), application specific integrated circuits (ASICs), or application specific standard products (ASSPs) It suggests how to do this effectively.

However, in addition to any emulations and simulations, as well as any other patents, not only the previously filed patents, but also any formal verification or any semi-formal verification can be used in the digital system. It does not present a way to effectively perform design verification. Formal verification or semi-formal verification enables white-box verification or gray-box verification using Assertion, so that the result of a circuit malfunction due to a design error is delivered to the output of the circuit to be verified. Even if it is not done, it is possible to automatically detect design errors by using an inspector or monitor that checks whether the assertions are satisfied or violated. This is called ABV (Assertion-based Verification). However, the disadvantage of formal verification or semi formal verification is that the verification execution time is very slow compared to the simulation.

Accordingly, it is an object of the present invention to provide an arbitrary emulation and any simulation of any large scale digital system implemented in hardware using one or more RFPDs for ultra-scale design verification and any formal verification or any semi- Minimize the elimination of numerous design errors in the circuit to be verified through design verification by using a combination of semi-formal verification and design verification using both the hardware I / O probe method and the software I / O probe method. It is to provide a design verification device that can be performed quickly at a high cost.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows a design verification apparatus of the present invention.

Fig. 2 is a diagram schematically showing an example in which an output probe addition circuit is added to a design verification target circuit.

3 is a diagram schematically showing an example in which an input probe addition circuit is added to a design verification target circuit;

4 is a diagram schematically showing an example in which a tester or a monitor is built in the input probe addition circuit;

<Description of the symbols for the main parts of the drawings>

12: RFPD 20: Computer for Server

26: interface module 28: interface cable

30: Component other than one or more RFPD in which the design verification target circuit on any prototyping board is implemented.

32: Design verification system software 34: Arbitrary simulator

35: random computer

44: random prototyping board 74: multiplexer

73: Single Input Flip-Flop with Asynchronous Set / Reset and Synchronous Enable

75: dual input D flip flop 76: single input D flip flop

77: dual input flip-flop with asynchronous set and asynchronous reset

78: Single Input Flip-Flop with Asynchronous Set and Asynchronous Reset

79: Tri-state buffer

86: output probe target signal line

87: flip-flops forming a shift register of an additional circuit for the output probe

88: flip-flops forming the shift register of the additional circuit for the input probe

90: simulation circuit for design verification

92: Inspector or monitor implemented in hardware

In order to achieve the above object, the design verification apparatus according to the present invention provides a design verification system software and a design verification interface module. The design verification interface module may be composed of an interface module 26 and an interface cable 28. The design verification system software runs on a server computer, which is connected through a computer network with one or more computers having any simulator (eg HDL simulator, logic simulator, or cycle-based simulator). Any one or more of the computers may have any formal verification tool or semi formal verification tool. The design verification interface module is one or more hardware boards or prototyping hardware platforms or emulation hardware platforms that are equipped with server computers with design verification system software and one or more RFPDs implemented with millions of gate-class digital circuits designed. Another important feature of the design verification interface module is the system clock needed for the input / output probes to the circuit under test and the one or more users generated from the system clock. Clocks, probe clocks, operation mode control signals, probe mode control signals, and probe memory read and write signals are generated under the control of the design verification system software and supplied to any prototyping board or PCB as needed. Stand any prototype PCB control board or any of the action. To this end, the design verification interface module has its own FPGA or CPLD, a microprocessor or microcontroller, or a dedicated ASIC / ASSP chip. Brief Description of the Drawings Figure 1 is an embodiment of the present invention comprising a design verification system software and a design verification interface module operating in a server computer, and one or more arbitrary computers having arbitrary simulators through a server computer and a computer network (for example, LAN, WAN, ATM, etc.). It is a figure which shows schematically the design verification apparatus about. Specifically, the design verification interface module 26 may be mounted in a PCI slot or connected to a secondary secondary system bus (such as a SUN workstation) to be connected to the Peripheral Computer Interface (PCI) bus of the server computer. It is common to connect to the S-bus, but if high speed is required, it may be connected to the main bus, which is the primary system bus of the server computer. Universal Serial Bus), parallel port or serial pod can be connected to it, and any server computer, any prototyping board or any PCB is connected.

The design verification system software, via the design verification interface module, can be used to design part or all of the millions of gate-level design verification circuits implemented on any prototyping board or PCB at any point or situation desired by the user during the design verification process. The complete state information or the partial state information about the state can be read from the prototyping board at any point in time or vice versa, or vice versa. Here, state information refers to the values of the memory elements (flip-flops or latches) of the digital circuit and the contents of the memory (RAM or ROM). Complete state information refers to the values and all the values of all the memory elements of the circuit for design verification. The partial state information refers to the value of the memory elements of the portion of the design verification target circuit and / or the contents of the portion of the memory. In addition, the memory device is different from the memory, and the memory device means flip-flop or latch, and the memory refers to all kinds of random access memory (RAH), PROM, EPROM such as SRAM, DRAM, SDRAM, Rambus DRAM, etc. In other words, logical information refers to a binary logic sequence appearing on any one or more signal lines of a digital circuit. The reason that the logic value information is different from the state information is that the logic value information is not limited to the values of the memory elements and the contents of the memory, but the combination may also include the output value or the input value of the gate.

The design verification system software includes a probe circuit synthesizer that converts input probes or output probes or input / output probes to specific signal lines present in the circuit under design verification in an automated manner. By adding the additional circuit to the design verification target circuit, a completed circuit (which is called an extended design verification target circuit) is generated in an automated manner. The role of the probe additional circuit included in the extended design verification target circuit is that in the case of the output probe, the circuit part formed by adding the additional circuit has a shift register structure to shift the shifting operation synchronized with the probe clock just before the shifting operation. The logic values of the registers have the logic values of the signal lines in the circuit to be output probe.In the case of the input probe, the circuit part formed by adding an additional circuit has a shift register structure to perform the shifting operation. By using a specific logic value can be displayed after the shifting operation is completed on the signal lines in the circuit that is the input probe target, in the case of input and output probes, each of the input probe and the output probe can be performed at a desired time point, When normal operation is required, the additional circuit The even to to operate in functional properties logic circuit that (logical functional behavior) anji not a variation of the circuit design verification. Alternatively, when the design verification object is dictated by a hardware oral language (hereinafter referred to as HDL) code, the HDL code representing the behavior of the probe additional circuit is added to the HDL code to be verified by design, and is completed. In the case of the output probe, the HDL part formed by adding the additional HDL code expresses the shift register behavior, so that the shifting operation synchronized with the probe clock is applied to the register HDL code in the HDL code representing the shift register behavior immediately before the shifting operation. The signal values of the signal line of the signal line have the logic values of the signal lines of the HDL code which is the output probe target.In the case of the input probe, the HDL code part formed by adding the additional HDL code is shift register structure and synchronized to the probe clock. Shifted movements of the input probe using the shifting movements Output of the HDL code The specific logic values can be displayed after the shifting operation is completed on the signal lines in the target HDL code.In the case of the input / output probe, each of the input probe and the output probe can be performed at a desired time point. When normal operation is needed, even if an additional circuit is added, the functional logical behavior of the design verification HDL code is not modified.

In addition, when the signal lines to be probed are the outputs of the memory device, the role of the probe additional circuit included in the extended design verification target circuit is that in the case of the output probe, the circuit portion formed by adding the additional circuit has a shift register structure. A shifting operation synchronized to the probe clock is performed. The logic values of the shift register immediately before the shifting operation are used to output the logic values of all or a part of the memory elements in the circuit to which the output probe is targeted. A synchronous set or reset operation, or an asynchronous set or reset operation on the signals of the HDL code to be expressed, followed by a synchronous set or reset or asynchronous set or reset operation. This is a synchronous disable operation that inputs the logical value of the signals that are the input probe targets. In the case of input / output probes, each of the input probe and the output probe can be performed at a desired time point, and when the normal operation is required, the behavior of the design verification HDL code is not modified even if the probe additional circuit is added. .

The specific implementation method of the probe additional circuit for the above-described probe is a previously filed "quick input and output probe device, input and output probe method using the same and mixed emulation / simulation method based on the same" (PCT application number: PCT / KR01 / Since much of 01092 is already mentioned in detail, this patent will refer to only a few cases of additional ones.

FIG. 2 is a diagram schematically illustrating an example of an implementation of a probe additional circuit that performs an output probe on arbitrary signal lines existing in a design verification target circuit.

FIG. 3 is a diagram schematically illustrating an example of an implementation of a probe additional circuit that performs an input probe on arbitrary signal lines that are inputs or outputs of a combination circuit existing in a design verification target circuit, in this case a memory device Since the input probe should be performed on the signal lines other than the output of the circuit, the circuit portion formed by adding the additional circuit has a shift register structure to perform the shifting operation, and the input probe data forms the shift register structure using the shifting operation. After storage in flip-flops, the select input of the multiplexer 74 is controlled so that the input probe data appears on each of the corresponding signal lines.

Additionally, the design verification target circuit includes memory such as RAM or ROM, and these memories are also provided on-chip memory (specifically, for example, distributed RAM or block RAM of Xilinx FPGA). In the case of using an embedded array block of Altera FPGA, a memory read / write additional circuit is additionally included in the IOP probe additional circuit. The memory read / write additional circuit is controlled by the design verification system software, and in the output probe mode, the output probe is read out by reading all the contents of the memory or the specific region in the design verification target circuit implemented in the RFPD in a predetermined order. It can be read through the interface module and the interface cable through the design verification system software in an automated manner.In the input probe mode, the data of the design verification system software is transferred to the RFPD input probe through the interface cable and the interface module. Through the RFPD, the write operation is performed in a predetermined order in all regions or specific regions of the writable memory in the design verification target circuit implemented in the RFPD. A specific example of the implementation of such a memory read / write additional circuit is already described in the "quick input / output probe apparatus and input / output probe method using the same and a mixed emulation / simulation method based on the same" (PCT application number: PCT / KR01 / 01092). Since it is mentioned in detail, it will be omitted in the present patent.

In the present invention, the output probe line and the input probe line may exist as separate independent unidirectional probes, or may exist as bidirectional probes in which the output probes and the input probes are combined. In addition, the probe clock used in the present invention may generate and use a clock separate from the user clocks used in the design verification target circuit from the system clock, or may use one of the user clocks (for example, the fastest clock).

The design verification system software includes a step of manually inputting or automatically determining an onboard signal line and memory present in a design verification target circuit or an onboard signal and memory block present in a design verification HDL code. In order to implement the design verification circuit in one or more RFPDs mounted on an arbitrary prototyping board or an arbitrary PCB, the logic of the signal lines on the output probe or the specific time zone in the memory area to be read or when a specific situation occurs Arbitrary prototyping boards or arbitrary data are displayed so that the values appear sequentially on the output probe only for a certain period of time, and the signal lines on the input probe or the memory area to be written can have logic values applied to the input probe at specific times. Design verification subjects assigned to one or more RFPDs mounted on the PCB In further comprising the step of generating the verified design the circuit extended by adding additional circuitry for the probe. In addition, for the signal lines on the output probe and the memory area to be read, the logic values and the contents of the memory at specific time points on the signal lines on the output probe are displayed on the output probe of the corresponding RFPD using the probe additional circuit. The value displayed on the line is transmitted to the server computer through the design verification interface module. For the signal lines on the input probe and the memory area to be written, the input probe data is generated from the status information obtained from the server computer. The signal line on the input probe of the RFPD is applied while synchronizing with the probe clock only, or synchronized with the probe clock, and the probe mode is properly changed between the input probe mode and the output probe mode through the probe mode control signal line. By applying the signal lines on the input Have the logic value been sent contents of the writing target memory area and rigap this through the input probe lines by a step of setting gekkeum the status information of the design verification target circuit implemented in RFPD equal to the state information obtained from the server computer.

By using the above-described design verification apparatus and design verification method, any prototyping board or any PCB equipped with one or more semiconductor chips in which an extended design verification target circuit in which a probe additional circuit is added to the design verification target circuit is implemented. And arbitrary simulators can be used to perform design verification by temporally or spatially mixing emulation and simulation. In other words, such emulation and simulation mixed verification may be performed by the design verification system software. The design verification system software may manually designate the signal signals and memory blocks present in the circuit to be verified, or the signals and memory blocks present in the design verification HDL code. The signal lines on the output probes present in the entire design verification circuit or part of the design verification circuit implemented in one or more RFPDs mounted on any prototyping board or any PCB. Alternatively, logic values at a specific time zone or at a specific time in the memory area to be read are sequentially displayed on the output probe only for a certain time, and signal lines or input memory areas on the input probe are specified to the input probe. To have logical values applied to the time zone The entire design verification circuit or the extended design by adding the probe additional circuit to the entire design verification circuit or part of the design verification circuit which is allocated to one or more RFPDs mounted on a prototyping board or an arbitrary PCB Generating a portion of the circuit to be verified. In addition, for the signal lines on the output probe and the memory area to be read, the logic values and the contents of the memory at specific time points on the signal lines on the output probe are displayed on the output probe of the corresponding RFPD using the probe additional circuit. The value displayed on the line is transmitted to the server computer through the design verification interface model so that the simulator can calculate the current status information or the logic information of the current probe signal lines of the entire design verification circuit or the part of the design verification circuit. For the signal lines on the input probe and the memory area to be written, the input probe data is generated from the state information or logic value information obtained through the simulation on any computer, and then the interface module and the interface cable are connected. Input probe of the corresponding RFPD Apply to the target signal lines while synchronizing only with the probe clock, or by synchronizing with the probe clock and changing the probe mode between the input probe mode and the output probe mode through the probe mode control signal line. By making the logic value and the contents of the memory area to be written have the logic values transmitted through the input probe line, the state information or logic value information of the entire design verification circuit or part of the design verification circuit implemented in the RFPD is stored for a certain period of time in the simulator. And setting the same as the state information or logic value information generated through the simulation. The exchange of state information or logic value information between any one or more RFPDs mounted on any prototyping board or any PCB and any simulator can be accomplished by using a foreign language interface (FLI) or a programming language interface (PLI) provided in the simulator. This can be done at the API (Application Program Interface) level, with minimal overhead.

In addition, in the above-mentioned simulation process, the AVB method can be adopted by incorporating a tester or monitors in the design verification target circuit if necessary, and in the emulation process, when the design verification target circuit is implemented in one or more programmable devices, A tester or monitor can be implemented together in a programming device to adopt a hardware-based AVB approach. The simulation / emulation hybrid method mentioned in the future is based on the use of AVB on the simulation side or AVB on the emulation side.

As described above, in order to perform mixed verification in an automated manner between emulation and simulation by using the design verification apparatus and the design verification method of the present invention, performance switching between emulation and simulation should be automatically performed. The execution mode switching can be performed every clock or when a specific condition is satisfied (for example, when a specific value is written twice to a specific register in the circuit). This execution mode switching condition can be two or more times temporally related to each other during the entire verification process. In such a case, the condition is satisfied in the order of the condition that is set first in the order of time later. Is let this mode performs the switching of the logic emulation from a simulation at the time in emulation or simulation. To do this, it is necessary to store the execution mode switching conditions in a queue, which is called the execution mode switching condition queue, and maintains it in the form of a data structure in the design verification system software.

Through this I / O probe, it is possible to perform an emulation using an arbitrary prototyping board or an arbitrary PCB and a simulation performed by a server computer one or more times. In particular, when there is no combinatorial feedback loop in the circuit under design verification, the output probe signal lines are the output lines of all memory elements (flip-flops or latches) present in the circuit under design verification (output at this time). The values of all probed memory elements are referred to as complete state information.) Even when the output probe target signal lines are output lines of partial memory elements present in the design verification target circuit, one or more clock cycles are output from the output line values of these partial memory elements. If it is possible to determine all the values of the remaining memory devices (the values of the output probed partial memory devices at this time are called fully-capable partial state information), the logic values of the output probed signal lines are transferred to the simulator in the computer for emulation. The ion simulation can proceed continuously. If more than one combinational closed circuit is included in the design verification target circuit, each of the combinational signal lines present in the combined closed circuit that can cut the closed circuit in each combination closed circuit is also the output probe target signal line. Should be included in If the above emulation and simulation can be performed one or more times, alternately, there are numerous advantages in performing design verification using an arbitrary prototyping board or an arbitrary PCB.

First, design validation in current system on a chip (SoC) environments requires a great deal of time and money to create test benches for simulation. It is very difficult for designers to create their own test benches, which account for up to 80% of the overall design code size. In addition, it is very difficult for designers to create their own test benches in all SoC designs, considering all the many cases in which the actual designed chip is actually operated in a real environment. On the other hand, the ICE-based design verification method is capable of prototyping the circuit under design verification and interworking with the real environment, so that it is not necessary to create a test bench, and actual situations are produced by actual operation in the real environment. Therefore, it is possible to perform verification that is much more reliable than using a test bench. For the design verification by prototyping, the circuit to be verified must be implemented with one or more programmable devices. In general, however, there are many design errors, so in the early stages of design validation, which must correct these errors from as few as many to several tens of times, the circuits for design verification are designed so that design errors can be corrected for prototyping. The chip implemented must also be modified, which is very time-consuming and expensive, which cannot be used in the early stages of design, ie even when using the lowest programmable device (eg FPGA). Re-compiling the error-corrected design-verification circuit requires a re-compiling process of several hours to several tens of hours, which greatly increases the overall design verification time.

However, by using the design verification method proposed in this patent, it is possible to effectively solve these problems and perform design verification with minimum effort in a short time. That is, as already mentioned, emulation and simulation using an extended design verifying circuit or extended design verifying HDL code that adds a probe additional circuit or a probe additional HDL code to a design verifying circuit or a design verifying HDL code. Time and space in a systematic and automated way, when design validation is performed quickly using a mix of online and offline methods, it is not necessary to manually create a test bench from the early stage of the design. It is possible to use the results as they are, allowing for much more reliable design verification with much less time and cost. In addition, unlike other methods, the emulation method proposed in this patent utilizes an extended design verification circuit with a probe additional circuit, thereby providing perfect observability of signal lines present in the design verification circuit even during emulation. It is also important to have controllability.

Now, a method of having a high degree of observation and control during emulation as described above will be described in more detail, and FIG. 4 will be used for this purpose. 4 is a view schematically illustrating a situation in which the entire design verification target circuit is performed by emulation. As described above, not only the design verification target circuit but also an inspector or a monitor are embodied in a programmable device for emulation. Enable the ABV verification scheme in hardware.

In addition, similar to the "fast input / output probe device and input / output probe method using the same and a mixed emulation / simulation method based on the same" (PCT application No. PCT / KR01 / 01092), which is previously applied for the design verification method, the simulation is performed through simulation. Re-compile RFPD for all other signal lines, as well as signal lines that can be probed through the output probe in any design verification circuit implemented in one or more RFPDs on any prototyping board or any PCB. 100% probe is possible without process. The omission of this recompilation process is of utmost importance in the debugging process, since the time required to compile the latest multi-million-gate RFPD requires as little as tens of minutes to hours. Therefore, one of the most important things in the debugging process for the circuit implemented in the RFPD is to enable rapid debugging by maximally suppressing the recompilation of the RFPD. When design verification is performed using the above simulation and emulation, perfect observability and controllability of signal lines existing in the design verification target circuit necessary during debugging without recompiling the RFPD is required. It is also an important advantage.

Also, during the emulation process, the probe is obtained from one or more timeframes (assuming N timeframes) for which state information is desired in the design verification target circuit, and between the N timeframes. The input sequence applied in the circuit environment also obtains N through the probe and divides the simulation sessions following the emulation into N, and executes them in parallel with any M (M equal to or less than N) simulators in parallel to speed up the simulation. Can increase. In addition, the emulation process obtains one or more timeframes (assuming N timeframes) for which state information is desired in the design verification target circuit through the probe process, and randomly divides the formal verification session following the emulation into N. M (M is less than or equal to N) can be speeded up by performing a formal verification tool in parallel.

Other objects and advantages of the present invention in addition to the above object will be apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram schematically showing a design verification apparatus according to the present invention composed of one or more arbitrary computers having a design verification system software and a simulator running on a server computer, and a design verification interface module.

FIG. 2 is a diagram schematically showing an example of adding an output probe addition circuit to a design verification target circuit, and FIG. 3 is a diagram schematically showing an example of adding an input probe addition circuit to a design verification target circuit.

The extended design verification target circuit generated by adding the probe additional circuit to the design verification target circuit is implemented in one or more RFPDs on an arbitrary prototyping board or an arbitrary PCB, and executes the prototyping board to emulate the In the process of performing the verification, when the transition to simulation is necessary at a certain time or when a certain situation occurs, the design verification system software detects this and stops emulation and the one or more RFPDs under normal control of the design verification system software are normal. When the probe clock is applied to the RFPD after switching from mode to output probe mode, the logic on the signal lines that are probed through one or more output probes connected to the output of one flip-flop in each of the one or more shift register array structures Values are passed through the design verification interface module. However, the input / output probe point can be determined statically before emulation and can be determined dynamically, such as when a particular situation occurs during emulation, and when the specific situation occurs, In order to determine the input / output probe point which is dependent on the situation, an external device such as a logic analyzer can be observed and the input / output probe point can be determined, or the input / output probe point detector which detects the operation situation inside the RFPD By adding additional circuits, I / O probe status can be output, and the design verification system software can detect and start the I / O probe. When the input / output probe point detector circuit is additionally added to the design verification circuit along with the probe additional circuit inside the RFPD, the automatic generation and addition of the input / output probe point detector circuit is also in charge of the design verification system software.

In the case of input probes, the design verification system software generates input probe data for one or more RFPDs on the prototyping board, then switches the operation mode to the input probe mode under the control of the design verification system software, and then the probe clock One or more input probe data transmitted from the server computer through the design verification interface model through one or more input probes logically connected to the input of one flip-flop present in each of the one or more shift register array structures applied to the RFPD. The input probe data stored in flip-flops existing in each shift register array structure and the input probe data is finally output of the memory device (in the case of a latch, it is converted into an equivalent circuit using a flip-flop and a multiplexer). After applying it, For a detailed description, see PCT Application No .: PCT / KR01 / 01092). The set-up or reset operation of the flip flops on the input probe may be synchronous or asynchronous. Following a synchronous set or reset or asynchronous set or reset operation, a synchronous disable operation allows input probes to be made on one or more RFPDs mounted on any prototyping board or any PCB. If the input probe target signal lines are an output or an input of a combination circuit, the shift register array structure such that each of the outputs of the flip-flops existing in each of the shift register array structures in which the input probe data is stored is connected to the corresponding input probe target signal lines. An arbitrary protocol that controls the selection input of the multiplexer at the output of each flip-flop. Yiping be able to be done in the input probe RFPD board or the at least one mounted on any PCB.

4 is a diagram schematically illustrating a situation in which a tester or a monitor is embedded in a circuit to be verified for design. In this way, when the circuit and the tester or the monitor to be tested are implemented in hardware, the ABV method can be used for emulation. Let's do it.

As described above, the purpose of the design verification apparatus and the design verification method using the same according to the present invention is to verify the design verification using emulation, simulation, and formal verification of a large-scale digital system implemented in hardware for ultra-scale design verification. Even if the scale of the design verification target circuit exceeds the limit of simulation, the design verification method using the emulation, the simulation and the formal verification is applied to enable the design verification quickly. Specifically, it is not only possible to quickly find design errors, but also to fix these found design errors quickly.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (8)

A design verification apparatus comprising a design verification system software, at least one simulator, and a design verification interface module, The design verification system software may include a design verification target circuit implemented in one or more programmable elements mounted on an arbitrary prototyping board or an PCB, or a probe additional circuit or a probe additional circuit for a part or whole of an HDL code. Generate HDL code representing the behavior and present in part or all of the design verification target circuit or HDL code by adding the HDL code representing the behavior of the probe additional circuit or the probe additional circuit to the design verification target circuit or HDL code. An input probe, an output probe, or an input / output probe is enabled for one or more specific signal lines to be input probes for specific signal lines existing in part or all of the design verification target circuit or HDL code implemented in the one or more programmable devices. Circuits capable of output probes or input / output probes In addition to being implemented in one or more programmable devices, a checker or monitor for the ABV is also hardware-implemented in the one or more programmable devices to enable emulation of the design verification target circuit, and the design obtained in the emulation process through the probe. Using the information on the circuit to be verified and the information on the input sequence, the design can be verified by emulating the whole or part of the design verification target circuit or HDL code using one or more simulators on one or more computers. Design verification device. A design verification apparatus comprising a design verification system software, at least one simulator, and a design verification interface module, The design verification system software may include a design verification target circuit implemented in one or more programmable elements mounted on an arbitrary prototyping board or an PCB, or a probe additional circuit or a probe additional circuit for a part or whole of an HDL code. Generate HDL code representing the behavior and present in part or all of the design verification target circuit or HDL code by adding the HDL code representing the behavior of the probe additional circuit or the probe additional circuit to the design verification target circuit or HDL code. An input probe, an output probe, or an input / output probe is enabled for one or more specific signal lines to be input probes for specific signal lines existing in part or all of the design verification target circuit or HDL code implemented in the one or more programmable devices. Or a circuit capable of output probe or input / output probe One or more simulators using one or more simulators that are emulated and then run on one or more computers by using the information about the design verification target circuit and the input sequence obtained in the emulation process through the probe. Alternatively, in performing simulations of all or part of the HDL code, checkers or monitors for the ABV are embedded with all or part of the design verification target circuit or HDL code to perform the simulation and, if necessary, code coverage analysis during this simulation. Design verification device that enables design verification by performing together. The method according to claim 1 and 2, The information about the design verification target circuit and the input sequence obtained by performing the emulation are divided into two or more for each time zone, so that the simulation is performed in parallel using two or more simulators running on the two or more computers. Design verification device. In a design verification apparatus comprising a design verification system software, at least one formal verification tool, and a design verification interface module, The design verification system software may include a design verification target circuit implemented in one or more programmable elements mounted on an arbitrary prototyping board or an PCB, or a probe additional circuit or a probe additional circuit for a part or whole of an HDL code. Generate HDL code representing the behavior and present in part or all of the design verification target circuit or HDL code by adding the HDL code representing the behavior of the probe additional circuit or the probe additional circuit to the design verification target circuit or HDL code. An input probe, an output probe, or an input / output probe is enabled for one or more specific signal lines to be input probes for specific signal lines existing in part or all of the design verification target circuit or HDL code implemented in the one or more programmable devices. Circuits capable of output probes or input / output probes In addition to being implemented in one or more programmable devices, a checker or monitor for an ABV is also hardware-implemented in the one or more programmable devices to enable emulation of the design verification target circuit, and a design obtained in the emulation process through a probe. Using the information on the circuit to be verified and the information on the input sequence, the design is performed by emulation followed by the formal verification of all or part of the circuit or HDL code. Design verification device that enables verification. A design verification device comprising a design verification system software, one or more formal verification tools, and a design verification interface module, The design verification system software may include a design verification target circuit implemented in one or more programmable elements mounted on an arbitrary prototyping board or an PCB, or a probe additional circuit or a probe additional circuit for a part or whole of an HDL code. Generate HDL code representing the behavior and present in part or all of the design verification target circuit or HDL code by adding the HDL code representing the behavior of the probe additional circuit or the probe additional circuit to the design verification target circuit or HDL code. An input probe, an output probe, or an input / output probe is enabled for one or more specific signal lines to be input probes for specific signal lines existing in part or all of the design verification target circuit or HDL code implemented in the one or more programmable devices. Or a circuit capable of output probe or input / output probe One or more formal verification tools performed on one or more arbitrary computers following the emulation by using the information on the design verification target circuit and the input sequence obtained in the emulation process through the probe. In performing formal verification of all or part of the target circuit or HDL code, checkers or monitors for the ABV are incorporated with all or part of the design verification target circuit or HDL code to perform formal verification and, if necessary, this formality. Design verification device that enables design verification by performing code coverage analysis together during verification. The method according to claim 4 and 5, Design verification to divide the information on the design verification target circuit obtained by performing the emulation by two or more for each time zone and perform formal verification performed in parallel using two or more formal verification tools performed on the two or more arbitrary computers. Device. The method according to claim 1, 2, 3, 4, 5, or 6, The specific signal lines include the outputs of all latches or flip-flops present in the design verification target circuit, and the information about the design verification target circuit obtained in the emulation process through the probe is used in the design verification target circuit in one or more specific time frames. Design verification device that includes the status information of. The method according to claim 1, 2, 3, 4, 5, or 6, Design verification device wherein the programmable device is an FPGA or CPLD.