JPH06236414A - Method and device for verifying scan path logic - Google Patents

Abstract

PURPOSE:To verify the connection order of a flip-flop and an input signal on a scan path in a short time and completely in a CAD system. CONSTITUTION:A scan path or the like equivalent circuit generating means 1 generates a scan path or the like equipment circuit for only the scan path based on scan path connection information 6 representing the correct connection order of the flip-flop on the scan path, and outputs the net list of the circuit as a scan path or the line equivalent circuit net list 8. A control signal clamping means 2 generates a clamped logic circuit net list 9 in which a scan path control signal is set in a scan path operating state based on a logic circuit net list 7 with scan path representing the circuit configuration of the logic circuit set as a verification target. A logic equation conversion means 3 converts the scan path or the like equivalent circuit net list 8, the clamped logic circuit net list 9 to an equivalent circuit logic equation 10, a clamped logic circuit logic equation 11, and a logic equation comparison means 4 compares them with each other, and outputs a comparison result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path logic verification method for verifying the connection order of flip-flops forming a scan path and whether or not the input signal to the flip-flops during scan path operation is as intended by the designer. Regarding the device.

[0002]

2. Description of the Related Art When verifying the logical connection order of flip-flops forming a scan path and whether or not the input signal to the flip-flops during scan path operation is the one intended by the designer, conventionally, it is necessary to use a circuit diagram on a circuit diagram. I was checking it manually. However, there is a risk of oversight in manual confirmation.

Therefore, a logical simulation for operating the scan path is performed, and the simulation result and the expected value are compared to confirm the connection order of the flip-flops forming the scan path and the input signal of the flip-flop during the scan path operation. It has been conventionally proposed to do so (for example, Japanese Patent Application No. 3-157305).
issue).

The above-mentioned conventional technique will be described below by taking the logic circuit with a scan path shown in FIG. 6 as an example. The logic circuit shown in FIG. 6 has the scan path control signal SF
When M is "1", the scan path input signal SIN input to the terminal a is selected, and when it is "0", the selector SEL1 that selects the output signal of the combinational circuit L1 and the scan path control signal SFM are "1". In the case of ", the output signal of the flip-flop FF1 input to the terminal a is selected,
In the case of "0", the selector SEL2 for selecting the output signal of the combinational circuit L2 and the scan path operation clock CL
A flip-flop FF1 that takes in the output signal of the selector SEL1 according to K, and a scan path operation clock CL
The flip-flop FF2 takes in the output signal of the selector SEL2 according to K and outputs it as the scan path output signal SOUT.

When the logic simulation for operating the scan path is executed for the logic circuit with the scan path shown in FIG. 6, the scan path control signal SFM, the scan path input signal SIN, and the scan path operation clock CLK shown in FIG.
And the combination circuit L is set.
All the patterns that can be combined are set to the input signals of 1 and L2.

After setting the pattern, a logic simulation is performed. Then, the simulation result of the output signals of the flip-flops FF1 and FF2 and the simulation result of the scan path output signal SOUT are compared with the expected value shown in FIG.
Connection order of FF2 and flip-flops FF1 and FF2
It is determined that the input signal for is correct, and if they do not match, it is determined that they are incorrect. The expected value in FIG. 8 is that the flip-flop FF1 takes in the scan-path input signal SIN at the rising edge of the scan-path operation clock CLK, and the flip-flop FF2 takes in the value of the flip-flop FF1 at the next rising edge of the scan-path operation clock CLK. At the same time, it is expected that the value of the flip-flop FF2 will be output as the scan path output signal SOUT. Further, in FIG. 8, x indicates an indefinite value.

[0007]

As described above, in order to confirm that the connection order of the flip-flops forming the scan path and the input signals to the flip-flops are correct, the input signals to the combinational circuits L1 and L2 must be set. , It is necessary to set all the patterns that can be combined and perform a logic simulation. However, some actual logic circuits have thousands of flip-flops forming a scan path, and applying conventional techniques to such logic circuits requires a great deal of time for logic simulation. There is a problem that it becomes necessary. Further, in order to solve such a problem, it is conceivable to set all "1", all "0" or some random patterns in the input signal of the combinational circuit, but this constitutes a scan path. There is a problem that the connection order of the flip-flops and whether or not the input signals of the flip-flops are correct cannot be completely verified.

The object of the present invention is to verify whether or not the flip-flop connection order and the flip-flop input signal are correct in a short time and reliably even when the number of flip-flop stages forming the scan path is large. It is to provide a scan path logic verification method and apparatus.

[0009]

In order to achieve the above object, the present invention provides (A) scan path connection information indicating a correct connection order of flip-flops constituting a scan path in a logic circuit with a scan path to be verified. On the basis of the scan path connection information, a scan path equivalent circuit netlist that is a net list of scan path equivalent circuits in which flip-flops are connected in the connection order shown in FIG. Clamped, which is a netlist when the scan path control signal of the logic circuit with scan path to be verified is clamped to a signal value for operating the scan path based on the logic circuit net list with scan path showing the circuit configuration. Create a logic circuit netlist and use the scan path equivalent circuit netlist And converting the clamp already logic netlist respectively equivalent circuits logical expression and the clamp already logic logical expression is obtained so as to compare with the equivalent circuit logical expression and the clamp already logic formula.

Further, in order to achieve the above object, the present invention provides:
(B) The flip-flops are connected in the connection order indicated by the scan path connection information, based on the scan path connection information indicating the correct connection order of the flip-flops forming the scan path in the logic circuit with the scan path to be verified. A scan path equivalent circuit netlist that creates a scan path equivalent circuit net list that is a net list of the scan path equivalent circuit, and a scan path logical circuit net list showing the circuit configuration of the scan path logical circuit to be verified. And a control signal clamp means for creating a clamped logic circuit netlist which is a netlist when the scan path control signal of the logic circuit with the scan path to be verified is clamped to a signal value for operating the scan path based on the above. , The scan path equivalent circuit netlist, Logical expression conversion means for converting the ramped logical circuit netlist into an equivalent circuit logical expression and a clamped logical circuit logical expression, and a logical expression comparison means for comparing the equivalent circuit logical expression with the clamped logical circuit logical expression. Is provided.

[0011]

The scan path equivalent circuit creating means is based on the scan connection information indicating the correct connection order of the flip-flops forming the scan path in the logic circuit with the scan path to be verified, and the connection order indicated by the scan path connection information. A scanpath equivalent circuit netlist, which is a netlist of scanpath equivalent circuits to which flip-flops are connected, is created.

The control signal clamp means outputs the scan path signal of the logic circuit with the scan path to be verified to the scan path based on the logic circuit netlist with the scan path showing the circuit configuration of the logic circuit with the scan path to be verified. Create a clamped logic circuit netlist that is a netlist when clamped to the signal value that operates.

The logical expression conversion means converts the scan path equivalent circuit netlist and the clamped logical circuit netlist into an equivalent circuit logical expression and a clamped logical circuit logical expression, respectively, and the logical expression comparison means is equivalent circuit logical expression and clamped Compare with logic circuit logic formula.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a scan path equivalent circuit creating means 1 having scan path control signal information 5 and scan path connection information 6 as inputs,
Control signal clamp means 2 to which scan path control signal information 5 and logic circuit netlist 7 with scan path are input
And a logical expression conversion means 3 which receives the scan path equivalent circuit netlist 8 output from the scan path equivalent circuit creation means 1 and the clamped logic circuit netlist 9 output from the control signal clamping means 2, and a logical expression. A logical expression comparing means 4 which receives the equivalent circuit logical expression 10 and the clamped logical circuit logical expression 11 output from the converting means 3;
It is composed of the terminal device 12.

The scan path control signal information 5 includes the signal names of the scan path control signal, the scan path input signal, the scan path output signal, the scan path operation clock, and the signal value of the scan path control signal that sets the scan path to the operating state. I'm out.

FIG. 2 is a diagram showing an example of the contents of the scan path control signal information 5. In this example, the signal names of the scan path control signal, scan path input signal, scan path output signal, and scan path operation clock are respectively shown. SFM, S
IN, SOUT, and CLK indicate that the signal value of the scan path control signal SFM that brings the scan path into the operating state is "1".

The scan path connection information 6 indicates the connection order of the flip-flops on the scan path intended by the designer.

FIG. 3 is a diagram showing an example of the contents of the scan path connection information 6, and this example shows that the connection order of the flip-flops intended by the designer is FF1 and FF2.

The scan path added logic circuit netlist 7 shows the circuit configuration of the scan path added logic circuit to be verified.

The scan path equivalent circuit creating means 1 uses the scan path input signal, scan path output signal, scan path operation clock signal names included in the scan path control signal information 5 and the scan path indicated by the scan path connection information 6. Based on the connection order intended by the designer of the above flip-flop, it has a function of creating a netlist of scanpath equivalent circuits that execute only scanpath operations and outputting it as a scanpath equivalent circuit netlist 8.
That is, in the scan path equivalent circuit creating means 1, the flip-flops are connected in the order indicated by the scan path connection information 6, and each flip-flop is supplied with the scan path operation clock having the signal name included in the scan path control signal information 5. Then, the scan path input signal of the signal name included in the scan path control signal information 5 is input to the flip-flop of the input stage, and the scan path input signal of the signal name included in the scan path control signal information 5 is input from the flip-flop of the output stage. It has a function of creating a net list of the scan path equivalent circuit to which the scan path output signal is output and outputting it as the scan path equivalent circuit net list 8.

The control signal clamp means 2 has a scan path indicating the signal value of the scan path control signal included in the scan path connection information 6 during the scan path operation, and the circuit configuration of the logic circuit with the scan path to be verified. Based on the logic circuit netlist 7 and the scan path control signal,
It has a function of creating a netlit of a clamped logic circuit clamped by a signal value for operating the scan path and outputting it as a clamped logic circuit netlist 9.

The logical expression conversion means 3 converts the scan path equivalent circuit, the scan path equivalent circuit netlist 8 which is a netlist of the clamped logic circuit, and the clamped logic circuit netlist 9 into a logic expression represented by Boolean algebra. If there is a redundant description in the logical expression, it has a function of deleting it and outputting it as an equivalent circuit logical expression 10 and a clamped logical circuit logical expression 11.

The logical expression comparing means 4 has a function of comparing the equivalent circuit logical expression 10 with the clamped logical circuit logical expression 11 and outputting the comparison result to the terminal device 12.

Next, the operation of this embodiment will be described.

Now, the contents of the scan path control signal information 5 and the scan path connection information 6 are as shown in FIGS. 2 and 3, respectively, and the scan path added logic circuit netlist 7 is the scan path added logic circuit of FIG. It is assumed that the circuit configuration is shown.

The scan path equivalent circuit creating means 1 includes the signal names SIN, SOUT, and CLK of the scan path input signal, the scan path output signal, and the scan path operation clock included in the scan path control signal information 5 of FIG. Figure 3
Connection order of the flip-flops on the scan path indicated by the scan path connection information 6 (1st: FF1, 2nd: F
F2) is input to create the logic circuit having only the scan path shown in FIG. 4, and the netlist thereof is output as the scanpath equivalent circuit netlist 8.

The control signal clamp means 2 has the signal name SFM of the scan path control signal included in the scan path control signal information 5 of FIG. 2 and the signal value ("1") of the scan path control signal SFM during the scan path operation. And the scan path control signal SFM is clamped to “1” to create the clamped logic circuit shown in FIG. 5, and the net list is used to clamp the logic circuit net. Output as list 9. In FIG. 5, VCC indicates a clamp terminal.

The logical expression converting means 3 first inputs the scan path equivalent circuit netlist 8 which is the net list of the scan path equivalent circuits of only the scan paths shown in FIG.
It is converted into a logical expression expressed by Boolean algebra and output as an equivalent circuit logical expression 10.

Next, the logical expression conversion means 3 inputs the clamped logic circuit netlist 9 which is the netlist of the clamped logic circuit shown in FIG. 5, converts it into a logic expression expressed in Boolean algebra, and further The redundant expression is deleted from the logical expression and output as the clamped logic circuit logical expression 11.

Here, the scan path control signal SFM, which is the control signal for the selectors SEL1 and SEL2, is clamped to "1", and the selectors SEL1 and SEL2 respectively have the scan path input signals SIN, which are input to the terminal a.
Since the output signal of the flip-flop FF1 is always selected, the description regarding the selectors SEL1 and SEL2 and the combinational circuits L1 and L2 is deleted from the logical expression as redundant description. Also, if the selector SEL
1, if the signals input to the terminals a and b of SEL2 are opposite to those in FIG. 5, that is, the terminals a and b of the selector SEL1
The output signal of the combinational circuit L1 and the scan path input signal SIN are supplied to the terminals b and b of the selectors SEL2.
If the output signal of the combinational circuit L2 and the output signal of the flip-flop FF1 are input to the selectors SEL1 and SEL2, the selectors SEL1 and SEL2 always select the output signals of the combinational circuits L1 and L2.
And the description regarding the scan path input signal SIN and the output signal of the flip-flop FF1 is deleted from the logical expression as redundant description.

The logical expression comparing means 4 compares the equivalent circuit logical expression 10 output from the logical expression converting means 3 with the clamped logical circuit logical expression 11 and outputs the comparison result to the terminal device 12.

In the case of this example, the equivalent circuit logical expression 10 is shown in FIG.
Shows the logic of the scan path equivalent circuit, and the clamped logic circuit logical expression 11 is the selector SEL1, SEL2 and the combinational circuits L1, L from the clamped logic circuit of FIG.
2 shows a logic in which the flip-flop FF1 is the scan path operation clock CLK.
According to the scan path input signal SIN, the flip-flop FF2 outputs the scan path operation clock CLK.
Since the logic for fetching the output signal of the flip-flop FF1 is shown in accordance with the above, the comparison result of the logical expression comparison means 4 becomes coincident, and that is displayed on the terminal device 12. This makes it possible to confirm that the connection order of the flip-flops FF1 and FF2 is correct and that the input signals of the flip-flops FF1 and FF2 during the scan path operation are correct.

On the other hand, in the case where the circuit configuration shown in the logic circuit netlist 7 with scan path is the order of the flip-flops FF1 and FF2 in FIG.
The logic indicated by the clamped logic circuit logical expression 11 is that the flip-flop FF2 takes in the scan-path input signal SIN according to the scan-path operation clock CLK, and the flip-flop FF1 takes in the output signal of the flip-flop FF2 according to the scan-path operation clock CLK. And the logic represented by the equivalent circuit logical expression 10 (logic in which the flip-flop FF1 takes in the scan-path input signal SIN according to the scan-path operation clock CLK and the flip-flop FF2 takes in the output signal of the flip-flop FF1 in accordance with the scan-path operation clock CLK). Since they are different from each other, the comparison result of the logical expression comparison means 4 becomes inconsistent, which is displayed on the terminal device 12.

Further, when the circuit configuration shown in the logic circuit netlist 7 with scan paths is a circuit configuration in which the signals input to the terminals a and b of the selector SEL1 in FIG. The logic indicated by 11 is that the flip-flop FF1 has the scan path operation clock CL.
Take in the output signal of the combinational circuit L1 according to K,
The flip-flop FF2 causes the scan path operation clock C
Since the output signal of the flip-flop FF1 is taken in according to LK, which is different from the logic shown by the equivalent circuit logical expression 10, the comparison result of the logical expression comparing means 4 becomes inconsistent, and this is displayed on the terminal device 12. To be done.

As described above, when the connection order of the flip-flops on the scan path or the input signal to the flip-flops is different from the one intended by the designer, the comparison result of the logical expression comparing means 4 does not match. Therefore, it is possible to recognize that the connection order of the flip-flops or the input signal to the flip-flops is incorrect.

[0037]

As described above, according to the present invention, the scan path equivalent circuit having only the scan path is created and verified based on the scan path connection information indicating the correct flip-flop connection order intended by the designer. Create a clamped logic circuit in which the scan path control signal is in the scan path operating state based on the logic circuit net list with scan path showing the circuit configuration of the target logic circuit with scan path, and compare the logical expressions of both. Therefore, even if the number of flip-flops forming the scan path is large, it is necessary to confirm in a short time whether the flip-flop connection order and the input signal to the flip-flops are correct. There is an effect that becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of contents of scan path control signal information 5.

FIG. 3 is a diagram showing an example of contents of scan path connection information 6.

FIG. 4 is a diagram showing an example of a scan path equivalent circuit.

FIG. 5 is a diagram showing an example of a clamped logic circuit.

FIG. 6 is a diagram showing an example of a logic circuit with a scan path to be verified.

FIG. 7 is a diagram showing a pattern set for each signal in the conventional technique.

FIG. 8 is a diagram showing expected values of respective signals in the conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Scan path equivalent circuit creation means 2 ... Control signal clamp means 3 ... Logical expression conversion means 4 ... Logical expression comparison means 5 ... Scan path control signal information 6 ... Scan path connection information 7 ... Scan path added logic circuit netlist 8 ... Scan campus equivalent circuit netlist 9 ... Clamped logic circuit netlist 10 ... Equivalent circuit logic formula 11 ... Clamped logic circuit logic formula 12 ... Terminal device

Claims (2)

[Claims] 1. A flip-flop in a connection order indicated by the scan path connection information based on scan path connection information indicating a correct connection order of flip-flops forming a scan path in a logic circuit with a scan path to be verified. A scanpath equivalent circuit netlist that is a netlist of scanpath equivalent circuits connected to each other, and based on the scanpath-equipped logic circuit netlist showing the circuit configuration of the scanpath-equipped logic circuit to be verified, the verification is performed. Create a clamped logic circuit netlist that is a netlist when the scan path control signal of the target logic circuit with the scan path is clamped to the signal value that operates the scan path, and the scan path equivalent circuit netlist and the Each clamped logic circuit netlist Scan path logic verification method characterized by converting the value circuits logical expression and the clamp already logic formulas, compared with the equivalent circuit logical expression and the clamp already logic formula. 2. A flip-flop in the connection order indicated by the scan path connection information based on the scan path connection information indicating the correct connection order of the flip-flops forming the scan path in the logic circuit with the scan path to be verified. Scan path equivalent circuit netlist, which is a netlist of scan path equivalent circuits connected to each other, and a scan path logical circuit net showing a circuit configuration of the scan path added logic circuit to be verified. A control signal clamp that creates a clamped logic circuit netlist that is a netlist when the scan path control signal of the logic circuit with the scan path to be verified is clamped to a signal value that operates the scan path based on the list. Means and the scan path equivalent circuit net And a clamped logic circuit netlist are converted into an equivalent circuit logic expression and a clamped logic circuit logic expression, respectively, and a logic expression comparison for comparing the equivalent circuit logic expression and the clamped logic circuit logic expression. And a scan path logic verification device.