JP2000241514A - Parallel generation method for test pattern and generation apparatus for test pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a generation apparatus for a parallel test pattern which is not different in every trial and which can always obtain the same result as a sequential processing operation. SOLUTION: A plurality of hypothetical failures 113 which are selected by a hypothetical-failure-list control part 102 in the list order of a hypothetical failure list 112 are distributed respectively to a plurality of test-pattern generation parts 103. A generated test patter is received by a failure-simulation-order decision part 104 as hypothetical-failure ad test-pattern information 114. The order decision part 104 selects test-pattern information 115 in the order of the failure list from the received information 114 so as to be output to a failure simulation part. All failures which can be detected by a test-pattern are found by a simulation. The test pattern which detects a new failure is output to a test-pattern series 117. In addition, detected failure information 116 is deleted, and the hypothetical failure list 112 is updated. In addition, also other hypothetical-failure and test-pattern information 114 which corresponds to the detected failure information 116 is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to test pattern generation for detecting a manufacturing defect of a logic circuit, and more particularly to a method and apparatus for generating test patterns in parallel.

[0002]

2. Description of the Related Art In a process of generating a test pattern for detecting a manufacturing defect of an LSI or the like, a test for detecting one fault selected from the list is provided when information on a logic circuit and a list of assumed faults for signal lines in the circuit are given. Generate a pattern. Next, a fault simulation is performed to find all hypothetical faults that can be detected by the generated test pattern. These detected hypothetical faults are removed from the hypothetical fault list, and the above processing is repeated for the remaining hypothetical faults.

As a method of generating test patterns in parallel by a plurality of processors in order to speed up the test pattern generation process, a paper by J. Wolf et al.
ultPartitioned Parallel Test Generation ''
TRANSACTIONS ONCOMPUTER-AIDED DESIGN OF INTEGRATE
D CIRCUITS AND SYSTEMS, VOL.15, NO.5, MAY 1996, p5
17-p534 "(this prior art is hereinafter referred to as a cited example).

In the cited example, a hypothetical fault list management program distributes a hypothetical fault to each processor, and each processor generates a test pattern for detecting the allocated hypothetical fault, and generates a hypothetical fault that can be detected by the test pattern. Find all by failure simulation. The hypothetical fault list management program sequentially receives the test pattern and the detected fault sent from each processor, leaves only the test pattern that detects a new hypothetical fault in the hypothetical fault list, and stores the hypothetical fault that the test pattern detects. The above is removed from the hypothetical fault list, the remaining hypothetical faults are distributed to each processor, and the above is repeated.

[0005]

The result of the parallel test pattern generation processing of the cited example described above often differs from the result of the sequential processing that always outputs the same result. In other words, even for the same generation algorithm and circuit data, test patterns output in parallel differ for each trial. The reason for this is
This is because, since the pattern processing time of each processor is different for each trial, the fault simulation order of a plurality of test patterns changes, and the hypothetical faults left by updating the hypothetical fault list management program list differ.

If the test pattern is different for each trial, there is a problem that performance evaluation becomes difficult. Even if a bad evaluation such as a large number of test patterns or a long test generation time is obtained in a certain trial, it is possible that a bad result is accidentally obtained in the trial. For this reason, correct performance evaluation cannot be performed unless the same input data is repeated many times.

[0007] More essentially, it becomes difficult to develop a parallel test generation program. Generally, a parallel processing program is often created by parallelizing a sequential processing program.
If the parallel processing program always obtains the same result as the original sequential processing program, the correctness of the program can be verified by comparing the results. However, if the results differ for each trial, it is not possible to verify the correctness of the program only by looking at the results.

Furthermore, the parallel processing of the cited example has a problem that the number of test patterns increases as compared with the sequential processing as described later. As the number of test patterns increases, the memory for storing them and the test time increase.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a method for generating a test pattern with high reliability while maintaining the high speed of parallel processing, always obtaining the same result every trial. It is to provide a device.

[0010]

In order to achieve the above object, the present invention assigns a plurality of hypothetical faults of a logic circuit to be tested to a plurality of processors, and each processor generates a test pattern for detecting each hypothetical fault. In a parallel test pattern generation method, a plurality of hypothetical faults are selected from a hypothetical fault list including all the hypothetical faults of the logic circuit and distributed to a plurality of processors, and each processor corresponds to the distributed hypothetical fault. The generated plurality of test patterns are rearranged according to a predetermined sequential processing order, and a failure simulation of each test pattern is performed in that order.
A test pattern in which a detected fault becomes new for each simulation is saved, and the detected fault is deleted and updated from the fault list. In addition,
The predetermined sequential processing order is, for example, an ascending order or a descending order of the failure list.

When a fault simulation is also performed in parallel, a plurality of hypothetical faults are selected from a hypothetical fault list including all the hypothetical faults of the logic circuit and distributed to a plurality of processors. Is passed to a plurality of other processors together with the hypothetical fault and the fault is simulated in parallel, and the detected faults of the simulation result are arranged in a predetermined sequential processing order along with the corresponding hypothetical fault and the test pattern, and the detected fault becomes new. The method is characterized in that only the test pattern is stored, and the detected fault is deleted from the hypothetical fault list and updated.

A test pattern generating apparatus for executing the method of the present invention includes a plurality of processors for generating test patterns for detecting a plurality of hypothetical faults of a logic circuit to be tested in parallel. Selecting a plurality of hypothetical faults from a hypothetical fault list including all hypothetical faults of the circuit and distributing them to the plurality of processors;
Assumed fault list management means for deleting the detected fault by the generated test pattern and updating the assumed fault list,
Fault simulation order determining means for receiving test patterns generated by the plurality of processors, rearranging the plurality of test patterns in accordance with a predetermined sequential processing order, and sequentially outputting the test patterns; And a failure simulation means for finding all the detected failures that can be detected.

Further, the fault simulation order determining means corresponds to a hypothetical fault included in the detected fault obtained by the fault simulation and discards an unoutputted test pattern.

As described above, the parallel test pattern generation device of the present invention provides a processing unit for making the result of each trial the same,
Specifically, when only the test pattern generation unit is parallelized, a failure simulation order determination unit is added. The failure simulation order determination unit stores the test patterns generated in parallel, selects a test pattern in a predetermined sequential processing order, and outputs the selected test pattern to the failure simulation unit.

As a result, the subsequent processing from the failure simulation unit is always the same, and the result for each trial is the same. If the generated test patterns are stored until they are no longer needed, the processing of generating the test patterns in parallel is not wasted, and the effect of speeding up by parallel processing is not impaired.

When both the test pattern generation unit and the failure simulation unit are parallelized, means for storing the output of the failure simulation unit in a predetermined sequential processing order is provided to determine a newly detected failure of the test pattern to be stored. The same operation and effect can be obtained by determining the update of the failure list in the predetermined sequential processing order.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a test pattern generation device according to the present invention will be described below in detail with reference to the drawings. First, a description will be given of a logic circuit and a hypothetical fault which are objects of the embodiment. FIG. 6 shows an example of a logic circuit,
This circuit uses ND gates G6 and G9, OR gates G7 and G8, input terminals G1 to G5, and output terminals G10 and G11.

FIG. 7 shows a data format of circuit information of the logic circuit of FIG. T11 is an element number, T12 is an element type, T
13 is an element number connected to the output side of the element, T14 is a signal line name connected to the output side of the element, T15 is an element number connected to the input side of the element, and T16 is connected to the input side of the element. This is the signal line name. Although the illustrated circuit information is based on elements, other forms may be used, such as based on signal lines as long as connections between elements can be represented.

FIG. 8 is a hypothetical fault list of the logic circuit of FIG. The hypothetical fault T21 is a fault that degenerates to a signal value of 0 (0 stuck-at fault) and a fault that degenerates to a signal value of 1 (1 stuck-at fault) for all signal lines. For example, a / 0 indicates a stuck-at-0 fault for the signal line a, and a / 1 indicates a stuck-at-1 fault for the signal line a.

The test pattern of the logic circuit is a pattern of a logical value given to the input terminals G1 to G5 in order to determine whether or not these hypothetical faults exist in each signal line. Hereinafter, the ability to determine whether or not there is a failure is referred to as being able to detect (failure). Also, a hypothetical failure may be simply referred to as a failure.

As a premise of the parallel processing of this embodiment, a sequential processing applied to the logic circuit of FIG. 6 will be described. FIG. 11 is an outline flow of the sequential processing of test pattern generation. S15
At 1, a / 0 at the head of the hypothetical fault list T21 is selected,
The fault value is given to the signal line. a / 0 indicates that the signal line a has the logical value 0
The logic value of the signal line a is 0
And In order to detect a failure, a pattern of an input terminal group having a different logic value of an output terminal may be obtained without a failure.

In S152, a value 1 different from the fault value 0 of the signal line a is set as a normal value, the value of the input terminal G1 is set to 1, and the following fault value propagation processing is performed. At this time, the normal value of the signal line a is 1 and the fault value is 0. Hereinafter, the normal value and the fault value of the signal line will be expressed as a normal value / fault value. In this example, the normal value / failure value of the signal line a is represented as 1/0.

The normal value / fault value of the signal line a is output to the output terminal G1.
Until the value of another signal line in the circuit is determined so as to be different from 0 (represented as 1/0), in S153, it is determined that the process is to be terminated, and the fault value propagation process in S152 is repeated. First,
Assume that the value of the signal line b is 1. Because the value of the signal line b is 0
In the case of, even if the value of the signal line a is either 1 or 0, the value of the signal line f becomes 0 and the normal value / fault value becomes 0/0 due to the AND operation rule, so that it cannot be distinguished. However, the signal line b
Is 1, the signal line f is 1/0, and the normal value / failure value can be distinguished. To set the signal line b to 1, the input terminal G2 is set to 1.

Similarly, the value of the signal line g is determined to be 0 according to the OR operation rule, and the signal line j is 1/0. Set signal line g to 0
, The signal line c and the input terminal G3 must also be 0. The value 1/0 of the signal line j is output to the output terminal G10 as it is.
The normal value / failure value differs at the output terminal. Here, the determination in S153 can be ended.

In S154, a value is assigned to an input terminal whose value has not been determined under predetermined conditions. G1, G2, and G3 are each 1, regardless of G4 and G5.
If it is 1, 0, a / 0 can be detected. Here, G4, G5
Are respectively 0,0. Thus, the test pattern for the failure information a / 0, that is, the input terminal groups G1, G2,
The logical value T32 of G3, G4, G5 is [1,1,0,0,
0].

Next, all hypothetical faults detected by this test pattern are obtained by fault simulation. FIG.
FIG. 2 shows a schematic processing flow of the failure simulation. First, in S161, the value of the output terminal for the test pattern T32 when there is no hypothetical fault is calculated. In the test pattern T32 of a / 0, G10 becomes 1 and G11 becomes 0 due to the AND and OR operation rules.

Next, in S162, one hypothetical fault is selected from the top of the hypothetical fault list T21, and a / 0 is selected first.
In S163, the signal line a is fixed to 0, and a normal operation is performed on the other signal lines to calculate the value of the output terminal group. In this case, G10 becomes 0 and G11 becomes 0, which is different from the normal case, so that a / 0 can be detected. Therefore, a / 0 is deleted from the assumed failure list in S165.

Next, returning to S162, a / 1 is selected from the assumed failure list. At the time of a / 1, the value of the signal line a is fixed to 1, and the other signal lines perform a normal operation. As a result, G10
Is 1 and G11 is 0, the same value as when normal, and a hypothetical failure
a / 1 cannot be detected. Therefore, it is left in the assumed failure list. This series of processing S162 to S165 is performed for all the hypothetical faults in the hypothetical fault list T21.

When the failure simulation processing is completed,
The test pattern generation processing is performed again. The test pattern generation process and the fault simulation process are repeated until a test pattern for detecting all the assumed faults is generated. As a result, a plurality of test patterns T32 for detecting all the faults in the hypothetical fault list in FIG. 8 and a hypothetical fault T33 for which each pattern can be detected are obtained.

FIG. 9 shows test pattern generation result information by sequential processing. The combination of the hypothetical fault T31 and the test pattern T32 (logical value of the input element group) is the hypothetical fault / test pattern information, and the hypothetical fault T33 to be detected is the detected fault information.

In the sequential processing of test pattern generation, 1
Assuming that the time for generating one test pattern is constant irrespective of a hypothetical fault and that this time is one time, the sequential processing can generate seven test patterns at seven times.

Hereinafter, an embodiment of a test pattern generation apparatus by parallel processing according to the present invention will be described. FIG. 1 is a configuration diagram of a parallel processing test pattern generation apparatus according to an embodiment. The parallel test pattern generation function 101 receives information from a circuit information storage unit 111 relating to elements and signal lines of a logic circuit and a hypothetical fault list 112 for the circuit, and performs a plurality of tests for detecting a hypothetical fault in the hypothetical fault list 112. The pattern is generated in parallel, and the result is output to the test pattern sequence storage unit 117. Note that the test pattern sequence is a set of test patterns input to the input terminal group of the logic circuit in order to detect all the hypothetical faults in the hypothetical fault list 112.

Here, the circuit information includes information on the type of each element in the logic circuit and the signal line connecting between the elements. The hypothetical fault list 112 lists faults assumed for each signal line of the circuit information. In the following description, the logic circuit to which this embodiment is applied is the same as that shown in FIG. 6, the circuit information is the same as that shown in FIG. 7, and the assumed failure list is the same as that shown in FIG.

The parallel test pattern generation function 101 includes a hypothetical fault list management unit 102 and a test pattern generation unit 1
03, a failure simulation order determination unit 104, and a failure simulation unit 105. Each of the hypothetical fault list management unit 102, the fault simulation order determination unit 104, and the fault simulation unit 105 may operate on the same processor or may operate separately on a plurality of processors. Assumed failure list management unit 1
02 and the fault simulation order determination unit 104 operate on the same processor, the hypothetical fault list 112 can use common data.

The test pattern generation unit 103 is composed of a plurality of processors operating in parallel,
The test pattern information 114 is output to the failure simulation order determination unit 104.

FIG. 2 is a flowchart showing a schematic operation of the test pattern generation apparatus. To simplify the explanation,
The operations of the assumed failure list management unit 102, the failure simulation order determination unit 104, and the failure simulation unit 105 are shown by one process by the same processor.
In this case, the test pattern information 115 and the detected failure information 116 in FIG. 1 do not need to be stored in a file or the like, and thus merely show the flow of information.

Steps S101 to S109 show the operations of the assumed failure list management unit 102, the failure simulation order determination unit 104, and the failure simulation unit 105.
Steps S301 to S305 show the operation of one processor of the plurality of test pattern generation units 103.

First, in steps S101 and S301, circuit information is input from the circuit information storage unit 111, and in step S102, all assumed faults are input from the assumed fault list 112 and stored as an internal fault list 112 '. In S103,
The generated test pattern for detecting a new hypothetical fault and the list of detectable faults are edited as shown in FIG. At this time, a hypothetical fault that can be detected by the generated test pattern is deleted from the internal fault list 112 '. When the process first passes the step of S103, the process proceeds to S104 without doing anything.

In step S104, it is determined whether the order of the test patterns for performing the failure simulation has been determined. If the order in which the necessary test patterns are arranged is determined, the process proceeds to step S107. If the order is not determined, the process proceeds to step S105. When the step of S104 is also passed for the first time, the process immediately proceeds to S105.
In S105, the hypothetical faults 113 are selected from the internal fault list 112 'in a predetermined order or an arbitrary order, and the test generation unit 10
Send to 3. The order of transmission to the plurality of test generators 103 is also arbitrary.

In S302 of the test generation unit 103, the process stands by until the hypothetical fault information 113 is sent, and when the hypothetical fault is received, the process proceeds to S303. In S303, a test pattern for detecting the received hypothetical fault 113 is generated based on the circuit information 111, and in step S304, the hypothetical fault / test pattern information 114 is output. The test pattern generation processing by one processor is the same as the sequential processing.

In step S305, if there is an end notification 118 from the hypothetical failure list management unit 102, the process ends.
Otherwise, the process returns to S302. Note that all test pattern generation units operating on each processor operate according to the same test pattern generation algorithm.

In the above description, the number of the assumed fault information 113 input in S302 is one for each processor, but a plurality may be provided. If multiple hypothetical faults are input at the same time,
The test pattern generation unit 103 repeats the processing of S303 and S304 by the number of hypothetical failures. Thereby, the pattern generation processing can be performed faster.

In S106, the test pattern generator 10
Assumed fault / test pattern information 11 sent from 3
4 is input, and it returns to S103. It should be noted that the test pattern generation processing time differs depending on the assumed failure, and may actually be 10 times or more. Test pattern generator 10
3 generates a test pattern and outputs it immediately. Therefore, the fault simulation order determining unit 104 does not always receive the assumed fault / test pattern information 114 in the order in which the assumed fault list management unit 101 transmitted in S105.

Failure simulation order determination unit 104
Determines the order of the test patterns for performing the failure simulation in S104, and performs the failure simulation on the selected test patterns in the determined order in S107. In this embodiment, the order of the simulation is determined so that the order is the same as that of the sequential processing as described later, and the same result as that of the sequential processing is obtained. This sequential processing order
Pre-configured or programmed.

In S108, when the generation of the test patterns for all the hypothetical faults is completed, an end notification 118 is output to the test pattern generation unit 103, and the process proceeds to S109. If not completed, the process returns to S103. In S109, S1
The test pattern sequence edited in step 03 is output, and the process is terminated.

Next, the detailed processing of each section will be described by applying it to the logic circuit of FIG. The test pattern generation unit 103
It is assumed that the predetermined order of the failure simulations follows the list order of the assumed failure list 112.

FIG. 3 shows a process S20 of the assumed failure list management unit.
1 to S205, FIG. 4 is a flowchart showing processes S401 to S407 of the failure simulation order determination unit, and FIG. 5 is a flowchart showing processes S501 to S507 of the failure simulation unit, respectively. Note that the processing S of the test pattern generation unit
Steps 301 to S305 are the same as those in FIG.

First, the parallel test pattern generation function 101
The processing of the initial input is performed in each of the components. That is, S20
In steps 1 and S401, the hypothetical fault list of FIG. 8 is input, in S301 the circuit information of FIG. 7 is input, and in S501, the circuit information and the hypothetical fault list are initially input. Here, only one internal fault list may be fetched from the hypothetical fault list 112.

Next, in S202, the internal failure list 11
Select a / 0, a / 1, b / 0 from the beginning of 2 'and assume hypothetical fault information 1
13, and distributed to the three test pattern generation units 103. At this time, the test pattern generation unit 103, the failure simulation order determination unit 104, and the failure simulation unit 105 are each on standby until there is input information from the previous stage.

Each of the test pattern generators 103
When a / 0, a / 1, and b / 0 are input as the hypothetical fault information 113 in 302, a test pattern for detecting the input hypothetical fault is generated in S303. The test pattern generation processing is the same as the sequential processing, and the fault value propagation processing (S
153) or the logical value setting of the input terminal (S154).

The test pattern T42 of the fault a / 0 is [1, 1, 0, 0, 0] for the input element numbers G1 to G5, and the same pattern as the sequential processing of FIG. 9 is generated. The test patterns a / 1 and b / 0 by the other generators 103 are also [0, 1, 0, 1, 1], [1, 1,
[0,0,0]. Next, in S304, as the assumed failure / test pattern information 114, T41 in FIG.
The set of T42 is output, and the process returns to S302.

FIG. 10 shows a test pattern / fault list which is the result information of the parallel processing of this embodiment. T41 indicates a hypothetical fault, T42 indicates a test pattern, and T43 indicates a hypothetical fault to be detected.

Failure simulation order determination unit 104
Is the assumed fault / test pattern information 114 in S402.
When (T41, T42) is received, it is rearranged and stored in S403 according to the failure order of the internal failure list 112 'in S403. Next, in S404, the assumed fault / test pattern information 114 of the assumed fault (a / 0 in this case) stored at the top is selected, and in S405, T42 for a / 0 is output as the test pattern information 115. .

The failure simulation unit 105 determines in S50
2, the test pattern of the hypothetical fault a / 0 [1,1,0,0,
0] is input, all of the faults T43 that can be detected by this pattern in S503 are a / 0, b / 0, f / 0, j / 0, k / 0.
Ask for. Note that T43 for the assumed failure information a / 0 is
This is the same as in the case of sequential processing.

Next, in S504, the assumed failure list management unit 102 and the failure simulation order determination unit 104 use T43 for T41 (a / 0) as the detected failure information 116.
And temporarily store the pattern of T42 for a / 0 as result information.

Next, in S505, the detected hypothetical fault T
43 is deleted from the internal failure list 112 '. Also, the test pattern information 115 generated by using one of the deleted hypothetical faults as the information 114 is discarded. Here, the end determination in S506 is based on the hypothetical fault a / generated by another processor.
Since the processing of the test pattern [0, 1, 0, 1, 1] corresponding to 1 remains, the process returns to S502. Note that the test pattern [1, 1, 0, 0, 0] corresponding to b / 0 has been discarded.

The hypothetical fault list management unit 102 and the fault simulation order determination unit 104 respectively execute S204 and S204.
At 406, the detected fault information 116 is input, and the common internal fault list 112 'is updated. In S407, the entirety of the failure list 112 is processed, and when the end notification is issued, the process ends, and otherwise, the process returns to S403.

In S403, the test pattern generator 10
Assumed fault / test pattern information 11 in order of acceptance from 3
4 is rearranged based on the internal failure list 112 '. At first, the assumed fault / test pattern information 114 is arranged in the order of the initial fault list, in the order of a / 0, a / 1, b / 0. When the fault simulation is executed, the hypothetical fault b / 0 is also detected in the first test pattern of a / 0.
Test pattern information (T41, T42) becomes unnecessary,
delete. On the other hand, since a / 1 has not been detected, the assumed fault / test pattern information 114 is retained.

In S404, the editing of the assumed fault / test pattern information 114 is completed, and it is determined whether the order of the fault simulation can be determined. If NO, the flow returns to S402.
That is, the test pattern generation unit 1 is provided for each parallel processing.
It is determined whether editing has been completed for all inputs from 03 (at first, a / 0, a / 1, b / 0). If the order can be determined, S4
In step 05, the test pattern T42 is selected and output in order from the top of the assumed fault / test pattern information 114.

In the above description, the assumed failure list management unit 1
02 until all of the test patterns of the hypothetical faults transmitted at a time have been received.
Does not proceed to S405 for outputting a test pattern. However, when a test pattern to be simulated next is received according to the order of the failure list, for example, if a test pattern of a / 0 is received, even if other test patterns of a / 1 and b / 0 are not received, S405 is performed. To perform a failure simulation.

As described above, in the present embodiment, the fault simulation order determining unit 104 selects the test patterns in the same order as in the sequential processing, and
15, the result of the failure simulation is the same as that of the sequential processing.

When the parallel processing of the test patterns for the hypothetical faults a / 0, a / 1, and b / 0 ends, the hypothetical faults b / 1, c /
The parallel processing for 0, d / 0 is repeated. When a fault simulation is performed on the fault b / 1 using the test pattern T42 according to the order of the hypothetical fault list, the detected hypothetical fault T43 is obtained as T43 in FIG. As a result, the test pattern of the fault d / 0 is deleted, so that a fault simulation of the test pattern of c / 0 is performed next.

Similarly, when the test pattern T42 of the hypothetical faults d / 1, e / 1, and i / 1 is generated, the hypothetical fault T43 detected by the test pattern of d / 1 is obtained. The i / 1 test pattern is deleted. Finally, a test pattern T42 of e / 0, g / 0 is generated, and a hypothetical fault T43 to be detected is obtained. When all of the hypothetical faults are detected, the hypothetical fault list management unit 102 satisfies the termination condition of S205, so the test pattern generation unit 103, the fault simulation order determination unit 104, and the fault simulation unit 105
Issue an end notice 118 to the user.

As described above, the final test pattern sequence generated for the logic circuit of FIG.
Among them, the test patterns for a / 0, a / 1, b / 1, c / 0, d / 1, e / 0, and g / 0 are the same as the results of the sequential processing in FIG. As described above, the parallel test pattern generation device according to the present embodiment can always obtain the same test pattern sequence as the result of the successive processing under the same circuit data because the test pattern sequence output as a result is always the same. In other words, unlike conventional parallel processing, there is no difference between trials,
The performance of the test pattern generation processing program can be evaluated by the result of one trial, thereby facilitating program development.

Further, the generation processing can be sped up as compared with the sequential processing. Incidentally, the three test pattern generators 103
Are all constant and one time. At this time, the parallel test pattern generation function 101 of the present embodiment generates a pattern for a / 0, a / 1, and b / 0 for one time, and generates a pattern for b / 1, c / 0, and d / 0 for one time. , D /
Pattern generation for 1, e / 1, i / 1 is performed at one time, e / 0, g / 0
Is generated at one time. That is, seven test patterns can be generated at four times, and the effect of the parallel processing is more remarkable than at seven times in the case of sequential processing.

In the present invention, the order in which the hypothetical faults are selected is the order of the hypothetical fault list, but the present invention is not limited to this. This order may be an arbitrary order determined in advance, and if the order is followed, no different result is obtained for each trial, and the same result as in the sequential processing can be obtained.

Here, for comparison with the present embodiment, the method of the cited example which is a conventional parallel test pattern generation process is described as follows.
A result applied to the logic circuit of FIG. 6 will be described. In the cited example, the number of test pattern generation units and the number of failure simulation units are the same, and each is three. The test pattern generation processing and the failure simulation processing are the same as those in the sequential processing, but have a hypothetical failure list management program as described above.

First, three hypothetical faults a / 0, a / 1, and b / 1 are selected from the hypothetical fault list T21 in FIG. 8, and a test pattern T42 for detecting these and a hypothetical fault T43 for the test pattern to be detected. It is obtained as shown in FIG.

It is assumed that the detected failure information T43 is received in the order of a / 0, a / 1, b / 0 by the management program of the assumed failure list. In the parallel test pattern generation processing of the cited example, the hypothetical fault list is updated in the order in which the detected faults are received. At this time, a / 0 and a / 1 are in the hypothetical fault list,
Since a hypothetical fault is newly detected, the test pattern is a final result. However, since the test pattern of b / 0 is the same as the test pattern of a / 0, it is discarded.

Next, test patterns T of b / 1, c / 0, d / 0
42 and a hypothetical fault T43 detected by the test pattern,
It is assumed that each is obtained as shown in FIG. The detected fault information T43 is a program for managing a hypothetical fault list,
When received in the order of b / 1, c / 0, d / 0, the test pattern of b / 1, c / 0 becomes the test pattern as the final result. Similarly, the test pattern of d / 0 is a test pattern as a final result because a hypothetical fault of j / 0 and g / 0 is newly detected. However, the test pattern of d / 0 does not exist in the test pattern sequence of FIG. 9 which is the result of the sequential processing.

Thereafter, test patterns T42 of d / 1, e / 1, i / 1 are generated, and the final result is the test pattern of d / 1. Further, test patterns e / 0 and g / 0 are generated, and these are also test patterns as final results.

As described above, the test patterns remaining as final results are eight test patterns for a / 0, a / 1, b / 1, c / 0, d / 0, d / 1, e / 0, and g / 0. And one more than the result of the sequential processing. Thus, the method of the cited example does not always match the result of the sequential processing.

Next, another trial based on the cited example will be described.
Here, when the test patterns b / 1, c / 0, and d / 0 are generated, information on the hypothetical faults detected by these test patterns is stored in a program that manages the hypothetical fault list in b / 1, d / 0.
It is assumed that the data is received in the order of 0 and c / 0. The test patterns b / 1 and d / 0 newly detect a hypothetical fault, and thus become test patterns as final results. However, since all the hypothetical faults detected by the test pattern of c / 0 are detected by the test pattern of d / 0, the test pattern of c / 0 does not become the test pattern as the final result.

As described above, in the method of J. Wolf et al. In the cited example, if the failure simulation order of the test patterns differs for each trial, the test patterns of the final result differ.
In general, when a test pattern is generated on a plurality of processors, the time for generating the test pattern changes for each trial, and therefore the order in which results are returned to a program that manages a hypothetical fault list also differs. Therefore, in the conventional parallel processing, there is a problem that a test pattern sequence as a result differs for each trial.

On the other hand, in the parallel test pattern generation processing of the present embodiment, a different result does not occur for each trial. Further, since the same result as in the sequential processing is obtained, the processing efficiency can be improved.

In the above embodiment, the failure simulation processing is performed on one processor. However, the failure simulation processing can be performed in parallel by a plurality of processors. That is,
The hypothetical fault selected from the fault list is distributed to a plurality of processors to generate test patterns in parallel, and the test patterns generated by each processor are subjected to fault simulation in parallel to obtain faults detected by each pattern. It is stored as detected failure / test pattern information.
Then, only test patterns for detecting a new fault in the order of the fault list are set as result information, and faults detectable by these test patterns are deleted from the assumed fault list.

[0077]

According to the parallel processing of test pattern generation according to the present invention, fault simulation is performed on test patterns generated in parallel in a predetermined order, for example, in the order of a fault list. , The same result information as in the sequential processing can be obtained. For this reason, the performance evaluation of the test pattern can be performed from one trial result, and there is an effect that the processing can be speeded up and the reliability can be improved.

Further, since the parallel processing program can be verified by comparison with the sequential processing, the development of the test pattern generation device is facilitated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a parallel test pattern generation device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure of test pattern parallel generation according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a processing procedure of a hypothetical failure list management unit according to one embodiment.

FIG. 4 is a flowchart showing a processing procedure of a fault simulation order determination unit according to one embodiment.

FIG. 5 is a flowchart showing a processing procedure of a failure simulation unit according to one embodiment.

FIG. 6 is an explanatory diagram illustrating an example of a logic circuit to which the present invention is applied.

FIG. 7 is an explanatory diagram showing circuit information of the logic circuit in FIG. 6;

FIG. 8 is an explanatory diagram showing a hypothetical fault list of the logic circuit shown in FIG. 6;

FIG. 9 is an explanatory diagram showing test pattern generation result information by sequential processing.

FIG. 10 is an explanatory diagram showing test pattern generation result information by parallel processing of the present invention.

FIG. 11 is a flowchart showing a processing procedure of test pattern generation by sequential processing.

FIG. 12 is a flowchart showing a processing procedure of a failure simulation.

[Explanation of symbols]

101: Parallel test pattern generation function, 102: Assumed fault list management unit, 103: Test pattern generation unit, 10
4 ... Fault simulation order determination unit, 105 ... Fault simulation unit, 111 ... Circuit information, 112 ... Assumed fault list, 113 ... Assumed fault information, 114 ... Assumed fault information / test pattern information, 115 ... Test pattern information, 116 ... Detection Failure information 117: Test pattern sequence.

Claims (5)

[Claims] 1. A parallel test pattern generation method in which a plurality of hypothetical faults of a logic circuit to be tested are assigned to a plurality of processors, and each processor generates a test pattern for detecting each hypothetical fault. A plurality of hypothetical faults are selected from a hypothetical fault list including all hypothetical faults and distributed to a plurality of processors, and a plurality of test patterns generated by each processor corresponding to the distributed hypothetical faults are determined according to a predetermined sequential processing order. Rearranging, performing a fault simulation of each test pattern in that order, storing a test pattern in which a detected fault becomes new for each simulation, and deleting and updating the detected fault from the fault list. How to generate test patterns in parallel. 2. A parallel test pattern generation method in which a plurality of hypothetical faults of a logic circuit to be tested are allocated to a plurality of processors, and each processor generates a test pattern for detecting each hypothetical fault, A plurality of hypothetical faults are selected from a hypothetical fault list including all hypothetical faults and distributed to a plurality of processors, and a plurality of test patterns generated in parallel by each processor are passed to a plurality of other processors along with the hypothetical faults in parallel. The fault simulation is performed, and the detected faults of the simulation result are arranged in a predetermined sequential processing order along with the corresponding hypothetical faults and test patterns, and only the test patterns in which the detected faults are new are stored. Parallel production of test patterns characterized by deletion and update Method. 3. The parallel test pattern generation method according to claim 1, wherein the sequential processing order is an ascending order or a descending order of the hypothetical fault list. 4. A test pattern generation apparatus comprising: a plurality of processors for generating test patterns for detecting a plurality of hypothetical faults of a logic circuit to be tested in parallel, the hypothetical fault including all the hypothetical faults of the logic circuit A plurality of hypothetical faults selected from the list and distributed to the plurality of processors, a hypothetical fault list management unit for updating the hypothetical fault list by deleting detected faults based on the generated test pattern, and a plurality of hypothetical faults generated by the plurality of processors; The received test patterns are received, a plurality of test patterns are rearranged in accordance with a predetermined sequential processing order, and thereafter, a failure simulation order determining unit that sequentially outputs the test patterns, and all the test patterns that can be detected for each test pattern input from the order determining unit. A failure simulation means for determining the detected failure is provided; Test pattern generation apparatus for. 5. The fault simulation order determination unit according to claim 4, wherein the fault simulation order determination unit corresponds to a hypothetical fault included in the detected fault obtained by the fault simulation and discards a test pattern that has not been output. Test pattern generation device.