JPH11265980A - Failure verification method of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a wasteful processing time so as to effectively carry out a failure verification, by a method wherein verification target points of a circuit are ranked depending on a signal transition ratio at the points, and the points are successively verified in due order depending on the ranking. SOLUTION: Before failure verification is carried out, signal transition verification 102 is carried out using a net list 100 and a test pattern 1 (101). Data obtained through signal transition verification are written into a transition database 108. Furthermore, when a test pattern 2 (103) is given, a signal transition verification 104 is carried out again, and obtained data are written in the database 108. Then, the transition database 108 is subjected to a database analysis 109, and the transition ratio at each node in each test pattern is guided. As mentioned above, a signal transition verification 104 is carried out, whereby a test pattern can be preferentially processed, a target failure can be quickly verified, a wasteful processing can be eliminated, and a processing time can be much shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an efficient method for verifying a failure of an integrated circuit.

[0002]

2. Description of the Related Art In a manufacturing process of an integrated circuit, for example, if fine foreign matter adheres to a mask, a defect such as a pattern bridge may occur at the adhered portion. Such a defect is generally detected by examining an input / output signal using a predetermined test pattern in an integrated circuit inspection process.

However, in advanced integrated circuits, the number of test patterns to be executed is also limited due to the limitation of the inspection time corresponding to the cost. Therefore, it is important how to efficiently detect a failure (hereinafter referred to as a failure) of an integrated circuit in a short time. Therefore, it is necessary to evaluate the probability of detecting a failure of the integrated circuit with a certain test pattern, that is, to evaluate the failure detection rate. In the present invention, such evaluation of the fault detection rate is referred to as fault verification.

As a specific method, as shown in FIG. 16, a net list 700 and a test pattern 701 are inputted to an inspection machine or a failure detector 702, and a failure state is artificially created in advance in an integrated circuit, and It is checked whether or not a failure is normally detected (failure simulation).
3 is output. Further, as a technology based on a failure simulation, an automatic test pattern generation device (A) that automatically generates a test pattern based on information such as a circuit diagram.
TPG) is also well known.

[0005] In other words, a test pattern with a high failure detection rate is a test pattern that facilitates control of the circuit, and transmits the state of a signal to a portion to be verified of the circuit to an output terminal and can be observed. One of the techniques for confirming the ease of circuit control is signal transition confirmation verification (toggle check). This is based on whether the state of the signal with respect to the portion to be verified of the circuit is H level or L level at a certain time,
It also checks whether the signal has changed or the like, and can perform processing at a processing speed comparable to that of logic verification and at a considerably higher speed than failure verification.

On the other hand, conventionally, a distributed fault verification method has been used as a method for performing fault verification at high speed. In this method, all faults are divided into multiple faults, multiple fault sets are subjected to fault verification in parallel using multiple fault detectors, and the fault detection results are combined to obtain the overall fault detection rate. calculate.

[0007]

The verification time for detecting each fault in the fault verification is not uniform, but greatly varies depending on the ease with which the fault is detected and the amount of events generated during the verification. In fault verification, it is more effective to process test patterns that are likely to be detected or faults that are likely to be detected first, and to process faults that require processing time due to the occurrence of events, etc.
In the conventional failure verification, the order of processing is not considered.

Specifically, pins of flip-flops on a scan line in scan design, pins related to a system clock, a set, a reset, and control pins of a tri-state cell that generates an undefined state are set there. The fault affects a wide area of the circuit, and there is a possibility that a larger number of events will occur during verification than a fault set in a normal verification target location. In the present invention, such a failure is called a hyper failure. If the amount of events that occur during verification increases, the processing time decreases due to the burden on the hardware of the fault detector.However, conventional fault verification requires measures before processing the fault that increases the amount of events. Not done.

On the other hand, in distributed fault verification, all possible faults are processed in parallel by a plurality of fault detectors, so that the entire fault verification time is limited by the slowest processing among the parallel fault verifications. . Distributed fault verification is most effective when the processing times of distributed fault verification are the same. In other words, in the distributed fault verification, the effect is significantly reduced when a fault requiring a long time for verification is biased toward a set of distributed faults.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned conventional problems and to provide a method for verifying the failure of an integrated circuit which can effectively perform the failure verification while eliminating unnecessary processing time. .

[0011]

According to a first aspect of the present invention, there is provided a method for verifying a failure of an integrated circuit, comprising: verifying a transition of a signal to a portion to be verified of a circuit; , And verification is performed in the order based on the ranking.

According to the method for verifying the failure of an integrated circuit according to the first aspect, in order to know the easiness of failure detection for all possible failures, signal transition confirmation verification is performed before normal failure verification. The test patterns or verification target locations for performing the fault verification are ranked according to the signal transition ratio, and the verification is performed in order based on the ranking, so that useless test patterns are flown or unnecessary fault verification is performed. Without performing the above, it is possible to effectively perform the failure verification without using unnecessary processing time.

According to a second aspect of the present invention, there is provided a method for verifying an integrated circuit failure, wherein a signal transition confirmation verification is performed for a portion to be verified of a circuit, and a verification test pattern or a portion to be verified is ranked according to a signal transition ratio. The present invention is characterized in that the verification target portions are equally divided so that the transition ratio is equal, the respective portions are processed in parallel, and the processes are performed based on the ranking in each process.

According to the method for verifying the failure of an integrated circuit according to the second aspect of the present invention, the portions to be verified are equally divided so that the signal transition ratios become equal, and finally the entire failure detection rate is calculated. Since the processing time of the parallel processing in the distributed fault verification can be equalized, effective distributed fault verification can be performed. According to a third aspect of the present invention, there is provided an integrated circuit failure verification method, wherein, among the verification target portions of the circuit, the verification target portions are ranked according to an event amount generated at the time of verification.
The feature is that verification is performed in order based on the ranking.

According to the method for verifying the failure of an integrated circuit according to the third aspect, an event that is empirically known is generated among all possible faults in order to consider in advance the amount of events that occur at the time of verification. The ranking is made in consideration of the easy hyper failure, and the verification is performed in order based on the ranking. In this way, prior to normal failure verification, by considering the hyper-failure that is likely to cause an event at the time of verification and ranking the test patterns for performing the failure verification or the failures to be verified, a useless test pattern can be flown, Failure verification can be performed effectively without performing unnecessary failure verification.

According to a fourth aspect of the present invention, there is provided a method of verifying an integrated circuit failure, wherein, among the verification target portions of the circuit, the verification target portions are ranked in accordance with the amount of events generated at the time of verification, and a hyper is easily generated during the verification. The present invention is characterized in that the verification target portions are equally divided so that the failures are equal, the respective portions are processed in parallel, and the processes are performed based on the ranking in each process.

According to the fourth aspect of the present invention, the processing time of the parallel processing in the distributed fault verification is reduced by equally dividing the hyper fault and finally calculating the entire fault detection rate. It is possible to make them even and effective distributed fault verification can be performed. An integrated circuit failure verification method according to claim 5, wherein a hyper-failure that easily causes an event at the time of verification is taken into consideration in a verification target portion of the circuit, and a signal transition confirmation verification for the verification target portion of the circuit is performed. It is characterized in that the verification test patterns and the verification target portions are ranked according to the signal transition ratio, and the verification is performed in the order based on the ranking.

According to the method for verifying the failure of an integrated circuit according to the fifth aspect, of all possible failures, a hyper-failure which is likely to cause an event which is empirically known is considered, and the failure is easily detected. As a confirmation of the above, signal transition confirmation verification is performed, the verification test pattern or the verification target portion is ranked according to the signal transition ratio, and the verification is sequentially performed based on the ranking. In other words, signal transition verification is performed before fault verification, and the order of fault verification is determined by considering the amount of events that occur during verification.
This has the same effect as the first aspect.

According to a sixth aspect of the present invention, there is provided a method of verifying an integrated circuit failure, wherein a hyper-failure which is likely to generate an event at the time of verification is taken into consideration in a portion to be verified of a circuit, and a signal transition confirmation verification to a portion to be verified of the circuit is performed. The verification test patterns and the verification target locations are ranked according to the signal transition ratio, and the verification target portions are equally divided so that the ratios of the hyper-failure and the signal transition are equal, and each is processed in parallel. In each of the processes, the process is performed based on the ranking.

According to the fault verification method for an integrated circuit according to the present invention, the target portion to be verified is equally divided as the distributed fault verification so that the signal transition ratio becomes equal, and finally the entire fault detection rate is calculated. Therefore, there is an effect similar to that of the second aspect.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment
The embodiment will be described with reference to FIGS. Conventionally, a fault is set in a circuit and fault verification is performed by inputting a netlist and a test pattern to a fault verification device, but the processing order of the target fault is not considered. According to the present invention, first, the net list 105 is taken into the failure detector 106, and the failure list 107 is generated in the preprocessing of the failure verification. The basic data of the transition information database is generated from the failure list 107.

The transition database has the format shown in FIG. 2, in which information on a verification target part (failure node name) and an equivalent failure are written. Further, after a test pattern is passed and signal transition verification is performed, the number of transitions of the signal levels H, L, Z (high impedance), and X (undefined) occurred in each failure is written. Finally, a failure verification is performed, and information on which test pattern was detected is written.

As shown in FIG. 1, before the fault verification, a signal transition verification 102 is performed using the netlist 100 and the test pattern 1 (101). The data obtained by the signal transition verification 102 is written in the transition information database 108 described above. If the test pattern 2 has the test pattern 2 (103), the signal transition verification 104 is performed again, and the result is written into the transition information database 108. Next, by performing a database analysis 109 for analyzing the transition information database 108, a transition ratio of each node in each test pattern is derived.

The specific contents of the database analysis 108 are as follows. First, a representative fault is selected from all faults in consideration of an equivalent fault to be verified. This representative failure may be any equivalent failure. Next, which test pattern is processed first is selected. The selection is performed based on the number of toggling faults and the number of toggling. FIG. 3 shows an example. Test pattern 1 (101) and test pattern 2 (10
If there is 3), the number of toggle faults is test pattern 1
(101), test pattern 2 (103) is larger in the order, test pattern 1> test pattern 2, and processing is performed in the larger order. When the number of toggle faults is the same, the process is preferentially performed in descending order of the total number of toggles of all representative faults, for example, if test pattern 1> test pattern 2, When the selection of the test pattern is completed, the failure list 1 (110) is generated in consideration of the processing order so that the higher the ratio of the transition, the earlier the failure verification is performed. FIG. 4 shows an example, in which the number of toggles is in the order of failures 1 and 2, and the failure list is generated in this order.

In this example, two test patterns 1 (1
01) and the test pattern 2 (103), but the test pattern 1 (101) has a higher transition rate, and this pattern is processed preferentially. The netlist 100, the test pattern 1 (101) and the fault list 1 (110) are input to the fault detector 111, and fault verification is performed. The result of the failure verification is written into the transition information database 108 again by the detection information writing 112.

The database analysis 113 is performed again, and the fault list 2 (114) is generated from the transition ratio of the undetected fault in the test pattern 1 (101). The fault list 2 (114), the test pattern 2 (103), and the netlist 100 are input to the fault detector 115, and fault verification is performed. In this example, two test patterns are used, but when verifying a plurality of test patterns, the same processing is repeated. For a fault that does not make any transition in the signal transition verification 104, no fault verification is performed. Conventionally, an undetected fault has been found to be undetected after a long period of fault verification. However, this method can be performed without performing unnecessary fault verification. In addition, by performing the signal transition verification 104, an effective test pattern can be preferentially processed, and a target failure that contributes to an improvement in the detection rate can be quickly verified, so that unnecessary processing can be omitted and processing time can be reduced. A great effect can be obtained in shortening the time.

A second embodiment according to the present invention will be described with reference to FIGS. Claim 2
The invention described in (1) is a case where the invention described in claim 1 is applied to distributed fault verification. FIG. 5 shows an example of a fault verification using two test patterns as in FIG. 1, and shows a method after the fault list 1 (110) in FIG. A fault division 502 for allocating a fault to be processed is performed on the fault list 1 (110) in FIG. 5 so that the signal transition ratios are substantially the same.
FIG. 6 shows a method of fault division. The failure list 600 (110) arranged in descending order of the number of signal transitions is divided into division lists 601 and 602. In FIG. 5, a fault is divided by this method, and a fault list 1A (503) and a fault list 1B (504) are generated. Two failure detectors 50
7 and 508 respectively show the failure list 1A and the failure list 1B.
And the netlist 100 and the test pattern 1 (101) are input to perform fault verification. The two fault verifications are performed in parallel at the same time. In each process, the processes are performed based on the ranking, and when all the processes are completed, the results are totaled 509 to calculate the entire fault detection rate. The time for the entire fault verification is tied to the later of the two fault verifications.
If the target faults that require processing time are offset, the effect of the distributed fault verification is significantly reduced. However, in the present invention, the faults to be processed are sorted so that the signal transitions are almost the same by performing the signal transition verification in advance, so that the two fault verification times become almost the same, and the maximum effect in the distributed fault verification is obtained. can get.

Subsequently, a database analysis 113 is performed, and a failure list 2
(114) is generated. The fault division 512 for allocating the target fault from the signal transition ratio is performed, and the fault list 2A (5
13), and generates a failure list 2B (514). These lists, netlist 100, and test pattern 2 (1
03) are input to the two fault detectors 516 and 517, respectively, and parallel fault verification is performed.

In this example, two test patterns are used. However, when a plurality of test patterns are verified, the same processing is repeated. Claim 3 of the present invention
A third embodiment corresponding to FIG. 7 will be described with reference to FIGS. Conventionally, a fault is set in a circuit in a pseudo manner by inputting a netlist and a test pattern to a fault verification device, and fault verification is performed. However, the processing order of the target fault is not considered. According to the present invention, a hyper fault and a fault that is likely to become a hyper fault are specified from the netlist, and the processing order of the fault verification is performed.

In FIG. 7, first, a net list 105 is taken into a failure detector 106, and a failure list 107 is generated in a pre-process for failure verification. Further, by considering the equivalent fault information 103 in the fault dictionary generated by the preprocessing of the fault verification and the library 122 used to create the netlist, the fault list 107 is listed in the order in which the fault verification is actually performed. Rearrangement 121 is performed. The contents of the rearrangement 121 of the specific list are as follows. First, a representative fault is selected from all the faults in consideration of an equivalent fault to be verified. This representative failure may be any equivalent failure. Next, a hyper failure and a failure having a high possibility of becoming a hyper failure are specified and ordered. Here, the definition of the hyper failure is as shown in FIG. That is, a hyper failure is a terminal of a cell on a scan line when scan design is performed. Further, there are control terminals of the tri-state cell, clock terminals of flip-flops other than scan cells, and set and reset terminals as possible failures that may become hyper failures. The order of the failure verification is after the hyper failure. Also, for the same hyper failure, the more equivalent failures, the higher the possibility of event occurrence, and the order of failure verification is delayed. The failure list 123 is generated by rearranging the above list. Failure list 12
9 is shown in FIG. As the processing order, if it is largely determined, a failure (failure 1, 2, 3,
4), a failure (failure h
a, hb, hc, hd), hyper failure (failure he, h
f, hg). Within the same group, the processing order becomes slower as the number of equivalent faults increases. For example,
In the faults 1, 2, 3, and 4, when there are many faults sequentially, the fault 4> the fault 3> the fault 2> the fault 1 is satisfied, and the fault 4 having the largest equivalent fault is processed later. Regarding the hyper-failure, the event amount generated by the foremost failure hg existing on the same line is larger depending on the context on the scan line (failure hg → fault hf → fault he).
To be processed later. The generated fault list 123, net list 105, and test pattern 1 (101) are taken into the fault detector 111, and fault verification is performed. For a hyper failure and a failure that may become a hyper failure, it is easy to confirm an operation failure by logic verification, and it is also possible not to perform failure verification. (The underline above was added corresponding to the figure, but please consider.) Conventionally, hyper failures are recognized during failure verification and removed from the failure verification target list, or it takes a long time Although the failure has been verified, as shown in the present invention, by considering the hyper failure before performing the failure verification, it is possible to omit useless processing and perform an effective failure verification.

A fourth embodiment according to the fourth aspect of the present invention will be described with reference to FIGS. That is, the fourth embodiment is a case where the third embodiment is applied to distributed fault verification. FIG. 10 shows a method after creation of the failure list 123 of the failure detector 108 in FIG. In FIG. 10, the failure list 123 is divided into the failure divisions 401.
Divide by. FIG. 11 shows a method of dividing the failure list 123 exemplified in FIG. Reference numerals 502 and 503 denote divided lists. When splitting, the faults to be processed are allocated so that the ratio of hyper faults is almost the same, and in each of the allocated fault sets, the processing order is considered so that the processing order of hyper faults is delayed Then, a failure list 1A (402) and a failure list 1B (403) are generated based on the ranking in FIG. Two failure detectors 40
6 and 407, the fault list 1A (402), the fault list 1B (403), the net list 100, and the test pattern 101 are input to perform fault verification. The two fault verifications are performed in parallel at the same time, and when all the processes are completed, the results are totaled 408 to calculate the overall fault detection rate. The time for the entire fault verification is tied to the later of the two fault verifications. If the target faults that require processing time are offset, the effect of the distributed fault verification is significantly reduced.
However, according to the present invention, processing faults are determined in advance so that hyper faults that take a long processing time and greatly affect the entire fault verification time can be sorted so that the hyper faults become almost the same, and the number of equivalent faults is reduced. By taking into account the division in consideration of the above, the two fault verification times become almost the same, and the maximum effect is obtained in the distributed fault verification.

A fifth embodiment according to the fifth aspect of the present invention will be described with reference to FIGS. Conventionally,
By inputting the netlist and the test pattern to the fault verification device, faults are set in the circuit and fault verification is performed, but the processing order of the target fault is not considered. According to the present invention, first, a hyper failure and a failure that is likely to become a hyper failure are specified from a net list.
Here, the definition of the hyper failure is the same as that shown in FIG. 8 of the third embodiment. That is, a hyper failure is a terminal of a cell on a scan line when scan design is performed. In addition, the control terminal of the tri-state cell, the clock terminal of the flip-flop other than the scan cell, the set terminal, and the reset terminal are possible failures that may cause a hyper failure. The order of the failure verification is after the hyper failure. Also, for the same hyper failure, the more equivalent failures, the higher the possibility of event occurrence, and the order of failure verification is delayed. In FIG. 12, first, the netlist 100 is taken into the failure detector 106, and a failure list 107 is generated in preprocessing for failure verification. Further, taking into account the library 140 used to create the netlist 100, hyper failures and failures having a high possibility of becoming hyper failures are specified (141), ordered, and the basic data of the transition information database 142 is determined. Generate.

Before the failure verification, the netlist 100
Transition verification 1 by using and test pattern 1 (101)
02 is performed. The data obtained by the signal transition verification 102 is written in the transition information database 142 described above. FIG. 13 shows the format of the transition information database. The transition information database includes a portion to be verified (node name), a test pattern name, transition information, equivalent information indicating an equivalent failure, failure detection information on whether the target node has been detected, and information on whether a hyper failure has occurred. In the transition information, the number of times the transition state of the signals 1, 0, Z (high impedance), and X (undefined) has occurred in each failure is written after the test pattern is flown and the signal transition is verified.
If the test pattern 2 has the test pattern 2 (103), the signal transition is verified again (104) and written into the transition information database 142. Next, the transition information database 142 is analyzed (144). Specific database analysis 144
First, a representative fault is selected from all the faults in consideration of an equivalent fault to be subjected to fault verification. This representative failure may be any equivalent failure. Next, the ordering is performed for the hyper failure and the failure that is likely to become the hyper failure. Next, which test pattern is processed first is selected. The selection is performed based on the number of toggling faults and the number of toggling. One example is similar to FIG. Test pattern 1 (101), test pattern 2 (103)
If there is, the number of toggle faults is in the order of test pattern 1 and test pattern 2, and processing is performed in this order. When the number of toggle faults is the same, the processing is preferentially performed in descending order of the total number of toggles of all representative faults. When the selection of the test pattern is completed, the failure list 1 (145) is generated in consideration of the processing order so that the higher the rate of transition is, the earlier the failure verification is performed. FIG. 14 shows an example of the failure list. The processing order is as follows: failures that do not relate to a hyper failure (failures 1, 2, 3, 4), failures that may become hyper failures (failures ha, hb, hc, hd), and hyper failures (failure he , Hf, hg). For a fault that may become a hyper fault, the processing order becomes slower as the number of equivalent faults increases. For example, failure hb, hc
In, when the fault hc> the fault hb, the fault hc having many equivalent faults is processed later. For a hyper fault, depending on the context on the scan line, when fault hg → fault hf → fault he, the amount of events generated by the fault hg that is present at the earliest on the same line increases, and the To process. For a failure that is not related to a hyper failure, the one with the greater number of toggles is processed first. For example, regarding faults 1, 2, 3, and 4, fault 1> fault 2> fault 3
In the case of the fault 4, the fault 1 having the largest number of toggles is processed first.

In this example, two test patterns 1 (1
01) and test pattern 2 (103), but test pattern 1 (101) has a higher rate of transition, and this pattern is processed preferentially. Netlist 100, test pattern 1 (101) and failure list 1
(145) is input to the failure detector 146, and failure verification 1 is performed. The result of the failure verification 1 is returned to the transition information database 1
42 is written 147 and the database analysis 148 is performed.
Is performed, and a failure list 2 (149) is generated from the rate of transition in the undetected failure in the test pattern 1. The fault list 2 (149), the test pattern 2 (103), and the netlist 100 are input to the fault detector 116, and fault verification 2 is performed.

In this example, two test patterns are used. However, when verifying a plurality of test patterns, the same processing is repeated. For a hyper failure and a failure that may become a hyper failure, it is easy to confirm an operation failure by logic verification, and it is also possible not to perform failure verification. Conventionally, a hyper failure was recognized during the failure verification and removed from the failure verification target list, or the failure was verified as it was for a long time. By considering the above, unnecessary processing can be omitted. Further, the failure verification is not performed for a failure that does not make any transition in the signal transition verifications 102 and 104. Conventionally, a fault that has not been detected has been found to be undetected after a long period of fault verification. However, this method can be processed without performing unnecessary fault verification. In addition, signal transition verification 10
By performing steps 2 and 104, an effective test pattern can be preferentially processed, and a target failure that contributes to an improvement in the detection rate can be quickly verified, so that useless processing is omitted and processing time is greatly reduced. Is obtained.

A sixth embodiment of the present invention will be described with reference to FIG. The sixth embodiment is a case where the fifth embodiment is applied to distributed fault verification. FIG. 15 shows an example of the fault verification using two test patterns as in FIG.
5 will be described. In FIG. 15, the failure list 145 is divided (151). The method of dividing the failure list is the same as the method shown in FIG. 11, and divides the failure list shown in FIG. In other words, when dividing, the faults to be processed are distributed so that the ratio of the hyper-failures and the ratio of the signal transitions are substantially the same, and the processing order of the hyper-failures is delayed in each of the allocated fault sets. , The faults not related to the hyper fault are arranged in descending order of the number of signal transitions, and the fault list 1A (1
52), a failure list 1B (153) is generated. The fault list 1A (1
52), failure list 1B (153) and netlist 10
0, test pattern 1 (101) is input to perform fault verification. The two failure verifications are performed in parallel at the same time, and when all processes are completed, the results are totaled 156, and the overall failure detection rate is calculated. The overall failure verification time is limited by the slower of the two failure verifications. If the target faults that require processing time are offset, the effect of the distributed fault verification is significantly reduced. However, according to the present invention, the processing time is long, and the hyper failure which greatly affects the entire failure verification time is checked in advance, and the signal transition verification is performed so that the hyper failure and the signal transition become almost the same. Since the faults to be processed are sorted, the two fault verification times are almost the same, and the maximum effect is obtained in the distributed fault verification.

Subsequently, a database analysis 157 is performed to generate a failure list 2 (158) for an undetected failure in the test pattern 1 (101). The fault division 1 (159) of the target fault is performed based on the ratio of the hyper fault and the signal transition, and the fault list 2A (160) and the fault list 2B (16)
Generate 1). These lists and netlist 10
0, test pattern 2 (103) is input to two fault detectors 162 and 163, respectively, and a parallel fault verification is performed.
A totalization 164 of the results is performed.

In this example, two test patterns are used. However, when a plurality of test patterns are verified, the same processing is repeated. The technique according to the present invention is also applicable to an automatic test pattern generation device (ATPG).

[0039]

According to the method for verifying the failure of an integrated circuit according to the first aspect of the present invention, in order to know the ease of failure detection for all possible failures, signal transition is performed before normal failure verification. The test patterns or the verification target locations for performing the failure verification are ranked according to the signal transition ratio, and the verification is performed in order based on the ranking, so that useless test patterns are flown or unnecessary failures are performed. Without performing verification, it is possible to effectively perform failure verification while saving unnecessary processing time.

According to the integrated circuit fault verification method according to the second aspect, the verification target portion is equally divided so that the signal transition ratio becomes equal, and finally the entire fault detection rate is calculated. Since the processing time of the parallel processing in the distributed fault verification can be equalized, effective distributed fault verification can be performed. According to the failure verification method for an integrated circuit according to claim 3, since the amount of events that occur at the time of verification is considered in advance, a hyper-failure that is likely to generate an empirically known event among all possible failures Is considered, and verification is performed in order based on the ranking. In this way, prior to normal failure verification, by considering the hyper-failure that is likely to cause an event at the time of verification and ranking the test patterns for performing the failure verification or the failures to be verified, a useless test pattern can be flown, Failure verification can be performed effectively without performing unnecessary failure verification.

According to the integrated circuit fault verification method of the present invention, the processing time of the parallel processing in the distributed fault verification is reduced by equally dividing the hyper fault and finally calculating the entire fault detection rate. It is possible to make them even and effective distributed fault verification can be performed. According to the integrated circuit failure verification method according to the fifth aspect, among all possible failures, a hyper failure that easily causes an event known empirically is considered, and the confirmation of the ease of failure detection is performed. The signal transition confirmation and verification are performed, and the verification test patterns or the verification target portions are ranked in accordance with the signal transition ratio, and the verification is sequentially performed based on the ranking. That is, the signal transition verification is performed before the failure verification is performed, and the order of performing the failure verification is determined by considering the amount of events generated at the time of the verification.

According to the fault verification method for an integrated circuit according to the sixth aspect, as the distributed fault verification, the portions to be verified are equally divided so that the ratio of signal transitions becomes equal, and finally the entire fault detection rate is calculated. Therefore, there is an effect similar to that of the second aspect.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a fault verification method for performing signal transition verification according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a format of a transition information database used in claims 1 and 2;

FIG. 3 is an explanatory diagram for explaining a method of selecting which test pattern is to be processed first when a plurality of test patterns are used in claims 1 and 2;

FIG. 4 is an explanatory diagram of an example of a failure list in which the signal transition shown in claims 1 and 2 is considered.

FIG. 5 is an explanatory diagram illustrating a distributed fault verification method using signal transition verification according to a second embodiment corresponding to claim 2;

FIG. 6 is an explanatory diagram for explaining a fault dividing method for equalizing signal transitions shown in claim 2;

FIG. 7 is an explanatory diagram illustrating a failure verification method that focuses on a hyper failure that easily causes an event at the time of verification shown in the third embodiment corresponding to claim 3;

FIG. 8 is an explanatory diagram for explaining the definition of a hyper fault used in claims 3 and 4;

FIG. 9 is an explanatory diagram illustrating an example of a failure list generated in consideration of a hyper failure described in claims 3 and 4;

FIG. 10 is an explanatory diagram for explaining a distributed fault verification method in consideration of a hyper fault shown in the fourth embodiment corresponding to claim 4;

FIG. 11 is an explanatory diagram illustrating a fault dividing method for equalizing hyper faults according to claim 4;

FIG. 12 is an explanatory diagram of a fault verification method for performing signal transition verification in consideration of a hyper fault according to the fifth embodiment corresponding to claim 5;

FIG. 13 is an explanatory diagram of a transition information database format in claims 5 and 6;

FIG. 14 is an explanatory diagram of an example of a failure list in which hyper-failures and signal transitions shown in claims 5 and 6 are considered.

FIG. 15 is an explanatory diagram of a distributed fault verification method for performing signal transition verification in consideration of a hyper fault according to the sixth embodiment corresponding to claim 6;

FIG. 16 is an explanatory diagram of a conventional failure verification method.

[Explanation of symbols]

 Reference Signs List 100 netlist 101 test pattern 1 102 signal transition verification 103 test pattern 2 104 signal transition verification 105 netlist 106 failure detector 107 failure list 108 transition information database 109 database analysis 110 failure list 1 111 failure detector 112 detection information writing 113 database Analysis 114 Failure list 2 115 Failure detector

Claims (6)

[Claims] The present invention is characterized in that a signal transition verification for a verification target portion of a circuit is verified, a verification test pattern or a verification target portion is ranked according to a signal transition ratio, and verification is performed in an order based on the ranking. Verification method for integrated circuits. 2. A circuit for verifying and verifying a transition of a signal with respect to a portion to be verified of a circuit, prioritizing a verification test pattern or a portion to be verified according to a signal transition ratio, and verifying a signal to be verified so that the signal transition ratio becomes equal. A method for verifying the failure of an integrated circuit, characterized in that parts are equally divided, each is processed in parallel, and each processing is performed based on a ranking. 3. A verification target portion is ranked among the verification target portions of the circuit according to an event amount generated at the time of verification,
A fault verification method for an integrated circuit, wherein verification is performed in order based on the ranking. 4. A verification target portion is ranked among the verification target portions of the circuit according to an event amount generated at the time of verification,
The integrated circuit is characterized in that the verification target parts are equally divided so that hyper-failures that easily cause an event at the time of verification are equal, and each is processed in parallel, and the processing is performed based on the ranking in each processing. Failure verification method. 5. Considering a hyper-failure which is likely to generate an event at the time of verification in a portion to be verified of a circuit, and performing a signal transition confirmation verification for a portion to be verified of the circuit, and verifying according to a signal transition ratio. A fault verification method for an integrated circuit, wherein a test pattern or a portion to be verified is ranked, and verification is performed in an order based on the ranking. 6. Considering a hyper-failure that easily generates an event during verification in a circuit verification target portion, performs signal transition confirmation verification for the circuit verification target portion, and performs a verification test according to a signal transition ratio. The patterns and verification target parts are ranked, and the verification target parts are equally divided so that the ratios of hyper-failures and signal transitions are equal, and each is processed in parallel, and each processing is performed based on the ranking. A method for verifying the failure of an integrated circuit, comprising: