JPH0926986A - Test pattern generating method and delay verifying method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily generate a test pattern activating a preliminarily designated path by assuming the initial value of a path table and providing the descrepancy check means of a determined input value and a path determination means. SOLUTION: The initial value of a path table 109 is set by an initialization means 105, the input value of an element is determined by an input value determination means 106, whether the input value is discrepant or not is decided by a discrepancy check means 107, whether the setting of the next path and the generation of a test pattern are terminated or not is decided by a path determination means 108 and the generation result is outputted. Namely, a circuit description 101, element delay information 102 and path designation information 103 are inputted and values are stored in the path table 109 based on the initialization means 105. Based on the input value determination means 106, the discrepancy check means 107 and the path determination means 108, the value of the path table 109 is changed, and a test pattern 111 or an error 110 is outputted. Thus, the test pattern activating a preliminarily designated path can be easily generated and processing speed becomes quick.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generation method for a logic circuit and a delay verification method using the test pattern generation method.

[0002]

The speed of operation of digital circuits is determined by the maximum delay of the path. Therefore, it is necessary to verify the path delay in the circuit design. As a verification method, there is a method of examining the delay of the signal value of the path by a logical simulation that considers the delay of the element or the like. In the method using the logic simulation, which path is activated depends on the test pattern at the time of simulation. Therefore, it becomes necessary to generate a test pattern of a small size capable of verifying as many paths as possible for a designated path, particularly a critical path with a large delay.

Conventionally, in a method of generating a test pattern for activating a designated path, a circuit is divided, a graph expression is generated, and an indefinite signal P is propagated from an input side of an element to an output side thereof. A method for determining the degree of coverage of a path is disclosed in Japanese Patent Laid-Open No. H5-
-150007.

[0004]

In the case of generating a test pattern that activates a previously designated path, the conventional method had the purpose of determining the coverage of the path, so the test pattern was generated. Even if it cannot be done, there is no problem and the test pattern generation rate becomes poor. Further, since the circuit size is reduced because the circuit is divided, there is a possibility that a contradiction occurs when the circuit is routed from the input pin to the output pin.

An object of the present invention is to provide a method for easily generating a test pattern that activates a predesignated path.

[0006]

In order to achieve the above object, the present invention provides a test pattern generation method for activating a designated path of a circuit by inputting a logic circuit description, element delay information and path designation information. The initial value of the path table is set by the setting means, the input value of the element is decided by the input value deciding means, the contradiction checking means decides whether or not the input values contradict, and the path deciding means decides the next path. And whether or not the test pattern generation is completed is output, and the generation result is output.

[0007]

By the above means, it is possible to easily generate a test pattern for activating a previously designated path. Also, the processing speed is high because the test pattern is generated only for the target path.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining the whole of one embodiment of the present invention. The test pattern generation device 104 uses the circuit description 10
1, the element delay information 102 and the path designation information 103 are input, and the values are stored in the path table 109 based on the initial setting means 105. A path table 109 based on the input value determining means 106, the contradiction checking means 107, and the path determining means 108.
Value of the test pattern 111 or error 110
Is output.

The processing procedure of the input value determining means 106, the contradiction checking means 107, the path determining means 108, and the initial setting means 105 will be described below with reference to FIGS. 2, 3, 4, and 5. The structure of the path table 109 will be described with reference to FIG. The conditions for determining the input value will be described with reference to FIG. In addition, processing regarding a specific example will be described with reference to FIGS. The output in the case of an error will be described with reference to FIG. Finally, the output of the result will be described with reference to FIG.

FIG. 2 is a diagram for explaining the input value determining means 106 in detail. 201 is a branch condition for branching to 202 if the input value is uniquely determined from the element and the output value, and to 203 if not. 202 obtains an input value and stores it in the path table (604 in FIG. 6). 203 finds the fastest path to reach the element. 204 obtains an input value from FIG. 7 and stores it in the path table (605 in FIG. 6). Reference numeral 205 is a contradiction checking means (FIG. 3).

FIG. 3 is a diagram for explaining the contradiction checking means 107 in detail. 301 indicates two input values (20 in FIG. 2).
2 and 204) are different, the branch condition is to branch to 304, and if they are not different, branch to 302. Reference numeral 302 is a branch condition for branching to 303 if the same input signal on the reconvergence path matches, and to 304 if they do not match. Here, the reconvergence path means that there are a plurality of paths that reach the output value from the input value via some elements. Reference numeral 303 is a path determining means (FIG. 4). 30
4 is a branch condition for branching to 308 if the value of the output pin is 1, and to 305 if the value is not 1. 305 sets the value of the output pin to 1. 306 sets all paths except the input pin path as the target paths. 307 is an input value determining means (FIG. 2)
Call. 308 outputs a test pattern generation failure.

FIG. 4 is a diagram for explaining the path determining means 108 in detail. 401 is the path table of the current path (6 in FIG. 6).
03) completes the target path. 402 is a branch condition for branching to 408 if the input value of off-path is X and to 403 if it is not X. If the input path is a non-target path, 403 is a target path. 404 goes to 405 if the target path is completed, 40 if it is not completed
It is a branch condition for branching to 9. A branching condition 405 branches to 406 if there are a plurality of input values and to 407 if there are no input values. 406 selects an optimum input value from a plurality of input values. 407 activates the input pin. 408 is X
The path table of all paths after the value (603 in FIG. 6) is set as the non-target path. 409 gives priority to on-path and specifies the next path. Reference numeral 410 is an input value determining means (FIG. 2).

FIG. 5 is a diagram showing in detail the initial setting means 105. 501 is for all paths up to the element
The Max delay is calculated, and the Max delay of the path table (Fig. 6
602). Reference numeral 502 denotes values 1 and 2 in the path table corresponding to the designated output pin (604 and 60 in FIG. 6).
5) is set to 0. 503 sets X to values 1 and 2 (604 and 605 in FIG. 6) of the path table other than 502. 50
4 sets X to the flag (603 in FIG. 6) of the path table corresponding to the input pin. 505 sets the flags (603 in FIG. 6) of the path table other than 504 to 1. Reference numeral 506 excludes the flag (603 in FIG. 6) of the path table corresponding to the output pin other than the designated output pin from the target (0).

FIG. 6 is a diagram showing in detail the structure of the path table 109. 601 inputs all the path names of the circuit. 602 inputs the delay of the path obtained in 501 of FIG. 603 inputs one of the target path, the non-target path, the target path end, and the input pin path. A value 604 is input when 201 in FIG. 2 is satisfied. In 605, the value obtained in 204 of FIG. 2 is input.

FIG. 7 is a diagram for explaining the conditions for determining the input value. A branch 701 branches depending on whether or not a path that reaches the element earlier is a designated path. 702 branches depending on the condition of the element and the output value. Reference numeral 703 is an input value for the condition to be obtained.

Next, a processing example of the embodiment will be concretely described by using the circuits and data shown in FIGS.

FIG. 8A is an example of a circuit. G1, G
6, G7 are NOT gates, G3, G4, G8, G9, G
Reference numerals 10 and G11 are AND gates, G5, G12 and G13 are OR gates, and G2 is a NAND gate. a to p are path names. FIG. 8B is an example of the circuit description 101 describing the circuit of FIG. 8A. FIG. 8C is an example of the element delay information 102. FIG. 8D is an example of the path designation information 103.

FIG. 9A shows an example of a circuit. G1, G
6, G7 are NOT gates, G3, G4, G8, G9, G
Reference numerals 10 and G11 are AND gates, G5, G12 and G13 are OR gates, and G2 is a NAND gate. a to p are path names. FIG. 9B is an example of the circuit description 101 describing the circuit of FIG. 9A. FIG. 9C is an example of the element delay information 102. FIG. 9D is an example of the path designation information 103.

10 to 12 are path tables created based on the example of FIG. FIG. 10 shows the initial setting means 10.
It is a path table when 5 is executed. FIG. 11 shows the element G
12 is a path table when executed for 12. First,
The input value determining means 106 is executed. In 201, the element G1
Since the input value is uniquely determined from 2 (OR) and the output value of the path o (0 from the value 1 column of 1015), go to 202,
Value 1 for path k (column 1 for value 1011), value 1 for path l (1
0 is stored in the value 1 column of 012). At 203, the Max delays (602) of 1011 and 1012 are compared, and it is determined that 1011 reaches the element G12 earlier than 1012.

At 204, 701 in FIG. 7 is not equal to 702, the element OR is at 702, and the input value 703 obtained from the output value 0 is off-path.
= 0, on-path = 0, and the value of path k is 2 (value of 1011 is 2)
0) in the value 2 of path l (value 2 column of 1012)
Is stored. At 205, the procedure goes to the contradiction checking means 107.
In 301, the value 1 (604) of 1011 and the value 2 (60
5) The value 1 (604) of 1012 and the value 2 (605) of 1012 are respectively compared, and since they are the same, the process proceeds to step 302. Since 302 is not related to the path o, it is regarded as an input signal match and 30
Go to 3. At 303, the path determining means 108 is reached.

At 401, the flag of the current path o (flag column of 1015) is set as the target path. In 402, the input value of the path k goes from 0 to 403. Since 403 is already the target path, go to 404. At 404, since all the target paths are not finished, the process goes to 409. At 409, the next path is set to path 1. At 410, the input value determining means 106 is reached.
This completes the processing for the path o, and the path table shown in FIG. 11 is obtained. This process is repeated thereafter.

At a certain time, if the processing is performed with the value of the element G4 (AND) and the path g (0 from the value 1 column of 1007), the input signals do not match under the branch condition of 302.
Go to 304. In 304, the output pin value (value of 1015 is 1
(Column) is 0, so go to 305 and set the value of 1015 to 1
The column and the value 2 column are set to 1. At 306, the element G12 and the path o
To start with, set the initial flag state. At 307, the input value determining means 106 is reached. Repeat the process again,
At a certain time, the path table shown in FIG. 12 is created. When processing is performed with the element G4 (AND) and the value of the path g (1 from the value 1 column of 1007), since the input signals do not match under the branch condition of 302, the process proceeds to 304. In 304, the value is the output pin value (1 from the value 1 column of 1015), so the process proceeds to 308. 16 is output at 308.

Although 408 is not executed in the above example, 408 is executed assuming that there is no contradiction in the processing of the element G4 and the path g, for example. The operation of 408 will be described under this assumption. That is, assuming that there is no contradiction between the processing of the element G4 and the processing of the path g, the input value of off-path = X in 402, and the processing proceeds to 408. At 408, flags of the path f and the paths e and d on the input side (1004, 1005, 1006)
Flag field) is set as a non-target path (0).

13 to 15 are path tables created based on the example of FIG. FIG. 13 shows the initial setting means 1.
It is a path table when 05 is executed. FIG. 14 is a path table when the same process as the example of FIG. 8 is executed for the output value (0 from the value 1 column of 1116) of the element G13 (OR) and the path p. FIG. 15 shows a path table when this processing is repeated and all target paths are executed.

At 404, it is determined that all the target paths have been executed, and the processing proceeds to 405. Since there is only one input value in 405, the process goes to 407. In 407, the value 2 of the path b which is on-path is 0 (value 2 column of 1102), so the value of b is activated from 1 to 0 at time t = 0. Four
FIG. 17 is output at 11.

FIG. 16 is a diagram for explaining the output result when an error occurs. FIG. 17 is an example of the output result of the test pattern obtained when executing FIG.

Delay verification by the test pattern generator will be described with reference to FIGS.

FIG. 18 is a diagram for explaining the delay verification using the delay check system. Delay verification device 14
03 is a delay check system that inputs delay information 1409 and circuit description 1401 and outputs delay fault path information 1405, and circuit check 1401, element delay information 1402, and delay fault path information 1405 that are inactive path information. 1407 and a test pattern generation device 1406 that outputs active path information 1408.

Here, the delay check system is a system which enumerates all the paths existing in the logic circuit and calculates the delay time. The procedure for delay verification using the delay check system is shown below. Operates the delay check system to detect paths with defective delay times,
The test pattern generation device is operated to determine whether or not the delay time defective path is an active path, and when it is an active path, a countermeasure for the delay time defective path is taken.

FIG. 19 is a diagram for explaining delay verification using a logic simulator with delay. Delay verification device 1503
Is a circuit description 1501, a path trace / path coverage system which inputs a circuit description 1501, path designation information 1510, an initial test pattern 1511 or a test pattern 1506 and operates a logic simulator with delay 1504 to output inactive path information 1507. , Element delay information 1
502, a non-active path information 1507 as input, and a test pattern generation device 1508 which outputs a test pattern 1506 and inactive path information 1509.

Here, the path trace / path coverage system detects whether or not the specified path is activated during the logic simulation, and determines what percentage of the specified path is activated. , A system that determines which path has not been activated. The procedure for delay verification using the path trace / path coverage system is shown below. The path trace / path coverage system detects whether or not the path is activated during the logic simulator with delay.The inactive path is activated by the test pattern generator to determine whether it is an active path. As a result, a test pattern is generated, a logic simulator with delay is operated, and unverified paths are removed.

Next, the input / output of the delay check system 1404 and the path trace / path coverage system 1505 will be concretely described with reference to FIG.

FIG. 20A shows an example of a circuit. FIG.
(B) is an example of the delay information 1409. The delay check system 1404 uses the delay information 140 among all paths.
The paths exceeding 9 are output to the delay failure path information 1405 as the delay failure paths. FIG. 20C is an example of the delay failure path information 1405. FIG. 20D is an example of the path designation information 1510. FIG. 20E shows an example of the initial test pattern 1511. The path trace / path coverage system 1505 uses the initial test pattern for the path of the path designation information 1510, operates the logic simulator with delay 1504, and outputs the inactive path information 1507. FIG. 20F is an example of the inactive path information 1507. FIG. 20G shows an example of coverage information 1512. This example is an example of the path trace / path coverage system 1505 when the logic simulator with delay 1504 is operated using the initial test pattern 1511.

[0034]

According to the present invention, in a method for automatically generating a test pattern that activates a predesignated path,
It is possible to easily detect the delay target path. In addition, it can be said that a path that cannot generate a test pattern is a path that is not activated.

In the delay verification using the delay check system, the test pattern generating device is operated only for the delay time defective path detected by the delay check system, and it is determined whether or not the path is an active path. Inactive paths can be automatically removed. Further, the design change of the delay time defective path can be performed only for the active path, so that the man-hour of the design change can be reduced. Furthermore, in delay verification using a logic simulator with delay, the unverified path can be removed by operating the test pattern generator for the unverified path detected by the path trace / path coverage system and generating the test pattern. Is.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus configuration for implementing a method according to an embodiment of the present invention.

FIG. 2 is a flowchart of processing steps in an input value determining unit.

FIG. 3 is a flowchart of processing steps in the contradiction checking unit.

FIG. 4 is a flowchart of processing steps in a path determining unit.

FIG. 5 is a flowchart of processing steps in an initial setting unit.

FIG. 6 is an explanatory diagram of a data structure of a path table.

FIG. 7 is an explanatory diagram of a condition for determining an input value.

FIG. 8 is an explanatory diagram showing an example of a circuit and an input file.

FIG. 9 is an explanatory diagram showing an example of a circuit and an input file.

10 is an explanatory diagram of a path table created based on the circuit data of FIG.

FIG. 11 is an explanatory diagram of a path table created based on the circuit data of FIG.

12 is an explanatory diagram of a path table created based on the circuit data of FIG.

FIG. 13 is an explanatory diagram of a path table created based on the circuit data of FIG.

14 is an explanatory diagram of a path table created based on the circuit data of FIG.

15 is an explanatory diagram of a path table created based on the circuit data of FIG.

FIG. 16 is an explanatory diagram of an output result when the test pattern generation fails.

FIG. 17 is an explanatory diagram of an output result of a test pattern.

FIG. 18 is an explanatory diagram of delay verification according to an embodiment of the present invention.

FIG. 19 is an explanatory diagram of delay verification according to an embodiment of the present invention.

FIG. 20 is an explanatory diagram of a delay check system according to an embodiment of the present invention.

[Explanation of symbols]

101 ... Circuit description, 102 ... Element delay information, 103 ... Path designation information, 104 ... Test pattern generation device, 105 ...
Initial setting means, 106 ... Input value determining means, 107 ... Contradiction checking means, 108 ... Path determining means, 109 ... Path table, 110 ... Error result, 111 ... Output result.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 21/66 G06F 11/26 310 15/60 668A (72) Inside of the inventor Konagi, Kokubunji City, Tokyo 1-chome No. 280, Central Research Laboratory, Hitachi, Ltd.

Claims (3)

[Claims] 1. In a test pattern generation method for activating a designated path of the circuit by inputting a logic circuit description, element delay information, and path designation information, an initial value of a path table is set by an initial setting means, and an input value is set. The input value of the element is determined by the determination means, it is determined whether the input value is inconsistent by the contradiction check means, it is determined whether the setting of the next path and the test pattern generation is completed by the path determination means, A test pattern generation method characterized by outputting a generation result. 2. A delay check system is used to enumerate all paths of the circuit by inputting delay information, circuit description, and element delay information, and a delay time defective path is detected.
A delay verification method, comprising: determining whether or not a delay time defective path is activated by the test pattern generation device according to claim 1 and taking measures only for the activated path. 3. Path designation information, test pattern, circuit description,
With the element delay information as input, the logic simulator with delay is operated with the initial test pattern as input, and it is detected whether or not the specified path is activated by the path trace / path coverage system, and the inactive path is detected. A delay verification method characterized in that the test pattern generation device according to claim 1 is operated only for inactive paths to remove unverified paths.