JP3048003B2 - Semiconductor device failure simulation method and data creation device in failure simulation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating a failure of a semiconductor device and a data creating apparatus for the failure simulation. With the recent increase in the scale of LSIs, the processing time of a fault simulation performed by defining a hypothetical fault at the input / output terminal of each basic gate constituting a semiconductor device is increasing, and a reduction in the processing time is required. Is coming.

[0002]

2. Description of the Related Art Conventionally, a failure simulation of a semiconductor device is performed by examining circuit data defining a hypothetical failure at input terminals and output terminals of all basic gates constituting the semiconductor device and inputting the data to the semiconductor device and examining its operation. Signal data is prepared, and the operation is performed based on the circuit data and the signal data.

[0003]

However, as the size of a semiconductor device increases, that is, as the number of basic gates increases, the number of assumed faults defined in circuit data becomes enormous.
There is a problem that computer processing time in the failure simulation is long. The present invention has been made in order to solve the above problems, and provides a failure simulation method capable of shortening the simulation processing time by performing a failure simulation in units of functional blocks including a plurality of basic gates. With the goal.

Another object of the present invention is to provide a data creation device for a failure simulation for creating simulation data capable of shortening the processing time of the failure simulation.

[0005]

In order to achieve the above object, according to a first aspect of the present invention, there is provided circuit data defining a hypothetical fault with respect to input / output terminals of each basic gate constituting a semiconductor device, and input to the semiconductor device. Then, signal data for checking the operation are prepared in advance. Each basic gate in the circuit data is divided into a plurality of functional block units composed of a plurality of basic gates, and each functional block has one input terminal side gate or one output terminal side gate on the same net as each input terminal or each output terminal. Ask only. And each
Same net as each input terminal or each output terminal of the function block
Input terminal side gate or output terminal side gate
When only one is required, each input terminal of each functional block
Or there are multiple basic gates corresponding to each output terminal
When between the input terminal and the plurality of basic gates,
Or 1 between the output terminal and the plurality of basic gates.
And insert it into the input terminal side gate or
Is determined as the output terminal side gate. Then, of all the assumed faults defined in the input / output terminals of the respective basic gates in the functional block, the faults other than the assumed fault of the input terminal of the input terminal side gate and the assumed fault of the output terminal of the output terminal side gate are removed. To create fault elimination circuit data.
A failure simulation is performed based on the failure removal circuit data and the signal data.

In the second invention, the input / output of each basic gate is
Input the circuit data of the semiconductor device that defines the
Each functional block consisting of multiple basic gates.
To detect each input terminal and each output terminal of the function block
Function block terminal detection section and function block terminal detection
Each input terminal of each functional block detected by the
Net data detector that detects net data of output terminal
And each net data detected by the net data detector
Input or output terminal of the gate corresponding to each
Basic gate terminal detection section and basic gate terminal detection
Section is for each input terminal or each output terminal of each functional block.
Input terminals of multiple basic gates or
Indicates the input terminal and its
Between the input terminal of the basic gate or the output terminal and the
One dummy between the output terminals of these multiple basic gates
Equipped with a dummy gate insertion part for inserting a gate,
The terminal detection part is a dummy gate
When a dummy gate is inserted, the input terminal or output
Input terminal to the net data detected by the net data detector.
Detected as an input or output terminal of the gate corresponding to the
And the input terminal of each basic gate in the function block
Out of all the contingencies defined for the
Gate input terminal detected by this gate terminal detector
Or, remove failures other than the assumed failure of the output terminal and remove the failure
A hypothetical fault removing unit for creating circuit data;
Configure the creation device.

[0007]

[0008]

[0009]

According to the first aspect of the present invention, a fault simulation is executed based on the fault elimination circuit data and the signal data created from the circuit data, so that the number of assumed faults is reduced and the simulation processing time is shortened. You.
Further, in a semiconductor device of a product type having a high fault detection rate in the fault simulation based on the circuit data, even if the fault simulation based on the fault elimination circuit data is performed, the fault detection rate and the fault detection rate in the fault simulation based on the circuit data are not improved. And there is almost no difference between them, and a decrease in the accuracy of the failure simulation is prevented. In addition, each function block
And the same net as each input terminal or each output terminal
If there are multiple gates, execute a failure simulation
Although it is not possible, the input terminal and the
Between the gate or the output terminal and the plurality of basic gates.
Insert one dummy gate between the gate and input it
Terminal side gate or output terminal side gate
Fault simulation can be performed.
It works.

[0010]

According to the second aspect of the present invention, fault elimination circuit data in which a hypothetical fault in each functional block is eliminated is easily created from circuit data defining a hypothetical fault at the input / output terminal of each basic gate. In addition , even if there are input terminals or output terminals of a plurality of basic gates corresponding to each input terminal or each output terminal of each functional block in the circuit data, dummy data is inserted to correspond to each net data. Only one input terminal or output terminal of the gate is generated, and fault elimination circuit data that can execute a fault simulation is created.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a failure simulation device. The failure simulation device includes a circuit data file 1, a signal data file 2, a data creation device 3, a failure removal circuit data file 4, a failure simulator unit 5, and the like.

The circuit data file 1 stores data of a number of functional blocks constituting a semiconductor device.
FIG. 3 shows an example of a functional block 11 stored in the circuit data file 1, and this functional block 11
2, 13 and output terminals 14, 15, each basic gate 16 to 19 constituting the same block 11, each net n1 to n4 between the terminal and the basic gate or between the basic gates, and the input of each basic gate 16 to 19 It consists of data such as a hypothetical failure (indicated by ●) defined at the output terminal. The signal data file 2 stores signal data to be input to the semiconductor device and checked for its operation.

As shown in FIG. 2, the data generating device 3 includes a functional block terminal detecting unit 6, a net data detecting unit 7, a basic gate terminal detecting unit 8, a hypothetical fault removing unit 9, and the like. The function block terminal detection unit 6 inputs data from the circuit data file 1 in units of function blocks including a plurality of basic gates, and detects an input terminal and an output terminal of each function block. Therefore, for example, in the functional block 11 shown in FIG. 3, the input terminals 12 and 13 are detected, and the output terminals 14 and 15 are detected.

The net data detecting section 7 detects the net data of the input terminal or the output terminal of each functional block detected by the functional block terminal detecting section 6, and outputs the detected net data to the basic gate terminal detecting section 8. I do. In the functional block 11 shown in FIG. 3, n1 and n3 are detected as net data of the input terminals 12 and 13, respectively, and n2 and n2 are detected as net data of the output terminals 14 and 15, respectively.
n4 is detected.

The basic gate terminal detecting section 8 detects an input terminal or an output terminal of a gate corresponding to each net data detected by the net data detecting section 7, and assumes the detected input terminal or output terminal as a fault removing section. 9 is output. That is, in the functional block 11 shown in FIG.
1, the input terminal 16a of the basic gate 16 corresponds to the net n2, and the output terminal 17b of the basic gate 17 corresponds to the net n2.
Input terminal 18a of basic gate 18 corresponding to net n3
Is the output terminal 1 of the basic gate 19 corresponding to the net n4.
9b are respectively detected.

The basic gate terminal detecting section 8 includes a dummy gate inserting section 8A. When the input terminal or the output terminal of a plurality of basic gates respectively exists corresponding to each net data detected by the net data detection unit 7, the dummy gate insertion unit 8A determines the input terminal of the functional block and the plurality of basic terminals. One dummy gate is inserted between the input terminal of the gate or between the output terminal of the functional block and the output terminals of the plurality of basic gates. When the dummy gate is inserted by the dummy gate insertion unit 8A, the basic gate terminal detection unit 8 changes the input terminal or the output terminal of the dummy gate to the input terminal corresponding to the net data detected by the net data detection unit 7. Alternatively, it is detected as an output terminal.

Therefore, as shown in FIG. 5A, when there are input terminals 22a and 23a of the basic gates 22 and 23 corresponding to the net n5 of the input terminal 21 of the functional block 20, FIG. ), A dummy gate 29 is inserted between the input terminal 21 and the basic gates 22 and 23,
Input terminal 29a is detected corresponding to net n5. As shown in FIG. 5B, the input terminal 25 of the functional block 24
When there are input terminals 26a, 27a of the basic gates 26, 27 corresponding to the net n6 of FIG. 6, a dummy gate 30 is provided between the input terminal 25 and the basic gates 26, 27 as shown in FIG. Is inserted, and the input terminal 30a is detected corresponding to the net n6.

When the output terminals 33b and 34b of the basic gates 33 and 34 exist in correspondence with the net n7 of the output terminal 32 of the functional block 31, as shown in FIG. As shown in (), a dummy gate 39 is inserted between the output terminal 32 and the basic gates 33 and 34, and the output terminal 39b is detected corresponding to the net n7. FIG.
When the output terminals 37b and 38b of the basic gates 37 and 38 exist corresponding to the net n8 of the output terminal 36 of the functional block 35 as shown in FIG. 8B, the output terminals are output as shown in FIG. Dummy gate 40 is inserted between 36 and basic gates 37 and 38, and output terminal 40b is detected corresponding to net n8.

The hypothetical fault elimination unit 9 selects the input terminal or output terminal of each basic gate in each functional block other than the input terminal or output terminal of the gate detected by the basic gate terminal detection unit 8. The fault is removed to create fault removal circuit data, which is stored in the failure removal circuit data file 4. Therefore, for example, as shown in FIG. 3, the functional block 11 in which a hypothetical fault (indicated by ●) is defined in the input / output terminals of the basic gates 16 to 19,
As shown in FIG. 4, the input terminal 16a of the basic gate 16, the output terminal 17b of the basic gate 17, the input terminal 18a of the basic gate 18, and the output terminal 19b of the basic gate 19
Only one hypothetical fault remains and the other hypothetical faults have been eliminated.

The fault simulator section 5 inputs the fault elimination circuit data from which the assumed fault has been eliminated from the failure elimination circuit data file 4 and also inputs the signal data from the signal data file 2 and performs a fault simulation based on both data. Execute As described above, in the present embodiment, when performing the failure simulation of the semiconductor device, the circuit data of the semiconductor device is handled in units of functional blocks, and all of the input / output terminals of the plurality of basic gates constituting each functional block are defined. Reduced the number of hypothetical faults, because the hypothetical faults other than those defined for the input terminal or output terminal of the basic gate that is the same net as the input terminal or output terminal of each functional block are eliminated. And the simulation processing time can be shortened.

FIG. 9 is a diagram showing a comparison of the fault detection rates obtained by applying the fault simulation in the present embodiment and the conventional fault simulation to semiconductor devices of the same type. The failure detection rate in this embodiment is represented by ▲, and the failure detection rate in the conventional method is represented by ○. or,
The types of the semiconductor devices are arranged in the order of the type having the lowest failure detection rate in the conventional method. The fault detection rate is defined as (Y / X) × 100, where X is the total number of assumed faults in the circuit data before or after the fault is removed, and Y is the number of faults detected in the fault simulation. It is represented by

As can be seen from FIG. 9, in a product type having a high fault detection rate, for example, a product type having a fault detection rate of 95% or more, the fault detection rate of the fault simulation in this embodiment and the fault detection rate in the conventional fault simulation are compared. There is little difference between them. That is, even if the hypothetical fault defined in the input / output terminal of the basic gate in the functional block is removed as in the present embodiment, the accuracy of the fault simulation does not decrease.

In this embodiment, when there are input terminals or output terminals of a plurality of basic gates corresponding to the respective net data detected by the net data detector 7,
Dummy gate insertion unit 8 provided in basic gate terminal detection unit 8
With A, one dummy gate is inserted between the input terminal of the functional block and the input terminals of the plurality of basic gates, or between the output terminal of the functional block and the output terminals of the plurality of basic gates. This is to cope with the fact that when a net branches in a failure simulation and there is a hypothetical failure of a plurality of input terminals or output terminals for the net, the failure simulation cannot be executed. The hypothetical fault corresponding to the net of each output terminal is only one hypothetical fault defined for the input terminal or the output terminal of the dummy gate,
Fault elimination circuit data can be easily created and a fault simulation can be executed.

[0025]

As described above in detail, according to the first aspect, the failure simulation is executed based on the fault elimination circuit data and the signal data created from the circuit data, so that the number of assumed failures is reduced. Thus, the simulation processing time can be shortened while preventing the accuracy of the failure simulation from lowering. Also, in the circuit data
Each input terminal or each output terminal in each functional block
If there are multiple basic gates that are on the same net,
Between the output terminal and the plurality of basic gates or the output
One dummy gate between the terminal and the plurality of basic gates.
And insert it into the input terminal side gate or output terminal side
Since the gate is determined, failure simulation
You can perform the action.

Further, according to the second invention, a failure simulation system is provided .
Simulation data that can reduce the processing time of
Can be easily created. Also, in the circuit data
Each net of each input terminal or each output terminal of each functional block
Input terminal or output of multiple basic gates corresponding to data
Even if there is a terminal, failure spot
Create fault elimination circuit data that can execute simulation
Can be

[0027]

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a failure simulation device according to an embodiment.

FIG. 2 is a block diagram illustrating a data creation device according to one embodiment.

FIG. 3 is a diagram illustrating a state of a functional block of an example before a presumed fault is removed;

FIG. 4 is a diagram illustrating a state of a functional block of an example after a hypothetical fault is removed;

FIGS. 5A and 5B are functional blocks each showing a plurality of basic gates for an input terminal.

FIGS. 6 (a) and (b) are FIGS. 5 (a) and (b), respectively.
FIG. 7 is a diagram showing a state where a dummy gate is inserted into the functional block of FIG.

FIGS. 7A and 7B are diagrams showing a state in which a plurality of basic gates exist for an output terminal of a functional block, respectively.

FIGS. 8A and 8B are FIGS. 7A and 7B, respectively.
FIG. 7 is a diagram showing a state where a dummy gate is inserted into the functional block of FIG.

FIG. 9 is a diagram showing a failure detection rate in the failure simulation of the present embodiment in comparison with a failure detection rate in the conventional failure simulation.

[Explanation of symbols]

 Reference Signs List 3 Data creation device 6 Function block terminal detection unit 7 Net data detection unit 8 Basic gate terminal detection unit 8A Dummy gate insertion unit 9 Assumed fault removal unit

Continuation of the front page (56) References JP-A-1-217644 (JP, A) JP-A-3-179567 (JP, A) JP-A-4-241040 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) G06F 17/50 G01R 31/28 JICST file (JOIS)

Claims (2)

(57) [Claims] 1. A circuit data defining a hypothetical fault with respect to an input / output terminal of each basic gate constituting a semiconductor device and signal data for inputting to the semiconductor device and examining the operation thereof are prepared in advance. Each basic gate in the circuit data is divided into a plurality of functional block units composed of a plurality of basic gates. In each functional block, an input terminal side gate or an output terminal side gate which is on the same net as each input terminal or each output terminal is one.
Out of all the hypothetical faults defined for the input / output terminals of each basic gate in the function block, except for the hypothetical fault of the input terminal of the input terminal side gate and the hypothetical fault of the output terminal of the output terminal side gate. Create fault elimination circuit data by eliminating faults, and use the same as each input terminal or each output terminal of each functional block
Input terminal side gate or output terminal side gate
When asking for only one each, each input of each functional block
Multiple basic gates exist for each output terminal or each output terminal.
When the input terminal and the multiple basic gates
Or between the output terminal and the plurality of basic gates.
Insert one dummy gate between them and insert it into the input terminal side gate.
Over determined as preparative or output terminal side gate, fault simulation method of a semiconductor device characterized by being adapted to perform a fault simulation based this fault removal circuit data into the signal data. 2. The circuit data of a semiconductor device in which a hypothetical fault is defined is input to the input / output terminals of each basic gate, and each input terminal and each output terminal of each functional block comprising a plurality of basic gates are detected. a function block terminal detection unit that, the net data detector for detecting the net data of each input terminal or the output terminals of the functional blocks more detected on the functional block terminal detection unit, more detected on the network data detector a basic gate terminal detecting unit for detecting an input terminal or an output terminal of the gate corresponding to each net data, the basic gate terminal detection unit, the input of each functional block
Multiple terminals corresponding to each net data of terminal or each output terminal
When there is an input terminal or output terminal of the basic gate ,
Between the input terminal and the input terminals of the plurality of basic gates.
Between or between the output terminals and the outputs of the plurality of basic gates
Dummy gate with one dummy gate inserted between terminals
The basic gate terminal detector is a dummy gate
When a dummy gate is inserted by the insertion part,
Gate input terminal or output terminal
The gate corresponding to the net data detected by the output
Detected as an input terminal or output terminal
If, among all the assumptions faults defined in the input terminal or output terminal of each basic gates in the functional block, the fault other than hypothetical failure of the input terminal or output terminal of the more the detected gate to said basic gate terminal detector And a hypothetical fault removing unit for creating fault removing circuit data by removing the data.