JPH05242194A - Delay analytic system - Google Patents

Abstract

PURPOSE:To shorten the time required to calculate a signal path delay time based upon actual wiring length after layout operation. CONSTITUTION:Virtual wiring delay times which are calculated from virtual wiring length are held by networks of a logic circuit and actual wiring delay times calculated from actual wiring length are held by the networks of the logic circuit; and the wiring delay times in a virtual wiring delay time storage means 3 and an actual wiring delay time storage means 6 are compared, for every net work, and networks whose real wiring delay times are longer than their virtual wiring delay times at the maximum delay time are extracted; and a delay time increase network detecting means 7 holds the extracted networks and the maximum delay time of a signal path including the networks held in a delay time increase network information storage means 8 is calculated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay analysis system for a digital logic circuit, and more particularly to a delay analysis system for realizing an efficient delay calculation method after layout.

[0002]

2. Description of the Related Art In a conventional delay analysis system, a delay calculation based on a virtual wiring length is performed and a delay problem is solved.
Furthermore, the delay calculation based on the actual wiring length after layout detects the delay time violation signal path for the entire circuit to be calculated.

[0003]

In this conventional delay analysis system, the following two conditions are satisfied: condition 1: maximum wiring delay calculated by actual wiring length rather than maximum wiring delay time calculated by virtual wiring length Does not include any nets that take a long time. Condition 2: Does not include any net whose minimum wiring delay time calculated by the actual wiring length is shorter than the minimum wiring delay time calculated by the virtual wiring length. Even if the signal path that satisfies the condition is verified by the delay calculation based on the virtual wiring length, it is calculated again by the delay calculation based on the actual wiring length. Therefore, the delay time of the signal path based on the actual wiring length is calculated. However, there was a problem that extra calculation time was spent.

[0004]

The delay analysis system of the present invention comprises a virtual wiring charge time storage means for holding a virtual wiring delay time calculated by a virtual wiring length for each net of a logic circuit, and a net of the logic circuit. The actual wiring delay time storage means for holding the actual wiring delay time calculated for each real wiring length, the wiring delay times in the virtual wiring delay time storage means and the actual wiring delay time storage means are compared for each net. , A delay time increase net detecting means for extracting a net whose actual wiring delay time is larger than the virtual wiring delay time at the maximum delay time, and a delay time increasing net information storage means for holding the net extracted by the delay time increasing net detection means And a signal path maximum delay time meter for calculating the maximum delay time of a signal path including a net held in the delay time increase net information storage means. It is intended and means. A delay analysis system according to another invention of the present invention includes a virtual wiring delay time storage means for holding a virtual wiring delay time calculated by a virtual wiring length for each net of a logic circuit, and an actual realization for each net of the logic circuit. The actual wiring delay time storage means for holding the actual wiring delay time calculated by the wiring length, the wiring delay times in the virtual wiring delay time storage means and the actual wiring delay time storage means are compared for each net, and the minimum delay is obtained. A delay time reduction net detecting means for extracting a net whose actual wiring delay time is smaller than the virtual wiring delay time in time; a delay time decreasing net information storage means for holding the net extracted by the delay time decreasing net detection means; Signal path minimum delay time calculation means for calculating the minimum delay time of the signal path including the net held in the delay time reduction net information storage means It is those with a.

[0005]

According to the present invention, only the delay time of a signal path including a net whose actual wiring maximum delay time is larger than the virtual wiring maximum delay time or a net whose actual wiring minimum delay time is smaller than the virtual wiring minimum delay time is calculated.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, which shows a configuration example of the first invention. In FIG. 1, reference numeral 1 denotes a circuit connection storage means for holding the constituent elements of a logic circuit to be subjected to delay analysis and the connection relationship between the constituent elements,
Reference numeral 2 is a virtual wiring delay time calculating means for calculating the wiring delay time based on the virtual wiring length, 3 is virtual wiring delay time storing means for holding the virtual wiring delay time calculated by the virtual wiring length for each net of the logic circuit, 4 Is a layout result storage means for holding the placement / wiring results of the logic circuit in the circuit connection storage means 1, reference numeral 5 is an actual wiring delay time calculation means for calculating the wiring delay time based on the actual wiring length, and 6 is a logic circuit The actual wiring delay time storage means for holding the actual wiring time calculated by the actual wiring length for each net, 7 compares the wiring delay times in the virtual wiring delay time storage means 3 and the actual wiring delay time storage means 6 for each net. However, the delay time increase net detecting means for extracting nets whose actual wiring delay time is larger than the virtual wiring delay time at the maximum delay time, and 8 are extracted by the delay time increasing net detecting means 7. Delay time increased net information storage means for holding the net, the signal path maximum delay time calculating means for calculating a maximum delay time of a signal path including a net held in the delay time increases net information storage means 8 9, 1
0 is a calculation result obtained by the signal path maximum delay time calculating means 9.

Next, the operation of the embodiment shown in FIG. 1 will be described.

First, the circuit connection means 1 for holding the constituent elements of the logic circuit to be subjected to the delay analysis and the connection relationship between the constituent elements are input, and the virtual wiring delay time calculation means 2 inputs the wiring delay based on the virtual wiring length. The time is calculated and stored in the virtual wiring delay time storage means 3. The virtual wiring length is set to a length that has a high probability of becoming larger than the actual wiring length in the calculation of the maximum delay time. This length is for LSI chips and PKG
It is calculated based on the size of the board and the number of net pin pairs. Further, in the calculation of the minimum delay time, the virtual wiring length is set to a length having a high probability of becoming smaller than the actual wiring length by the same method as the maximum delay time. The maximum delay time and the minimum delay time are calculated for the virtual wiring delay time in consideration of the difference in the virtual wiring length and the variation in manufacturing. Then, the actual wiring delay time calculation means 5 calculates the wiring delay time based on the actual wiring length from the layout result storage means 4 holding the layout / wiring results of the logic circuits in the circuit connection storage means 1.
It is stored in the actual wiring delay time storage means 6. For the actual wiring delay time, the maximum delay time and the minimum delay time are calculated in consideration of variations at the time of manufacturing.

Next, the delay time increase net detecting means 7
The virtual wiring maximum delay time and the actual wiring maximum delay time are extracted from the virtual wiring delay time storage means 3 and the actual wiring delay time storage means 6 one net at a time, and when the actual wiring maximum delay time is larger than the virtual wiring maximum delay time. , And stores the net information in the delay time increase net information storage means 8. The delay time increase net detecting means 7 performs this process for all nets in the virtual wiring delay time storage means 3 and the real wiring delay time storage means 4. Then, the signal path maximum delay time calculation means 9 calculates the maximum delay time only for the signal path including the net in the delay time increase net information storage means 8 and displays the result in the calculation result 10.

FIG. 2 is a block diagram showing another embodiment of the present invention, showing a configuration example of the second invention. This Figure 2
In FIG. 11, the same reference numerals as those in FIG.
Compares the wiring delay times in the virtual wiring delay time storage means 3 and the actual wiring delay time storage means 6 for each net, and extracts the nets whose real wiring delay time is smaller than the virtual wiring delay time at the minimum delay time. Net detection means, 12
Is a delay time reduction net information storage means for holding the net extracted by the delay time reduction net detection means, 1
Reference numeral 3 is a signal path minimum delay time calculation means for calculating the minimum delay time of a signal path including the net held in the delay time reduction net information storage means 12, and 14 is obtained by the signal path minimum delay time calculation means 13. This is the calculation result.

Next, the operation of the embodiment shown in FIG. 2 will be described.

First, the circuit connection storage means 1 for holding the constituent elements of the logic circuit to be subjected to the delay analysis and the connection relationship between the constituent elements is input, and the virtual wiring delay time calculation means 2 inputs the wiring based on the virtual wiring length. The delay time is calculated and stored in the virtual wiring delay time storage means 3. The virtual wiring length is set to a length that has a high probability of becoming larger than the actual wiring length in the calculation of the maximum delay time. This length is for LSI chip and P
It is calculated based on the size of the KG board, the number of net pin pairs, and the like. Further, in the calculation of the minimum delay time, the virtual wiring length is set to a length having a high probability of becoming smaller than the actual wiring length by the same method as the maximum delay time. The maximum delay time and the minimum delay time are calculated for the virtual wiring delay time in consideration of the difference in the virtual wiring length and the variation in manufacturing. And
The actual wiring delay time calculation means 5 calculates the wiring delay time based on the actual wiring length from the layout result storage means 4 which holds the layout / wiring results of the logic circuits in the circuit connection storage means 1 and stores the actual wiring delay time. Store in the means 6. For the actual wiring delay time, the maximum delay time and the minimum delay time are calculated in consideration of variations at the time of manufacturing.

Next, the delay time reduction net detecting means 11
The virtual wiring minimum delay time and the actual wiring minimum delay time are extracted from the virtual wiring delay time storage means 3 and the real wiring delay time storage means 6 one net at a time, and when the actual wiring minimum delay time is smaller than the virtual wiring minimum delay time. , And stores the net information in the delay time reduction net information storage means 12. The delay time decrease net detection means 11 performs this process for all nets in the virtual wiring delay time storage means 3 and the real wiring delay time storage means 6. Then, the signal path minimum delay time calculation means 13 calculates the minimum delay time only for the signal path including the net in the delay time reduction net information storage means 12, and displays the result in the calculation result 14.

[0014]

As described above, according to the present invention, the delay time of a signal path including a net whose actual wiring maximum delay time is larger than the virtual wiring maximum delay time or a net whose actual wiring minimum delay time is smaller than the virtual wiring minimum delay time. Since only the calculation is performed, the calculation time of the signal path delay time based on the actual wiring length after layout can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 3 virtual wiring delay time storage means 6 actual wiring delay time storage means 7 delay time increase net detection means 8 delay time increase net information storage means 9 signal path maximum delay time calculation means 11 delay time decrease net detection means 12 delay time decrease net information Storage means 13 Signal path minimum delay time calculation means

Claims (2)

[Claims] 1. A virtual wiring delay time storage means for holding a virtual wiring delay time calculated by a virtual wiring length for each net of a logic circuit, and an actual wiring delay calculated by an actual wiring length for each net of the logic circuit. The actual wiring delay time storage means for holding the time, the wiring delay times in the virtual wiring delay time storage means and the actual wiring delay time storage means are compared for each net, and the actual wiring delay time is the virtual wiring at the maximum delay time. Delay time increase net detection means for extracting nets larger than the delay time, delay time increase net information storage means for holding the nets extracted by the delay time increase net detection means, and delay time increase net information storage means A delay analysis system for calculating a maximum delay time of a signal path including a stored net. Stem. 2. A virtual wiring delay time storage means for holding a virtual wiring delay time calculated by a virtual wiring length for each net of the logic circuit, and an actual wiring delay calculated by an actual wiring length for each net of the logic circuit. The actual wiring delay time storage means for holding time, the wiring delay times in the virtual wiring delay time storage means and the actual wiring delay time storage means are compared for each net, and the actual wiring delay time is the virtual wiring at the minimum delay time. Delay time reduction net detection means for extracting nets smaller than the delay time, delay time reduction net information storage means for holding the nets extracted by the delay time reduction net detection means, and delay time reduction net information storage means Delay path calculating means for calculating the minimum delay time of a signal bus including a net Stem.