JPH09198419A - Method ad device for designing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the correction of design and to improve the efficiency by highly accurately estimating delay time in the preceding stage of performing masking pattern design. SOLUTION: The required area of a semiconductor substrate is calculated (104), the probability distribution of a wiring length is calculated (107), the probability distribution of the capacity of wiring is calculated by integrating the capacity per unit length to the wiring length (108), the distribution of the capacity of the input / output terminals of a functional block is added to the probability distribution of the capacity of the wiring and the probability distribution of the delay time of the wiring is calculated by using the characteristic data of the functional block (110). Then, the internal delay time of the functional block is added to the probability distribution of the delay time of the wiring, the probability distribution of the delay time of a signal propagation route is calculated (112), the probability that a target operating speed can not be achieved is obtained from the probability distribution of the delay time of the signal propagation route (113), the probability that the target operating speed can not be achieved is compared with a prescribed value and the result is outputted (114).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor device and an apparatus therefor, and more particularly to a method suitable for calculating a delay time of wiring at a stage before designing a mask pattern.

[0002]

2. Description of the Related Art In the case of designing a semiconductor device, the conventional method shown in FIG.
The process shown in FIG. As step 401, logic design is performed. This is a process of logically combining a plurality of functional blocks used in circuit design to realize a target operation.

Next, in step 402, before the mask pattern is designed, it is verified whether or not there is an error in the logic design based on the expected wiring. The reason for such verification is that it takes more time to design a mask pattern than other steps, and it takes time to redo the design at this stage. The point is to discover as much as possible.

When the logical error is resolved, step 40
A mask pattern is designed as 3. Here, the position and wiring of each functional block are determined on the semiconductor substrate.
Next, as step 404, logic verification is performed in actual wiring. In this step, the actual wiring determined by the mask pattern design in step 403 is used to perform highly accurate logic verification in consideration of the delay time. Each of the above steps 401 to
If there is an error in 404, the process returns to the immediately preceding process, and if the error is resolved, the process proceeds to the next process and the final step 405 is to manufacture the semiconductor device.

Here, the "logical verification" is largely divided into a first verification for judging whether it is logically correct and a second verification for judging whether it can operate at a target operation speed. Be separated. In the first verification, the delay time caused by the wiring between the functional blocks is set to a single value and it is judged whether or not it is logically correct. In the second verification, the expected time before the mask pattern design process or the actual wire determined by the mask pattern is used to analyze the delay time for each path through which the signal propagates through each logic block and the wire, and the accuracy is improved. This is a high verification. In step 402, the first and second logic verifications are performed together, and in step 404, only the second logic verification is performed.

In the step of step 402, the second verification is performed on the basis of the expected wiring so that the mask pattern design of the next step 403 does not consume unnecessary time as described above. Therefore, when performing the second logic verification based on the expected wiring, it is necessary to perform verification with the highest possible accuracy, and for that purpose, it is necessary to obtain highly accurate delay time information. However, step 40
At the stage before proceeding to the mask pattern design of No. 3, the delay time must be predicted in a state where information regarding the arrangement of the functional blocks and the connection wiring information cannot be obtained.

Conventionally, according to the procedure shown in FIG.
The delay time was calculated. As step 501,
The design value of the existing semiconductor circuit is used in advance to calculate the average value of the wiring length for each number of input / output terminals between the circuits. In step 502, the total value of the areas of the functional blocks used is calculated. In step 503, the total area of the functional blocks obtained in step 502 is used to estimate the area of the semiconductor substrate required to realize the device.

In step 505, the number of input / output terminals of the functional block connected by wiring is calculated. In step 506, using the area of the semiconductor substrate obtained in step 503 and the number of input / output terminals obtained in step 505, the length of each wiring expected at the present stage before the mask pattern design is obtained.

In step 507, the estimated wiring length obtained in step 506 is multiplied by the capacitance per unit area of the wiring to calculate the capacitance of the entire wiring. Step 508
As a result, the capacitance of the wiring as a whole is obtained by adding the parasitic capacitance of the input / output terminal to the capacitance of the wiring obtained in step 507. In step 509, the delay time caused in the wiring is calculated using the characteristics of the functional block that drives each wiring and the capacitance of the wiring obtained in step 508. Here, as the characteristic of the functional block, the conduction resistance of the transistor forming the functional block is considered.

The above steps 505 to 509
The above steps are performed for each wiring, and the process is completed for the entire wiring.

[0011]

However, with the recent advances in fine processing technology for semiconductor circuits, the wiring width has decreased, and the area available on the semiconductor substrate has also increased. For this reason, the length of the wiring connecting between the respective functional blocks also becomes long, and the ratio of the delay time caused by the wiring to the total delay time has increased. As a result, the error between the expected capacity of the wiring and the actual wiring capacity after the mask pattern design increases, and the number of cases where the delay time required by the specifications cannot be met has increased. As a result, the number of cases in which the design needs to be corrected in the subsequent mask pattern designing process is increasing, and the total design time is increased by redesigning.

Although there has been a method of estimating the wiring capacitance largely in order to prevent the design from being redone, the constraint of the delay time becomes stricter than necessary, resulting in an increase in the area of the semiconductor substrate.

The present invention has been made in view of the above circumstances, and a semiconductor device capable of reducing the design correction and improving the efficiency by estimating the delay time with high accuracy before the mask pattern design. An object is to provide a designing method and a designing device therefor.

[0014]

A semiconductor device designing method according to the present invention is a designing method for connecting a plurality of functional blocks by wiring, and the area of a semiconductor substrate required to realize the semiconductor device is obtained. And a step of calculating a probability distribution of the wiring length of each wiring connecting between the functional blocks based on the calculated area of the semiconductor substrate, and a capacitance per unit length to the calculated wiring length. The step of integrating and calculating the probability distribution of the capacity of each wiring, and the calculated probability distribution of the capacity of each wiring,
The probability distribution of the capacitance of the input / output terminals of the functional block connected to each wiring is added, and the probability distribution of the delay time of each wiring is calculated using the added value and the characteristic data of the functional block. The probability distribution of the delay time of each signal propagation path is calculated by adding the calculation step and the calculated delay time probability distribution of each wiring with the internal delay time of the functional block connected to each wiring. A step of setting a target operation speed of the semiconductor device, and a step of obtaining a probability that the set target operation speed cannot be achieved by using the calculated probability distribution of delay times of the respective signal propagation paths. ,
It is characterized in that it comprises a step of comparing the calculated probability that the target operation speed cannot be achieved with a predetermined value and outputting the comparison result.

Here, the internal delay time of the functional block to be added to the calculated probability distribution of the delay time of each wiring may be regarded as the probability distribution.

When calculating the delay time generated in the wiring, the delay time generated due to the resistance component of the wiring may be added to the delay time generated due to the capacitance.

Furthermore, using the data of the existing semiconductor device, the relationship between the area of the semiconductor substrate and the wiring length for each number of input / output terminals is obtained in advance, and the relationship between the area of the semiconductor substrate and the area of the functional block is calculated. The relationship may be obtained in advance.

A semiconductor device designing apparatus according to the present invention uses an input section for inputting data of an existing semiconductor device, an area of a semiconductor substrate, and respective input / output terminals by using the data input to the input section. A means for obtaining the relationship between the number of wirings and a means for obtaining the relationship between the area of the semiconductor substrate and the sum of the areas of the functional blocks by using the data input to the input section; Storage means for storing the relationship between the area of the substrate and the wiring length for each number of input / output terminals and the relationship between the area of the semiconductor substrate and the area of the functional blocks as a database, and a database stored in the storage means Is a calculation means for calculating the delay time of the semiconductor device by calculating the area of the semiconductor substrate required to realize the semiconductor device, and based on the calculated area of the semiconductor substrate. Then, the probability distribution of the wiring length of each wiring connecting between the functional blocks is calculated, and the capacity per unit length is added to the calculated wiring length to calculate the probability distribution of the capacity of each wiring. , The calculated probability distribution of the capacitance of each wiring is added to the probability distribution of the capacitance of the input / output terminals of the functional block connected to each wiring, and the added value and the characteristic data of the functional block are added. Then, the probability distribution of the delay time of each wiring is calculated, and the internal delay time of the functional block connected to each wiring is added to the calculated probability distribution of the delay time of each wiring. Probability distribution of delay time of propagation path is calculated, and probability of not being able to achieve a predetermined target operating speed is calculated using the calculated probability distribution of delay time of each signal propagation path. The calculation means, a comparison means for comparing the calculated probability that the target operation speed cannot be achieved with a permissible value of the probability that the target operation speed cannot be achieved, and the comparison section for comparison. The output means is provided for outputting the result obtained by the above to the outside.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

In the present invention, before designing a mask pattern, the delay time occurring in the expected wiring is taken as a probability distribution, the expected delay time in each signal propagation path is obtained, and this expected delay time is set to the target operating speed. The probability of not being satisfied is obtained and the result is output. Then, by using this result, the circuit modification is performed so that the probability that all the signal propagation paths do not satisfy the target operation speed falls within a predetermined value, thereby reducing the number of times of re-designing in the mask pattern design process. .

FIG. 1 shows the procedure of processing in the first embodiment. First, steps 101 and 102 are steps for preliminarily holding data necessary for design processing as a database. In step 101, using the design data of the existing semiconductor circuit, a probability distribution of the wiring length for each number of input / output terminals of the wiring connecting between the functional blocks with respect to the area of the semiconductor substrate is obtained. When the area of the semiconductor substrate is small, the wiring length becomes short even when the same functional block is used. On the contrary, when the area of the semiconductor substrate is large, the wiring length becomes long. Therefore, even when a semiconductor device is configured using the same functional block, the wiring length differs depending on the area of the semiconductor substrate to be realized, and therefore the relationship between the area of the semiconductor substrate and the wiring length is important. Here, the reason why the wiring length is not a fixed value but the probability distribution is is because the width of the wiring has a certain width, and this width is taken into consideration.

In step 102, the relationship between the area of the semiconductor substrate and the total value of the areas of the functional blocks to be used is obtained using the existing design data. Specifically, the relationship between the area of the semiconductor substrate and the average value of the areas of the functional blocks is obtained. The data obtained in steps 101 and 102 described above is stored in advance as a database. Then, the delay time of each semiconductor device is estimated by the processing from step 103 to step 114 below.

At step 103, the sum of the areas of the functional blocks used in the semiconductor device whose delay time is to be predicted is calculated.

In step 104, the area of the semiconductor substrate required in the semiconductor device is obtained by using the relationship between the area of the semiconductor substrate and the area of the functional block obtained in step 102.

At step 106, the number of input / output terminals of the functional block connected to the wiring of interest is obtained.

In step 107, the wiring length distribution is obtained from the area of the semiconductor substrate obtained in step 104 and the number of input / output terminals of the functional block obtained in step 106 using the database obtained in step 101. .

In step 108, step 107
The distribution of the wiring length obtained by is multiplied by the capacitance per unit length to obtain the distribution of the wiring capacitance.

In step 109, the parasitic capacitance of the number of input / output terminals is added to the wiring capacitance distribution obtained in step 108 to calculate the distribution of the total load capacitance to be driven.

In step 110, the wiring delay distribution generated when driving the entire load capacitance obtained in step 109 is obtained based on the characteristics of the functional block for driving the wiring of interest. More specifically, the conduction resistance of the transistor in the functional block connected to the wiring,
The product of the distribution of the total load capacity is calculated, and the delay time distribution is proportional to the calculated value. Step 1 above
From step 06 to step 110, step 105
As shown in, the procedure is performed for all wirings.

At step 112, the delay time distribution generated inside the functional block included in the path along which the signal propagates and the wiring delay distribution obtained at step 110 result in the entire path along which each signal propagates. Calculate the distribution of delay times.

In step 113, the probability that the wiring delay time distribution of the plurality of signal propagation paths obtained in step 112 does not satisfy the desired operation speed is obtained. Specifically, of the delay time distributions obtained in step 112, those that do not satisfy the desired target operation speed are integrated to obtain the probability.

In step 114, the signal propagation path obtained in step 113, which does not satisfy the target operating speed, but whose probability is equal to or higher than a predetermined value indicating an allowable level, is extracted and output as a final result. This output result shows a signal propagation path with a long delay time, and is used in the subsequent design process as a point to be noted such as redesigning when designing a mask pattern.

Next, the procedure for obtaining the distribution of delay times occurring in the signal propagation path will be described more specifically with reference to FIG.
The signal lines 11, 12, and 13 shown by thick lines in the drawing are
The D flip-flop 15, which is a functional block, the AND circuit 14, the inverter 16, the buffer 21, and the D flip-flop are connected to each other. The D flip-flop 15 has an output terminal Q, and the output terminal Q and the input terminal A of the AND circuit 14 are connected by the signal line 11. The output terminal Z of the AND circuit 14 and the input terminal A of the inverter 16 are connected by the signal line 12, and the output terminal Z of the AND circuit 14 and the input terminal of the buffer 21 are connected by the signal line 12. The output terminal Z of the inverter 16 and the input terminal D of the D flip-flop 17 are connected by the signal line 13. FIG. 3 shows the distribution of the wiring length when the number of input / output terminals is “2” in the database created in step 101 of FIG. 1 described above. For example, the probability that the length is 0 to 1 μm is 10%, and the probability that the length is 1 to 2 μm is 40%. Further, FIG. 4 shows the distribution of the wiring length when the number of input / output terminals is “3”. The probability that the wiring length is 1-2 μm is 20%, and the probability that it is 2-3 μm is 30%.

FIG. 5 shows the characteristics of the functional blocks as a table. As a functional block, a D flip-flop 1
5 or 17, an AND circuit 14, an inverter 16 and a buffer 21. For example, D flip-flops 15 and 17 are provided.
For example, the input terminal D has a capacitance “1” parasitic on the terminal, and the output terminal Q has a capacitance “0.5”. It is assumed that the conduction resistance is "2" and the delay time from the clock terminal CLK to the output terminal Q is "5". Here, each numerical value corresponds to a value indicating a relative size with respect to other numerical values. Then, the value shown as the conduction resistance, for example, the value "2" of the D flip-flop corresponds to a coefficient which becomes time when multiplied by the capacitance driven by the output terminal Q. Here, the capacitance per unit length of wiring is
It is assumed to be "2".

FIG. 6 shows the signal line 1 corresponding to the distribution of the wiring length.
1 shows the wiring capacitance of 1 and the total capacitance calculated using the characteristic data of the D flip-flop 15 shown in FIG. 5, the wiring delay time, and the probability. Similarly, FIG. 7 shows the wiring capacitance of the signal line 12, the total capacitance calculated using the characteristic data of the AND circuit 14 shown in FIG. 5, the wiring delay time, and the probability.
FIG. 8 shows the wiring capacitance of the signal line 13, the total capacitance calculated using the characteristic data of the inverter 16 shown in FIG. 5, the wiring delay time, and the probability.

In FIG. 6, the wiring lengths "0.5, 1.5,
"" Is an average value of the wiring lengths "0 to 1, 1 to 2, ..." in FIG. 3, and the wiring capacitance is "0.5, 1.
Is a value obtained by multiplying the capacitance "2" per unit length of wiring. Then, the wiring capacitance obtained by the multiplication is added to the capacitance parasitic on the terminal to obtain the total capacitance. That is, when the capacitance "0.5" of the output terminal Q of the D flip-flop 15 of FIG. 5 and the capacitance "1" of the input terminal A of the AND circuit 14 are added to the wiring capacitances "1, 3, ...""2.5, 4.5, ..." is obtained. This total capacity "2.
5 is multiplied by the value "2" of the conduction resistance Q in FIG. 5, the wiring delay time "5, 9, ... (ns)" is obtained. That is, the probability that the wiring length will be "0.5" is 10%,
At this time, the wiring delay time is 5 (ns) and the wiring length is "1.
5 "is 40% and the wiring delay time in this case is 9%.
(Ns).

Similarly, the obtained wiring delay time of the wiring 12 is shown in FIG. 7, and the obtained wiring delay time of the wiring 13 is shown in FIG. In the wiring 12, the probability that the average value of the wiring length is “0.5, 1.5 ...” Is “10%, 20.
%, And the capacity per unit length “2” is multiplied to obtain the wiring capacity “1, 3, ...”. In this wiring capacity,
When the total capacitance "2" of the inverter 16 and the input terminal A of the buffer 21 is added, the total capacitance "3, 5, ..."

The total capacitance is multiplied by the conduction resistance "1" of the AND circuit 14 to obtain the wiring delay time "3, 5, ...".

In the wiring 13, the average value of the wiring length is "0.
The probability of "5, 1.5 ..." Is "10%, 40%, ..." And the capacitance per unit length "2" is multiplied to obtain the wiring capacitance "1, 3, ...". If the capacitance "1" of the input terminal D of the D flip-flop 17 is added to this wiring capacitance,
The total capacity "2, 4, ..." is obtained. This total capacitance is multiplied by the conduction resistance “1” of the D flip-flop 17 to obtain the wiring delay time “2, 4, ...”.

FIG. 9 shows delay times in the signal propagation paths of the wirings 11, 12, and 13 and respective probabilities. The probability that the wiring delay time of the wiring 11 is “5 ns” is 1 from FIG.
At 0%, the probability that the wiring delay time “3 ns” will occur in the wiring 12 is 10% as shown in FIG.
The probability of occurrence of "ns" is 10% from FIG. Therefore, the probability when all such wiring delays occur is 10
(%) * 10 (%) * 10 (%) = 0.1 (%). The delay time to be finally obtained in this case is 5 + 3 + 2 = 10 (ns) in total of the wiring delay times, and 5 + 2 + 1 in total of the delay times generated inside the D flip-flop 15, the AND circuit 14, and the D flip-flop 17. =
The total value of 8 (ns) is 18 (ns).

If the target operating speed of the circuit is 20 (MHz), the delay time needs to be less than 50 (ns). The probability of a delay exceeding 50 (ns) is 50 (n
0.1% for s) and 0.05 for 52 (ns)
%, And the total is 0.15%. That is, 0.1
It can be seen that it is necessary to correct the design in the mask pattern design process with a probability of 5%.

Next, a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the internal delay time of the functional block is set to a fixed value as shown in FIG. On the other hand, the second embodiment is characterized in that the delay time generated in the functional block depends on the variation in the manufacturing process. That is, instead of adding the fixed value of the internal delay time of the functional block to the value of the wiring delay, the entire delay time is obtained by adding it as a distribution function like the wiring delay time.

The processing from step 201 to step 210 is the same as the processing from step 101 to step 110 in the first embodiment described with reference to FIG. By the processing up to step 210, the delay time generated in each wiring is calculated.

Then, the process proceeds to step 212. The distribution of delay times generated inside each functional block is obtained. That is, a plurality of values are set without setting the internal delay of the functional block to a fixed value, and the distribution is given as a distribution in which the probability of occurring for each value is given.

Then, the distribution of the delay time of the wiring obtained in step 210 and the distribution of the internal delay time of this functional block are added to obtain the distribution of the entire delay time generated for each signal propagation path. Such processing is performed for all signal propagation paths in step 211.

Subsequent steps 213 and 214 are similar to steps 113 and 114 shown in FIG.
The probability that the target operation speed is not satisfied is calculated, and when this probability exceeds a predetermined value, that fact is output so that it can be used in the subsequent mask pattern design process.

According to the second embodiment, the delay time generated inside the functional block is not fixed, but is considered as a distribution in consideration of variations in the manufacturing process. For this reason,
The delay time can be estimated with higher accuracy.

FIG. 1 shows the third embodiment of the present invention.
This will be described using the flowchart of No. 1. In the present embodiment, when the number of fan-outs is 2 or more, the resistance component exists in consideration of the difference in the delay time due to the difference in the wiring length even if it is logically the same due to the existence of the resistance component in the wiring. The feature is that the distribution of delay time due to is obtained. The fact that the delay time has a distribution due to the resistance component of the wiring is disclosed in the following document. "W. Elmore," The transien
t response of dampled liner networks with particul
ar regard to wideband amplifiers ”, Journal of App
lied Phisics, Vol. 19, pp.55-63, issued January 1948. "The effect of the resistance component of the wiring on the delay time will be described with reference to FIG. The input terminal of the inverter INV2 and the input terminal of the inverter INV3 are connected to the output terminal of the inverter INV1. Inverter INV2
And the inverter INV3 have the same logical relationship. However, the signal line from the output terminal of the inverter INV1 to the input terminal of the inverter INV2 and the inverter I
There is a difference in distance L2-L1 between the signal line from the output terminal of NV1 to the input terminal of the inverter INV3. Since the signal line has a resistance component, if the distance is different, the time required for the output of the inverter INV1 to be input to the inverter INV2 and the inverter INV3 will be different. In consideration of the delay time distribution caused by the resistance component of the wiring, the entire delay time distribution is obtained by the following procedure.

In step 301, similarly to step 101 shown in FIG. 1, using existing design data, the distribution of the wiring capacitance with respect to the area of the semiconductor substrate and the number of wiring input / output terminals can be obtained and used as a database. Leave.

Unlike step 102, step 302 uses the existing design data to determine the area of the semiconductor substrate, the number of input / output terminals, and the distribution of delay time caused by the resistance component of the wiring.

The processing from step 303 to step 305 is the same as step 102 to step 10 shown in FIG.
This is the same as the processing up to 4. Further, in steps 306 to 311 similarly to steps 105 to 110 in FIG. 1, the delay time caused by the capacitance parasitic on the wiring is obtained.

In step 312, the delay distribution caused by the resistance component of the wiring is calculated using the data calculated in step 302 as described above. Next, the delay distribution of the wiring obtained by the capacitance obtained in step 311 and the delay distribution of the wiring obtained by the resistance component obtained in step 312 are used to calculate the delay distribution of the entire wiring.

Subsequent steps 314 to 317
The processing up to is the same as the processing contents of step 111 to step 114 in FIG. 1, and outputs the result when the probability that the target operation speed is not satisfied exceeds a predetermined value.

FIG. 15 shows a schematic structure of a designing apparatus which can be used in the designing methods according to the first to third embodiments. Required data is input to the data input unit 31, and the arithmetic processing unit 32 executes the arithmetic processing of each step described above. The storage unit 33 stores, for example, the database and the like obtained in steps 101 and 102 in FIG. 1 so that it can be used in the subsequent arithmetic processing. The comparison unit 34 performs a comparison operation between the probability that the target operation speed is not satisfied and the predetermined value, which is performed in step 114 of FIG.
The calculation result output unit 35 performs an output process for reporting the result performed by the comparison unit 34 in the form of a report.

According to the above-described first to third embodiments, the probability that the delay time does not satisfy the target operation speed in any signal propagation path based on the expected wiring in the previous stage of the mask pattern design process. Can be asked.
Therefore, it is possible to reduce the number of times of re-designing in the mask pattern designing process by detecting and correcting such a signal propagation path having a high probability of correction. As a result, the time required for the entire design process is reduced and the efficiency is improved.

Further, according to the second embodiment, the delay time generated in the entire signal propagation path is calculated in consideration of the fluctuation of the internal delay time of the functional block due to the fluctuation of the manufacturing process. Highly accurate estimation is possible.

In the third embodiment, the delay time of the signal propagation path is obtained in consideration of the distribution of delay time for each input terminal caused by the resistance component of the wiring, so that the calculation accuracy can be improved.

The above-mentioned embodiments are all examples,
It does not limit the invention. For example, the functional blocks used to form the semiconductor device are not limited to those shown in FIG. 2, and the present invention can be applied to any functional block for designing. That is, the delay time can be calculated by the present invention by setting the capacitance parasitic on the terminal of the functional block to be used, the characteristic data such as the conduction resistance of the functional block, and the internal delay time of the functional block. it can.

[0059]

As described above, according to the method of designing a semiconductor device and the device therefor of the present invention, the delay time of the signal propagation path is calculated based on the expected wiring at the stage before the mask pattern design process, and the target is obtained. Since the probability of achieving the operation can be obtained, it is possible to reduce the design rework in the mask pattern design process and improve the design efficiency.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing procedure of a semiconductor device designing method according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a semiconductor device that can be designed by applying the design method.

FIG. 3 is an explanatory diagram showing a distribution of wiring lengths when the number of input / output terminals calculated by the same design method is two.

FIG. 4 is an explanatory diagram showing a distribution of wiring lengths when the number of input / output terminals calculated by the same design method is three.

FIG. 5 is an explanatory diagram showing a capacitance, a conduction resistance, and an internal delay time of a functional block obtained in the design method.

FIG. 6 is an explanatory diagram showing a distribution of wiring capacitance and delay time obtained for the signal line 11 in FIG.

7 is an explanatory diagram showing a distribution of wiring capacitance and delay time obtained for the signal line 12 in FIG.

FIG. 8 is an explanatory diagram showing the distribution of wiring capacitance and delay time obtained for the signal line 13 in FIG.

9 is an explanatory diagram showing a distribution of delay time generated in the circuit of FIG.

FIG. 10 is a flowchart showing a processing procedure of a semiconductor device designing method according to a second embodiment of the present invention.

FIG. 11 is a flowchart showing a processing procedure of a semiconductor device designing method according to a third embodiment of the present invention.

FIG. 12 is a flowchart showing a procedure of processing when designing a semiconductor device.

FIG. 13 is a flowchart showing a processing procedure in a conventional delay time calculation method.

FIG. 14 is a circuit diagram for explaining the influence of the resistance component of the wiring on the delay time in the third embodiment of the invention.

FIG. 15 is a block diagram showing a schematic configuration of a design device that can be used in the semiconductor device design methods according to the first to third embodiments of the present invention.

[Explanation of symbols]

 11-13 Signal line 14 AND circuit 15, 17 D flip-flop 16, INV1-INV3 Inverter 21 Buffer 18, 19, 20 Internal signal propagation path 31 Data input part 32 Operation processing part 33 Storage part 34 Comparison part 35 Operation result output part

Claims (5)

[Claims] 1. In a method of designing a semiconductor device in which a plurality of functional blocks are connected by wiring, a step of calculating an area of a semiconductor substrate required to realize the semiconductor device, and a step of calculating the area of the semiconductor substrate based on the calculated area. And calculating the probability distribution of the wiring length of each wiring connecting the functional blocks, and multiplying the calculated wiring length by the capacitance per unit length to obtain the probability distribution of the capacitance of each wiring. The step of calculating and the calculated probability distribution of the capacitances of the respective wirings are added with the probability distribution of the capacitances of the input / output terminals of the functional blocks connected to the respective wirings. The step of calculating the probability distribution of the delay time of each wiring by using the characteristic data and the calculated probability distribution of the delay time of each wiring. Calculating the probability distribution of the delay times of the respective signal propagation paths by adding the internal delay times of the functional blocks connected to the wiring, and setting the target operating speed of the semiconductor device, Using the probability distribution of the delay time of the signal propagation path, the step of obtaining the probability that the set target operation speed cannot be achieved, and the probability that the calculated target operation speed cannot be achieved and a predetermined value A method of designing a semiconductor device, comprising: comparing and outputting a result of the comparison. 2. A method of designing a semiconductor device in which a plurality of functional blocks are connected by wiring, the step of calculating an area of a semiconductor substrate required to realize the semiconductor device, and the step of calculating the area of the semiconductor substrate. And calculating the probability distribution of the wiring length of each wiring connecting the functional blocks, and multiplying the calculated wiring length by the capacitance per unit length to obtain the probability distribution of the capacitance of each wiring. The step of calculating and the calculated probability distribution of the capacitances of the respective wirings are added with the probability distribution of the capacitances of the input / output terminals of the functional blocks connected to the respective wirings. The step of calculating the probability distribution of the delay time of each wiring by using the characteristic data and the calculated probability distribution of the delay time of each wiring. Adding the probability distribution of the internal delay time of the functional block connected to the wiring of, calculating the probability distribution of the delay time of each signal propagation path, and the step of setting the target operating speed of the semiconductor device, Using the calculated probability distribution of the delay times of the respective signal propagation paths, obtaining a probability that the set target operation speed cannot be achieved, and a probability that the calculated target operation speed cannot be achieved and a predetermined value. A method of designing a semiconductor device, comprising: a step of comparing the values with each other; and a step of outputting the comparison result. 3. A method of designing a semiconductor device in which a plurality of functional blocks are connected by wiring, a step of calculating an area of a semiconductor substrate required to realize a semiconductor device, and a step of calculating the area of the semiconductor substrate based on the calculated area. And calculating the probability distribution of the wiring length of each wiring connecting the functional blocks, and multiplying the calculated wiring length by the capacitance per unit length to obtain the probability distribution of the capacitance of each wiring. The step of calculating and the calculated probability distribution of the capacitances of the respective wirings are added with the probability distribution of the capacitances of the input / output terminals of the functional blocks connected to the respective wirings. Using the characteristic data, the step of calculating the probability distribution of the first delay time due to the capacitance of each wiring, and the resistance component of the wiring for each wiring Using the step of calculating the probability distribution of the second delay times to be delayed, and the probability distribution of the delay times of the respective wirings using the probability distribution of the first delay time and the probability distribution of the second delay time And the internal delay time of the functional block connected to each wiring is added to the calculated probability distribution of the overall delay time of each wiring, and the probability distribution of the delay time of each signal propagation path is calculated. And a step of setting a target operating speed of the semiconductor device, and using a probability distribution of delay times of the respective calculated signal propagation paths, a probability that the set target operating speed cannot be achieved. A step of obtaining, a step of comparing the calculated probability that the target operation speed cannot be achieved with a predetermined value, and outputting a result of the comparison. A method for designing a semiconductor device characterized by the above. 4. The method for designing a semiconductor device according to claim 1, further comprising: using the data of the existing semiconductor device, the area of the semiconductor substrate and the wiring for each input / output terminal number. A step of obtaining a relationship with the length in advance, and a step of obtaining a relationship between the area of the semiconductor substrate and the area of the functional block in advance by using the data of the existing semiconductor device. Semiconductor device design method. 5. A semiconductor device designing device for connecting a plurality of functional blocks with wiring, using an input unit for inputting data of an existing semiconductor device, and data input to the input unit, A means for obtaining the relationship between the area of the semiconductor substrate and the wiring length for each number of input / output terminals, and using the data input to the input section, the area of the semiconductor substrate and the sum of the areas of the functional blocks A storage unit that stores a relational means, a relation between the obtained semiconductor substrate area and the wiring length for each number of input / output terminals, and a relation between the semiconductor substrate area and the functional block area as a database. And an arithmetic unit that calculates a delay time of the semiconductor device using a database stored in the storage unit, and calculates an area of a semiconductor substrate required to realize the semiconductor device. Then, based on the calculated area of the semiconductor substrate, the probability distribution of the wiring length of each wiring connecting between the functional blocks is calculated, and the capacitance per unit length is added to the calculated wiring length, Calculate the probability distribution of the capacitance of each wiring, add the calculated probability distribution of the capacitance of each wiring to the probability distribution of the capacitance of the input / output terminals of the functional block connected to each wiring, Using the added value and the characteristic data of the functional block, the probability distribution of the delay time of each wiring is calculated, and the calculated probability distribution of the delay time of each wiring is used to calculate the probability distribution of the delay time of each wiring. The internal delay time is added to calculate the delay time probability distribution of each signal propagation path, and the calculated delay time probability distribution of each signal propagation path is used to determine the target Comparing the calculation means for calculating the probability that the operating speed cannot be achieved with the calculated probability that the target operating speed cannot be achieved and the allowable value of the probability that the target operating speed cannot be achieved And a comparison unit for outputting the result obtained by the comparison unit to output to the outside.