JP2000194734A - Back annotation method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease pseudo timing violation at the time of timing verification by reducing the error between the circuit simulation result and cell delay information for logic simulation. SOLUTION: Based on the error between the circuit simulation result 1012 and cell delay information 1013 of gate level calculated by the approximate function thereof, delay error correction information 1015 depending on the input signal waveform rounding and output load capacity of a cell is calculated. While referring to the said delay error correction information 1015 from the input signal waveform rounding and output load capacity found at the time of delay value calculation for back annotation using layout information 1014, a delay value for back annotation is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a back annotation method for calculating a delay time of a semiconductor integrated circuit and performing delay logic simulation or timing verification.

[0002]

2. Description of the Related Art A CMOS device handbook editing committee (ed.), "CMOS Device Handbook", pages 175 to 181 of Nikkan Kogyo Shimbun (1987), describes a method for back annotation of semiconductor integrated circuits. The back-annotation method is used to detect parasitic elements such as parasitic resistance and parasitic capacitance from mask pattern information after layout design in order to discover performance problems such as timing mixed in layout design before manufacturing a semiconductor integrated circuit. It refers to a method of adding to circuit diagram information of a semiconductor integrated circuit. In addition to adding the parasitic element information to the circuit diagram information, including the method of verifying whether the circuit to which the parasitic element information is added has a problem in performance such as timing, the method is called a back annotation method. There is also.

FIG. 10 shows an example of a conventional back annotation method. In FIG. 10, 1001 is
This is a cell delay value extraction condition setting step for setting conditions such as a load capacity and an input waveform gradient for executing a circuit simulation. Reference numeral 1011 denotes a cell model such as an inverter or a flip-flop to be subjected to a circuit simulation. Reference numeral 1002 denotes a circuit simulation execution step of inputting the cell model 1011 and executing a circuit simulation for each cell based on a cell delay value extraction condition. Reference numeral 1012 denotes a circuit simulation result.
A logic simulation cell delay information calculation step 1003 calculates logic simulation delay information of each cell by fitting the circuit simulation result 1012 with an approximation function (approximate curve).
Is the calculated cell delay information. 1014 is the layout information of the logic circuit, and 1004 is the layout information 1
This is a circuit delay value calculation step of calculating a cell delay value of the logic circuit from the 014 and the cell delay information 1013. 2001 is the cell delay information 1013 and the circuit simulation result 10
This is a cell delay error coefficient information calculation step of calculating a fitting error with the coefficient 12 as a coefficient, and 2011 is delay error coefficient information obtained as a result. 1019 is temperature, voltage,
It is temperature, voltage, process and other condition dependent delay variation coefficient information that sets the effect of process and other condition variations on delay values. Reference numeral 2002 denotes delay error coefficient information 2011 and delay variation coefficient information 1019 depending on conditions such as temperature, voltage, and process.
Is a condition-dependent delay variation coefficient calculating step of calculating the delay variation coefficient based on the above, and 1016 is the delay variation coefficient calculated thereby. Reference numeral 1007 denotes a circuit delay value calculating step based on the fluctuation condition.
Circuit delay value information under the best operating condition and the worst operating condition in which the variation coefficient is considered based on Reference numeral 1017 denotes circuit delay value information calculated and generated. Reference numeral 1008 denotes the generated circuit delay value information 1017 and the netlist 1018
This is a logic simulation execution step for performing timing verification based on the above.

Next, the operation of the above conventional example will be described. In a cell delay value extraction condition setting step 1001, a combination condition of an input signal waveform and an output load capacitance and a signal measurement voltage condition are set. In the cell model 1011, various parameters such as a transistor size, a diode, a resistance, and a capacitance, and various parameters of a cell such as an inverter and a flip-flop that perform delay extraction are set. In the circuit simulation execution step 1002, a circuit simulation is executed based on the cell delay value extraction condition and the cell model, and the delay time from the input terminal to the output terminal of the cell model to be simulated is measured. The measured delay time is stored as a circuit simulation result 1012. The delay time stored as the circuit simulation result 1012 is approximated as a function of the input signal waveform and the output load capacitance by the logic simulation cell delay information calculation step 1003, and the cell delay information 1
013 is output.

FIG. 11 shows a delay time measured by a circuit simulation and an approximate curve fitted at the delay time point. In this example, the input signal waveform rounding is fitted under three conditions of 1 ns, 2 ns and 3 ns, and the output load capacitance is fitted at a total of 9 points of 1.0 pF, 2.0 pF and 3.0 pF.

In a circuit delay value calculation step 1004, delay value information of a target circuit is calculated using layout information 1014 of a circuit to be verified and cell delay information 1013 of a cell used in the circuit. The delay value information calculated here is temporary delay value information, and is corrected in the circuit delay value calculation step 1007 based on the variation condition in consideration of various delay variation conditions and errors in the cell delay information.

In a cell delay error coefficient information calculation step 2001, delay error coefficient information 2011 is generated using the circuit simulation result 1012 and the cell delay information 1013. Here, the cell delay error coefficient information calculation step 2001 will be described with reference to FIGS.

FIG. 12 is a flowchart of the cell delay error coefficient information calculation step 2001, which includes a delay approximate error measurement representative cell selection step 4001, a delay error extraction step 4002, and a maximum delay error calculation step 4003. In the delay approximation error measurement representative cell selection step 4001, a representative cell having a large error between the delay value fitted by the approximation function and the delay value by circuit simulation is determined. The characteristics of the delay time with respect to the input signal waveform of the cell and the output load capacitance depend on the number of gate stages from the input terminal to the output terminal. In the case of a single stage such as an inverter, the load increases as the rounding of the input signal waveform increases. The curvature of the curve with respect to the capacitance increases, and when there are a plurality of gate stages such as a flip-flop, the curve with the same curvature moves in parallel with the load capacitance. Therefore, since the approximate curve of the one-stage gate cell is different from the approximate curve of the multiple-stage gate cell, a typical one-stage gate cell inverter and a typical multiple-stage gate cell flip-flop are used as delay representative error measurement representative cells. select. Next, a delay error extraction step 40
In step 02, circuit simulation results of the inverters and flip-flops selected in the previous step 4001 and their approximation results are extracted.

FIG. 13 shows a curve of a delay time with respect to an input signal waveform and an output load capacitance of the inverter, wherein a broken line represents a circuit simulation result, and a solid line represents an approximate curve. FIG. 14 shows the error between the circuit simulation result of the inverter and the approximate curve in a ratio, and shows the error ratio for each rounded input signal waveform by three types of lines. FIG. 15 shows a delay time curve relating to the input signal waveform and the output load capacitance of the flip-flop. The broken line represents a circuit simulation result, and the solid line represents an approximate curve. FIG. 16 shows the error between the circuit simulation result of the flip-flop and the approximation curve as a ratio, and shows the error ratio for each rounded input signal waveform with three types of lines.

Next, a maximum delay error calculating step 40 shown in FIG.
03, the maximum plus error when the approximation result is too large and the maximum minus error when the approximation result is too small are calculated. In the results of FIGS. 14 and 16, both the maximum plus error and the maximum minus error occur in the case of the one-stage gate cell (FIG. 14), and the values are 1.1 and 0.94, respectively.

Returning to FIG. 10, in the condition-dependent delay variation coefficient calculating step 2002, the delay error coefficient information 2011 and the temperature-voltage / process-dependent condition-dependent delay variation coefficient information 1019
And a delay variation coefficient 1016 for correcting the provisional circuit delay value information generated in the circuit delay value calculation process 1004 based on
Generate There are various methods for calculating the delay variation coefficient 1016. In this case, the delay variation coefficient 1016 is calculated by multiplying each of the temperature condition-dependent delay variation coefficient, the voltage condition-dependent delay variation coefficient, and the process-dependent delay variation coefficient by a delay error coefficient. . FIG. 17 shows an example of each of these coefficients and the calculated delay variation coefficient. Although the delay variation coefficient includes a coefficient relating to the gate and a coefficient relating to the wiring, only the coefficient relating to the gate is shown here for the sake of simplicity. Further, it is assumed that there are two types of delay variation coefficients, a best operating condition coefficient and a worst operating condition coefficient. Here, the best operating condition coefficient is the lowest temperature condition coefficient within the operating standard,
The maximum voltage condition coefficient, the best process condition coefficient and the coefficient for correcting the maximum plus error of the approximation function, and the worst operating condition coefficient is the highest temperature condition coefficient within the operating standard,
This is a coefficient for correcting the minimum voltage condition coefficient, the worst process condition coefficient, and the maximum minus error of the approximation function.

Circuit delay value calculating step 100 based on fluctuation conditions
7, multiply the provisional delay value information of each cell by the best operation condition coefficient and the worst operation condition coefficient based on the provisional delay value information and the delay variation coefficient 1016 generated in the circuit delay value calculation step 1004. To calculate circuit delay value information under the best operation condition and the worst operation condition, respectively, and generate circuit delay value information 1017.

In the logic simulation execution step 1008, based on the circuit delay value information 1017 and the net list 1018 of the circuit to be subjected to the logic simulation, timing verification is performed under the best operation condition and the worst operation condition, and there is no problem in the operation timing of the circuit. Verify whether or not.

[0014]

In the above-described conventional back-annotation method for a semiconductor integrated circuit, when calculating cell delay information for logic simulation,
In practice, several to dozens of extraction conditions are determined, a circuit simulation is performed, parameters are fitted from the results, and a delay approximation function is obtained.

In such a method, since the circuit simulation requires an enormous execution time, the combination condition of the input signal waveform and the output load capacity cannot be increased unnecessarily. Also, in order to reduce the error between the approximation function and the circuit simulation result, even if the circuit simulation is performed by increasing the combination conditions of the input signal waveform and the output load capacitance, the accuracy of the approximation function for fitting is insufficient. There is a problem that an accuracy error exists. Therefore, a method of reflecting the accuracy error as a delay error coefficient when calculating a circuit delay value has been adopted, and the maximum delay error has been used as the delay error coefficient of all cells from the viewpoint of safety of timing verification.

Further, in this method, since the accuracy error due to the difference between cells is large, there is a case where the maximum delay error coefficient is calculated for each type such as a one-stage gate cell and a plurality of stages. However, since the maximum delay error coefficient is set to a constant value for the cell without considering the rounding of the input signal waveform and the difference in the output load capacitance, with the recent increase in the operation speed of the semiconductor integrated circuit, an excessively large delay error coefficient There has been a problem that a pseudo timing violation occurs during timing verification due to a difference from an actual operation speed of the semiconductor integrated circuit.

Further, in the conventional back-annotation method for a semiconductor integrated circuit, the speed reduction due to aging of the transistor has not been taken into account. However, the rounding of the input signal waveform due to the recent miniaturization of the semiconductor integrated circuit and the improvement of the operating frequency has been considered. Due to the synergistic effect of the increase in the number of switching times and the intermediate potential state time near the threshold voltage, the operating speed after aging due to deterioration of the input stage transistor due to hot carriers is concerned.

According to the present invention, a delay error coefficient relating to a circuit simulation result and cell delay information for logic simulation is not made to be a uniform value for a cell, but depends on a rounded input signal waveform or a difference in output load capacitance. The purpose of the present invention is to reduce the number of pseudo timing violations during timing verification.

The present invention also provides a back annotation method which can ensure the reliability of the operation speed even after aging by considering the clock frequency and the rounding of the input signal waveform at the clock input pin of the flip-flop. Is also aimed at.

[0020]

In order to solve the above-mentioned problems, a first aspect of the present invention is a circuit simulation execution step, and cell delay information for calculating gate level cell delay information by parameter fitting using an approximate function. This method employs a back annotation method including a calculation step and a correction step of correcting an error between the calculated cell delay information and the circuit simulation result in accordance with two parameters of the input signal waveform rounding and the output load capacitance. .

Further, according to the present invention, there is provided a delay value correcting portion specifying step for specifying a cell and a flip-flop on a clock line in a logic circuit to be subjected to timing verification; The input signal waveform rounding at the specified location is calculated from the cell delay information, and the delay value at the specific location is operated based on the cell-specific deterioration correction information and the clock frequency information depending on the input signal waveform rounding. The back annotation method further includes a correction step of correcting the delay value after speed degradation.

[0022]

FIG. 1 shows a first embodiment of a back annotation method according to the present invention. In FIG. 1, reference numeral 1001 denotes a cell delay value extraction condition setting step;
11, a cell model; 1002, a circuit simulation execution step; 1012, a circuit simulation result;
3 is a logic simulation cell delay information calculation step, 1
013 is cell delay information, 1014 is logic circuit layout information, and 1004 is a circuit delay value calculation step. 100
Reference numeral 5 denotes an input signal rounding-corresponding cell delay error correction information calculating step for calculating delay error correction information depending on input signal rounding and output load capacity at the time of calculating cell delay value information.
015 is the generated delay error correction information. 1006
Is an input signal rounding circuit delay value correction step for correcting the cell delay error included in the temporary delay value information calculated in the circuit delay value calculation step 1004 using the delay error correction information 1015. Reference numeral 1019 denotes delay variation coefficient information depending on conditions such as temperature, voltage, and process. 1009 is the temperature
A condition-dependent delay variation coefficient calculating step 1016 of calculating a delay variation coefficient using the voltage-process and other condition-dependent delay variation coefficient information 1019 is a calculated delay variation coefficient. 1
007 is a circuit delay value calculating step based on the fluctuation condition, 1017
Denotes circuit delay value information calculated / generated, 1018 denotes a net list, and 1008 denotes a logic simulation execution step.

The operation of the back annotation method for a semiconductor integrated circuit as described above will be described below. Note that reference numerals 1001, 1002, 1003, and 10 in FIG.
04, 1007, 1008, 1011, 1012, 10
13, 1014, 1016, 1017, 1018 and 1
019 is the same as the conventional example with the same reference numerals in FIG.

FIG. 2 is a flowchart of an input signal rounding-corresponding cell delay error correction information calculating step 1005. It is. In FIG. 2, reference numeral 4001 denotes a delay approximation error measurement representative cell selection step;
4002 is a delay error extraction step, 4101 is a step 4001
A representative cell and each cell correspondence information generation step for making a correspondence between the type of the representative cell selected in step 4 and all cells, a determination step 4102 for determining that all the processes of the selected representative cell have been completed, and a reference cell step 4103 for the representative cell This is a step of generating delay error correction information for each input signal rounding and output load capacitance. Next, the operation will be described. However, 4001 and 4002 in FIG. 2 are the same as those of the conventional example denoted by the same reference numerals in FIG. Here, as in the conventional example, it is assumed that an inverter, which is a typical one-stage gate cell, and a flip-flop, which is a typical multi-stage gate cell, are selected as delay approximate error measurement representative cells. Note that the types of representative cells may be plural or all cells may be representative cells. Next, the correspondence information generation step 4 between the representative cell and each cell
At 101, a correspondence table between a representative cell and each cell is generated so that delay error correction corresponding to each cell can be performed at the time of circuit delay value correction. FIG. 3 shows an example of the generated correspondence table. This table is stored in the delay error correction information 1015 and is referred to in the circuit delay value calculation step 1007 based on the fluctuation condition.

Next, the delay error extraction step 4002 and the delay error correction information generation step 4103 for each rounded input signal and output load capacity are repeated until delay error correction information for all representative cells is generated. In the present embodiment, the description is repeated for two types of inverters and flip-flops. The delay error information of each of the inverter and the flip-flop extracted in the delay error extraction step 4002 is as shown in FIGS. Figure 4 shows the inverter
FIG. 5 shows delay error correction information for each input signal rounding and output load capacitance of the flip-flop. The index of the output load capacitance in FIGS. 4 and 5 is an output load capacitance value at which the error coefficient is 1, that is, the error is 0, and the error coefficient is inverted from this value. Here, the inversion of the error coefficient means that the value of the approximation function is larger than that of the circuit simulation result, and that the value of the approximation function is smaller than that of the circuit simulation result. It means the opposite. In this embodiment,
The range of the rounding of the input signal waveform and the maximum output load capacitance value are limited based on the approximation accuracy of the delay value, and three types of rounding of the input signal waveform and the maximum output load capacitance value are 5 pF.
Also, the delay error correction tables in FIGS. 4 and 5 are created by specifying the number of times that the error coefficient is inverted to be 4 or less, but if the number of times of the inversion is large under the limitation of the maximum output load capacitance value, The index of the output load capacity may be determined by the number of times.

Here, the correction coefficient of this embodiment is determined for each load capacity range in which the inversion does not occur, and is the reciprocal of the maximum error coefficient within each output load capacity range.
For example, in the example of the inverter shown in FIG. 4, the correction coefficient becomes 1 / 0.98 when the output load capacitance is 0 or more and less than 0.4 pF when the input signal waveform is 1 ns, and
In the case of 0.4 pF or more and less than 1.5 pF, 1/1.
03, which is 1 / 0.97 in the case of 1.5 pF or more and less than 5 pF. In the example of the flip-flop shown in FIG. 5, the correction coefficient is 1 ns when the input signal waveform is 1 ns.
When the output load capacitance is 0 or more and less than 0.1 pF, 1 /
1.01 and less than 0.1 pF and less than 1.9 pF, it is 1 / 0.97, which is more than 1.9 pF and 3.
If it is less than 8 pF, it becomes 1 / 1.00 and 3.8 pF.
In the case of above and less than 5.0 pF, it becomes 1 / 0.99.

If the correspondence table 1101 of FIG. 2 and the delay error correction tables (FIGS. 4 and 5) of all the representative cells are created and the delay error correction information 1015 is generated, the input signal rounding cell delay error correction can be performed. The information calculating step 1005 is completed, and then the input signal rounding circuit delay value correcting step 10
Proceed to 06.

Circuit for correcting rounding of input signal delay value 1
In 006, the delay value is corrected for each cell while focusing on one cell at a time. Here, an example in which the delay of the inverter cell is corrected will be described. First, focusing on cells,
With reference to the correspondence table shown in FIG. 3, the delay error correction table (FIG. 4) of the representative cell is extracted from the representative cell name corresponding to the cell. Then, the delay value is corrected by multiplying the correction coefficient by the rounded input signal waveform and the output load capacity of the inverter. Note that the input signal waveform rounding and the output load capacitance are calculated from the layout information 1014 and the cell delay information 1013 using an existing technique.

Here, the case where the combination of the input signal waveform rounding and the output load capacity is the three cases shown in FIG. 6 will be described as an example. FIG. 7 shows a circuit simulation result of the inverter and an approximate curve thereof. According to this, the delay value of the circuit simulation result is 0. 0 in case A.
75 ns, 1.27 ns in case B, and 1.10 ns in case C. The delay value calculation results before correction obtained from the approximate curve are 0.78 ns and 1.23 ns, respectively.
s, 1.11 ns.

The delay value calculation result before the correction is compared with the delay error correction table shown in FIG. 4 by using a table lookup method as a conventional technique (here, a correction coefficient having an input signal waveform rounding and an output load capacity as indexes). , A correction coefficient is calculated and a delay value is corrected. FIG. 8 shows the delay value of the circuit simulation result, the correction result in the present embodiment, the correction result under the best condition and the correction result under the worst condition of the conventional example. Here, the correction result under the best condition of the conventional example is obtained by multiplying the delay value calculation result before correction obtained from the approximate curve by the reciprocal of the maximum plus error shown in FIG. The correction result is shown in FIG.
4 multiplied by the maximum minus error.

After completion of the input signal rounding circuit delay value correcting step 1006, a circuit delay value calculating step 1007 based on a variation condition is executed as in the conventional example, but before that, a condition corresponding delay variation coefficient calculating step 1009 is performed. By
It is necessary to find a delay variation coefficient that depends on conditions such as temperature, voltage, and process. Here, in the condition-dependent delay variation coefficient calculation step 1009, the calculation is performed excluding the delay error coefficient in FIG. The calculated result is the delay variation coefficient 101
6 is generated. Subsequent steps 1007, 1008
Is the same as the operation described in the conventional example.

FIG. 9 shows a second embodiment of the back annotation method according to the present invention. In FIG.
1001 is a cell delay value extraction condition setting step, 1011 is a cell model, 1002 is a circuit simulation execution step,
1012 is a circuit simulation result, 1003 is a logic simulation cell delay information calculation step, 1013 is cell delay information, 1014 is logic circuit layout information,
Reference numeral 1004 denotes a circuit delay value calculating step, 1005 denotes an input signal rounding-corresponding cell delay error correction information calculating step, 1015 denotes delay error correction information, and 1006 denotes an input signal rounding-corresponding circuit delay value correcting step. Reference numeral 1702 denotes a delay value correction location specifying step for searching a clock pin of a flip-flop connected to the external clock or internal clock of the logic simulation target circuit, and reference numeral 1711 denotes a cell to which the clock pin specified by the delay value correction location specifying step 1702 belongs. 1712 is cell-specific deterioration correction information for assuming a state in which the operation speed has decreased over time due to the rounding of the input signal waveform, and 1713 is the logic simulation target circuit. Clock frequency information 1701 is a specific location delay value correction process. Reference numeral 1019 denotes delay variation coefficient information depending on conditions such as temperature, voltage, process, etc .; 1009, a condition-dependent delay variation coefficient calculation step; 1016, a generated delay variation coefficient; 1007, a circuit delay value calculation step based on variation conditions;
017 is generated circuit delay value information, 1018 is a net list, and 1008 is a logic simulation execution step.

The operation of the above-described back annotation method for a semiconductor integrated circuit will be described below. Note that reference numerals 1001, 1002, 1003, and 10 in FIG.
04, 1005, 1006, 1007, 1008, 10
09, 1011, 1012, 1013, 1014, 10
15, 1016, 1017, 1018 and 1019 are
1 and 10 are the same as those in FIGS. 1 and 10, and a description thereof will be omitted.

In the delay value correction point specifying step 1702, the net list 1018 is searched from the designated external clock pin or internal clock to the input pin of the flip-flop, and delay value correction point information 1711 is generated. The specific location delay value correction step 1701 includes delay value correction location information 171.
1, cell-specific degradation correction information 1712, clock frequency information 1713, layout information 1014, and cell delay information 1013. And layout information 1
014 and the cell delay information 1013 to calculate the rounding of the input signal waveform at the clock pin of the flip-flop,
By extracting a deterioration correction coefficient corresponding to the cell type of the flip-flop and depending on the rounding of the input signal waveform from the cell-specific deterioration correction information 1712, and multiplying the extracted correction coefficient by the input clock frequency, the clock pin of the flip-flop is extracted. Is corrected to the delay value after deterioration. However, since the delay value after deterioration is generated for performing timing verification when the operation speed is reduced, the circuit delay value information to be corrected here is only the worst condition. The circuit delay value information 1017 after aging is generated by the above-described specific location delay value correction step 1701, and the logic simulation execution step 100 is performed as in the first embodiment.
8, the timing verification is performed. This makes it possible to perform timing verification assuming aging.

Although the timing verification is performed in the logic simulation execution step 1008 in each of the above embodiments, the timing verification may be performed using a static timing verification tool. Although the circuit delay value calculating step 1004 and the input signal rounding-corresponding circuit delay value correcting step 1006 are executed separately, they may be executed as one step.

[0036]

As described above, according to the first aspect of the present invention, since the correction according to the error between the result of the circuit simulation and the approximation function can be accurately performed, the circuit simulation result and the gate-level cell delay information can be obtained. Margin can be reduced, and a remarkable effect that pseudo timing violation at the time of timing verification can be reduced can be obtained. In addition, since the correction is performed in consideration of the two parameters of the input signal waveform rounding and the output load capacitance, even if the output load capacitance of the delay value extraction condition is increased, it is possible to suppress the accuracy error due to the approximation function. A remarkable effect that timing design at the time of designing an integrated circuit is facilitated is obtained.

According to the second aspect of the present invention, by considering the rounding of the input signal waveform and the operating clock frequency, it is possible to perform reliability timing verification on the assumption that the operation speed is reduced due to aging of the flip-flop. The effect is obtained.

[Brief description of the drawings]

FIG. 1 shows a first example of a back annotation method according to the present invention.
5 is a flowchart showing an embodiment of the present invention.

FIG. 2 is a detailed flowchart of an input signal rounding-corresponding cell delay error correction information calculating step in FIG. 1;

FIG. 3 is an explanatory diagram showing an example of a correspondence table obtained in a correspondence information generation step of a representative cell and each cell in FIG. 2;

4 is an explanatory diagram showing an example of a delay error correction table of an inverter obtained in a delay error correction information generating step for each input signal rounding and output load capacitance in FIG. 2;

5 is an explanatory diagram showing an example of a delay error correction table of a flip-flop obtained in a delay error correction information generation step for each input signal rounding and output load capacitance in FIG. 2;

FIG. 6 is an explanatory diagram showing three examples of a combination of the rounding of the input signal waveform of the inverter and the output load capacitance.

FIG. 7 is an explanatory diagram showing a circuit simulation result of an inverter extracted in a delay error extracting step in FIG. 2 and an approximate curve thereof.

8 is an explanatory diagram showing the results of the delay value correction by the input signal rounding delay circuit correction value correction process in FIG. 1 according to the three examples of FIG. 6 in comparison with the delay value correction results of the conventional example.

FIG. 9 shows a second example of the back annotation method according to the present invention.
5 is a flowchart showing an embodiment of the present invention.

FIG. 10 is a flowchart showing an example of a conventional back annotation method.

11 is an operation explanatory diagram of a logic simulation cell delay information calculating step in FIG. 10;

FIG. 12 is a detailed flowchart of a cell delay error coefficient information calculation step in FIG. 10;

13 is an explanatory diagram showing an example of inverter information extracted in a delay error extraction step in FIG.

FIG. 14 is an explanatory diagram of a maximum plus error and a maximum minus error in the circuit simulation result of FIG. 13 and its approximate curve.

15 is an explanatory diagram illustrating an example of flip-flop information extracted in a delay error extraction step in FIG.

FIG. 16 is an explanatory diagram of a maximum plus error and a maximum minus error in a circuit simulation result of FIG. 15 and an approximate curve thereof.

FIG. 17 is an explanatory diagram showing a table including a delay variation coefficient in FIG. 10;

[Explanation of symbols]

1001 Cell delay value extraction condition setting step 1002 Circuit simulation execution step 1003 Logic simulation cell delay information calculation step 1004 Circuit delay value calculation step 1005 Input signal rounding corresponding cell delay error correction information calculating step 1006 Input signal rounding corresponding circuit delay value correction step 1007 Circuit delay value calculation process based on fluctuation condition 1008 Logic simulation execution process 1011 Cell model 1012 Circuit simulation result 1013 Cell delay information 1014 Layout information 1015 Delay error correction information 1016 Delay variation coefficient 1017 Circuit delay value information 1018 Netlist 1019 Temperature / voltage / Process-dependent condition-dependent delay variation coefficient information 1701 Specific location delay value correction step 1702 Delay value correction location identification step 1711 Delay value correction location information 1 712 Degradation correction information for each cell 1713 Clock frequency information 4001 Delay approximation error measurement representative cell selecting step 4002 Delay error extracting step 4101 Generating corresponding information of representative cell and each cell 4102 Processing end determining step for all selected cells 4103 Input signal rounding And delay error correction information generation process for each output load capacity

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G06F 15/60 668S H01L 21/82 TF term (Reference) 2G032 AD07 5B046 AA08 JA05 5F064 BB07 BB19 EE42 EE43 EE47 EE54 HH06 HH09 HH10

Claims (2)

[Claims] 1. A circuit simulation execution step, a cell delay information calculation step of calculating gate-level cell delay information by parameter fitting using an approximation function, and an error between the calculated cell delay information and the circuit simulation result is input to an input signal. A back annotation method for a semiconductor integrated circuit, comprising: a correction step of correcting according to two parameters of a waveform rounding and an output load capacitance. 2. A delay value correction location specifying step of specifying a cell and a flip-flop on a clock line in a timing-verification target logic circuit; and determining the delay value correction location based on layout information of the logic circuit and delay information of a cell in the logic circuit. The input signal waveform rounding at the specified location is calculated, and the delay value at the specific location is converted to the delay value after the operation speed is deteriorated, based on the cell-based deterioration correction information and the clock frequency information depending on the input signal waveform rounding. 2. The method according to claim 1, further comprising:
7. A back annotation method for a semiconductor integrated circuit according to claim 1.