WO2005119527A1 - Back annotation equipment, mask layout correcting equipment, back annotation method, program, recording medium, process for fabricating semiconductor integrated circuit - Google Patents

Abstract

Back annotation equipment for specifying the delay value of a logic cell employed in timing simulation while considering variation in characteristics of a transistor element arranged at a position overlapping the electrode pad of a semiconductor integrated circuit. The back annotation equipment comprises a storage means for storing mask layout information including positional information on the electrode pad and the logical cell of the semiconductor integrated circuit, a decision means for making a decision whether the logical cell is arranged at a position overlapping the electrode pad or not according to the mask layout information, and a selection means for selecting the delay value of the logic cell depending on the decision results obtained by the decision means.

Description

 Specification

 Back-annotation apparatus, mask layout correction apparatus, back-annotation method, program, recording medium, and semiconductor integrated circuit manufacturing method

 Technical field

 The present invention relates to a technology for designing a semiconductor integrated circuit, and more particularly, to a technology for performing back annotation and mask layout correction in consideration of a change in characteristics of a transistor element included in the semiconductor integrated circuit.

 Background art

 [0002] In general, a semiconductor integrated circuit is designed in the order of a functional design, a logical design, and a layout design, and a simulation is performed to perform operation verification at each design stage.

 In the timing simulation performed after the layout design, timing information that is information related to signal delay that can be specified from the mask layout information created in the layout design is used, and the specified timing information is reflected in the timing simulation. The timing simulation performed by reflecting the timing information or the timing information is called back annotation.

[0003] An example of a conventional invention relating to back annotation is a back annotation method disclosed in Patent Document 1 below.

 By the way, with the recent increase in the number of functions of semiconductor integrated circuits, the number of electrode pads used for input and output of each function provided on the outer layer of the semiconductor integrated circuit has been increasing. Despite this, there was a problem that the size had to be increased.

 [0004] Therefore, as in the semiconductor device disclosed in Patent Document 2 below, the above problem is caused by arranging the transistor element also in the position of the inner layer overlapping the position of disposing the electrode pad which has not been conventionally used. It is thought that it is possible to solve.

 Patent Document 1: JP 2000-194734

Patent Document 2: Patent No. 2559102 Disclosure of the invention

 Problems to be solved by the invention

 [0005] The applicant of the present application has been developing an integrated circuit in which a transistor element is arranged at a position overlapping with an arrangement position of an electrode pad, and as a part of the development, the characteristics change when pressure is applied to the transistor element. An experiment was performed to determine if there was.

 As a result, it was confirmed that when a certain amount of pressure was externally applied to the transistor element, the characteristics thereof changed. Here, the certain pressure is a pressure at which the transistor element is not broken.

 [0006] Further, a logic cell including a transistor element arranged in a position overlapping with an electrode pad of a semiconductor integrated circuit differs from a normal propagation delay time due to the influence of pressure applied to the electrode pad. It was also confirmed by experiment that the value was obtained.

 In view of the above, the present invention relates to a back-notation device that specifies a delay value that is a value corresponding to a propagation delay time of a logic cell used in timing simulation, in consideration of the above-described change in transistor characteristics, and to the device. A first object is to provide various techniques, and a second object is to provide a mask layout correction apparatus that corrects mask layout information in consideration of the above-mentioned change in transistor characteristics. A third object is to provide a method of manufacturing a semiconductor integrated circuit in consideration of a change in transistor characteristics. Means for solving the problem

 [0007] In order to achieve the first object, a back annotation apparatus according to the present invention comprises a storage unit for storing mask rate information including positional information of each of an electrode pad and a logic cell of a semiconductor integrated circuit. Identification means for identifying whether or not the logic cell is arranged at a position overlapping with the electrode pad based on the mask layout information; and the logic cell according to a result identified by the identification means. And a selecting means for selecting the delay value.

 The invention's effect

[0008] When the back annotation device having the above configuration is used, the delay value of the logic cell is selected depending on whether or not the logic cell is located at a position overlapping the electrode pad. It is possible to accurately simulate the operation timing of a semiconductor integrated circuit in which a transistor element is arranged at a certain position. The situation can be minimized.

 [0009] Further, in the back annotation apparatus having the above configuration, the storage means further includes a first delay value which is a delay value when the logic cell is arranged at a position not overlapping with the electrode pad. And a second delay value that is a delay value when the logic cell is arranged at a position overlapping with the electrode pad, and the selecting unit stores the second delay value in accordance with a result identified by the identifying unit. One of the first delay value and the second delay value stored in the storage means may be selected as the delay value of the logic cell, and the second delay value may be a magnitude of the pressure applied to the electrode pad. The pressure may be a value that changes according to the pressure, and the pressure is a pressure at the time of contacting an electrode pad of a probe used for electrical characteristic inspection in a manufacturing stage where the semiconductor integrated circuit is in a wafer state. As Is also good.

 [0010] Further, in the back annotation apparatus having the above configuration, the storage means further includes: a first delay value that is a delay value when the logic cell is arranged at a position that does not overlap the electrode pad; A coefficient used for calculating a second delay value, which is a delay value when the logic cell is arranged at a position overlapping with the electrode pad, is stored, and the selecting unit stores the result identified by the identifying unit. According to the above, one of the first delay value stored in the storage means and the second delay value obtained by the operation using the coefficient may be selected as the delay value of the logical cell, The coefficient may be a coefficient used for a calculation for obtaining a second delay value that changes according to the magnitude of the pressure applied to the electrode pad.

 [0011] Further, in the back-annotation device having the above configuration, the semiconductor integrated circuit has a multi-layer structure, and the identification means is further arranged at a position where the logic cell overlaps with the electrode pad. In this case, the number of wiring layers constituting the semiconductor integrated circuit may be identified, and the selection unit may select the delay value of the logic cell according to all results identified by the identification unit. ,.

According to this configuration, the logic cell is arranged together with the logic cell overlapping the electrode pad. It is also possible to identify the number of wiring layers to be selected, and to reliably select a delay value of the logic cell that depends on the number of wiring layers.

 Further, in the back annotation apparatus having the above configuration, the storage means further includes a delay value when the logical cell is arranged at a position where the logical cell does not overlap the electrode pad, and a delay value when the logical cell overlaps the electrode pad. A delay value in the case of being arranged, and a delay value associated with the number of each wiring layer is stored, and the selecting unit determines the delay value according to all results identified by the identifying unit. It is also possible to select one of the delay values stored in the storage means or the delay as the delay value of the logic cell.

 [0013] Further, in the back-annotation apparatus having the above configuration, the storage means further includes: a delay value when the logic cell is arranged at a position not overlapping with the electrode pad; The coefficients used for the calculation for obtaining the delay value when they are arranged in a position overlapping with the number of wiring layers and the coefficients associated with the number of wiring layers are stored. In accordance with all the results identified by the identification means, each of the delay values stored in the storage means and each of the delay values and the numbers obtained by calculation using the coefficients in association with the number of wiring layers. Any of the delay values may be selected as the delay value of the logic cell.

 [0014] Further, in the back annotation apparatus having the above configuration, when the logical cell is arranged at a position overlapping the electrode pad, the identification means may further determine the degree of overlap between the logical cell and the electrode pad. The identifying means may select the delay value of the logic cell according to all the results identified by the identifying means.

 Further, in the back annotation apparatus having the above configuration, the storage means may further include a delay value when the logic cell is arranged at a position where the logic cell does not overlap the electrode pad, and the delay value of the logic cell and the electrode pad. Storing the delay value associated with each overlap condition, which is a delay value in the case of being disposed at a position overlapping with the overlap condition, wherein the selection unit stores all of the identification values identified by the identification unit. According to the result, any one of the delay values stored in the storage means may be selected as the delay value of the logic cell.

[0015] With this configuration, different delay values can be reliably obtained depending on the degree of overlap between the electrode pad and the logic cell. Can be selected.

 Further, in the back annotation apparatus having the above configuration, the storage means may further include a delay value when the logic cell is arranged at a position where the logic cell does not overlap the electrode pad, and the delay value of the logic cell and the electrode pad. And a coefficient associated with each degree of overlap, which is used in an operation for calculating a delay value in the case of being placed at an overlapped position according to the degree of overlap, and the selecting means identifies by the identifying means In accordance with the result, any one of the delay value stored in the storage means and each of the delay values obtained by the operation using the coefficient associated with each degree of overlap is stored in the logic cell. A delay value may be selected, and the degree of overlap means that the pad and the n-type transistor area of the logic cell overlap, and the pad and the p-type transistor area of the logic cell overlap. Tsu state, the state in which all pads and logic cells overlap may be the one of the following states.

[0016] Further, the mask layout correcting apparatus according to the present invention includes a storage means for storing mask layout information including positional information of each of an electrode pad and a logic cell of a semiconductor integrated circuit; When the logic cell is arranged at a position that partially overlaps with the electrode pad, the position of the logic cell is set so as to be a force that does not completely overlap the electrode pad or a position that completely overlaps the electrode pad. It is characterized by comprising a correcting means for correcting the mask layout information.

Using the mask layout correction apparatus having the above configuration, the arrangement positions of the logical cells constituting the semiconductor integrated circuit are: (1) positions that do not completely overlap with the electrode pads, or (2) positions that completely overlap with the electrode pads. Therefore, it is not necessary to specify different delay values depending on the degree of overlap between the electrode pad and the logic cell. In other words, it is only necessary to be able to specify the delay value of the logic cell when it is located in either of the above (1) or (2). Therefore, it is necessary to minimize the information necessary to specify the delay value. Can

Further, the mask layout correcting apparatus according to the present invention includes a storage unit for storing mask layout information including positional information of each of an electrode pad and a logic cell of a semiconductor integrated circuit; An identification means for identifying whether the logic cell is disposed at a position overlapping the electrode pad, and a connection identified by the identification means. Selection means for selecting a delay value of the logic cell according to the result, timing simulation means for performing timing simulation using the delay value of the logic cell selected by the selection means, and a timing simulation result. And correcting means for correcting the mask layout information, which changes a layout of a logic cell arranged at a position not overlapping with the electrode pad to a position overlapping with the electrode pad.

 With the use of the mask layout correction device having the above configuration, the operation timing of a semiconductor integrated circuit in which a transistor element is arranged at a position overlapping with an electrode pad is accurately simulated, and a fine mask layout report is corrected based on the simulation result. Therefore, it is possible to minimize a situation that occurs when a timing defect due to a change in the characteristics of the transistor element at a position overlapping with the electrode pad is found after the manufacture of the semiconductor integrated circuit.

 [0020] Further, the mask layout correcting apparatus according to the present invention includes a storage means for storing mask layout information including positional information of each of an electrode pad and a logic cell of a semiconductor integrated circuit; Correction means may be provided for performing a correction for adding a buffer to the mask layout information for absorbing a difference between delay values that are different depending on whether the mask layout information is arranged or not.

 Further, the back annotation method according to the present invention is characterized in that the logic cell is connected to the electrode pad based on mask layout information including positional information of each of the electrode pad and the logic cell of the semiconductor integrated circuit. An identification step of identifying whether or not the logic cell is arranged at an overlapping position; and a selection step of selecting a delay value of the logic cell according to a result identified in the identification step.

 [0022] The program according to the present invention is a program for causing a computer to execute knock annotation processing, wherein the back annotation processing is performed for each of an electrode pad and a logic cell of the semiconductor integrated circuit. An identification step of identifying whether or not the logic cell is arranged at a position overlapping the electrode pad based on mask layout information including position information, and the logic step according to a result identified in the identification step. And selecting a delay value of the cell.

Further, the recording medium according to the present invention is a computer-readable recording medium recording a program for causing a computer to execute a knock annotation process, The annotation processing is a step of identifying whether or not the logic cell is arranged at a position overlapping with the electrode pad based on mask layout information including position information of each of the electrode pad and the logic cell of the semiconductor integrated circuit. And a selecting step of selecting a delay value of the logic cell in accordance with a result identified in the identifying step.

 Further, in the method of manufacturing a semiconductor integrated circuit according to the present invention, the logical cell may be connected to the electrode pad based on mask layout information including positional information of each of the electrode pad and the logic cell of the semiconductor integrated circuit. The identification step of identifying whether or not they are arranged in an overlapping position, and selecting the delay value of the logic cell according to the result of the identification in the identification step and the selection step. A simulation step of performing a timing simulation of the semiconductor integrated circuit using the delay value of the selected logic cell; and correcting the mask layout information based on a result of the timing simulation performed in the simulation step. Correcting the semiconductor integrated circuit based on the mask layout information corrected in the correcting step. Characterized that you and a manufacturing step for forming.

 If a semiconductor integrated circuit in which transistor elements are arranged at positions overlapping electrode pads by the above manufacturing method is manufactured, operation timing is accurately simulated, and mask layout information is obtained based on the simulation result. Is corrected, it is possible to minimize a situation where a timing defect due to a change in the characteristics of the transistor element located at a position overlapping with the electrode pad is found after the manufacture of the semiconductor integrated circuit.

 Brief Description of Drawings

 FIG. 1 is a layout diagram of electrode pads of a semiconductor integrated circuit 1 to be designed.

 FIG. 2 is a view for explaining a bonding step between the semiconductor integrated circuit 1 and the liquid crystal panel 3.

 FIG. 3 is a view showing a bonding state between a semiconductor integrated circuit 1 and a liquid crystal panel 3 bonded by ACF2.

 FIG. 4 is a layout diagram of a POE arranged at a position indicated by a dotted square portion 12 in FIG.

FIG. 5 is a diagram showing a part of a logic circuit of the semiconductor integrated circuit 1. FIG. 6 is a signal timing diagram.

 FIG. 7 is a functional block diagram of the back annotation device.

 FIG. 8 is a diagram showing a specific example of a logical netlist.

 FIG. 9 is a diagram showing an example of a logical netlist in which a logical cell name has been rewritten.

 [FIG. 10] In a mounted state of a multilayered semiconductor integrated circuit 1A, the semiconductor integrated circuit

FIG. 3 is a diagram showing a pressure applied to a 1A electrode pad 111A.

 FIG. 11 is a functional block diagram of a back annotation apparatus according to a first modification.

 FIG. 12 is a diagram showing an example of a logical netlist in which a logical cell name has been rewritten.

 FIG. 13 is a diagram showing an example in which electrode pads and logic cells overlap.

 FIG. 14 is a functional block diagram of a back annotation device according to a second modification.

 FIG. 15 is a diagram showing an example of rewriting of a logical netlist 102.

 FIG. 16 is a diagram used to describe a specific example of a mask layout correction process.

 FIG. 17 is a logic circuit diagram in which a buffer is inserted by the mask layout correction device.

 FIG. 18 is a view showing a process flow of a method for manufacturing a semiconductor integrated circuit according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1

 Hereinafter, a back annotation device according to an embodiment of the present invention will be described with reference to the drawings.

 Here, the back annotation device means a functional unit that realizes a back annotation function, which is one function of a CAD (Computer Aided Design) system used for designing a semiconductor integrated circuit.

[0028] The CAD system is a so-called computer composed of a storage device such as a CPU, a memory and a hard disk, and an input / output device and hardware, and executes a CAD system program stored in the storage device. As a result, various functions of the CAD system are realized.

 <Semiconductor integrated circuit>

Before describing the back annotation device, first, the semiconductor integrated circuit 1 to be designed will be described. FIG. 1 is a layout diagram of the electrode pads of the semiconductor integrated circuit 1.

 Six electrode pads 11 are arranged on the outer layer of the semiconductor integrated circuit 1 shown in FIG.

. Then, a logic cell is arranged at a position on the inner layer of the semiconductor integrated circuit 1, which is a position overlapping with the electrode pad 11 indicated by the dotted square portion 12.

 A logic cell is also called a gate and refers to an electronic circuit having a logic expression function such as AND, ΔR, and NOT.

 Hereinafter, a logic cell arranged at a position overlapping with an electrode pad as shown in FIG. 3 is referred to as P〇E (Pad On Element).

 Here, the mounting state of the semiconductor integrated circuit 1 will be described. FIG. 2 is a diagram for explaining a bonding process between the semiconductor integrated circuit 1 and the liquid crystal panel 3.

 As shown in FIG. 1, the semiconductor integrated circuit 1 is bonded to the liquid crystal panel 3 using ACF (Anisotropic Conductive Film: also called anisotropic conductive film) 2.

 [0031] ACF2 is an adhesive mainly composed of a thermosetting resin, and contains conductive particles having a size of about 3 to 5 µm dispersed therein.

 By heating and pressing each electrode of the semiconductor integrated circuit 1 and the liquid crystal panel 3 with the ACF2 sandwiched, the resin hardens and the distance between each electrode is reduced (5 / m or less),

The conductive particles contained in ACF2 ensure conduction between the electrodes.

FIG. 3 is a diagram showing a bonding state between the semiconductor integrated circuit 1 and the liquid crystal panel 3 bonded by ACF2.

 As shown in the figure, a pressure 111, which is a stress against pressurization, is generated in each electrode pad of the semiconductor integrated circuit 1 bonded to the liquid crystal panel 3. Note that the pressure 111 is a pressure that does not destroy the transistor element.

[0033] Supplementary explanation here is that in the case of solder bonding or wire bonding bonding, the transistor element may be destroyed by heat and pressure applied to the electrode pad during mounting. No transistor element is arranged at the overlapping position. However, ACF bonding has much lower heat and pressure applied to the electrode pads during mounting than solder bonding or wire bonding bonding. Is low, so that it is possible to arrange a transistor element at a position overlapping with an electrode pad.

[0034] <POE>

 Next, P〇E will be described.

 FIG. 4 is a layout diagram of the POE arranged at the position indicated by the dotted square portion 12 in FIG.

 P〇E shown in the figure is an AND circuit, and as shown in the figure, is composed of various layers such as a methanol layer, a channel layer, a contact layer, and a polysilicon layer.

[0035] Then, since the pressure applied to the electrode pad is indirectly applied to the POE, distortion occurs in the layer constituting the P〇E, and the characteristics of the transistor element change.

 Therefore, the propagation delay time of P〇E is different from the propagation delay time of the same type of logic cell when it is located at a position that does not overlap the electrode pad.

 This difference in propagation delay time will be described with reference to FIGS.

FIG. 5 is a diagram showing a part of the logic circuit of the semiconductor integrated circuit 1, and shows an electrical connection relationship between the AND circuit 141, the OR circuit 142, the AND circuit 143, and the AND circuit 144. FIG. 6 is a timing chart showing the difference in signal timing received by AND circuit 144 when AND circuit 143 shown in FIG. 5 is a POE and when it is not.

According to FIG. 6, when the AND circuit 143 is a POE, its signal timing is output by Δt earlier than the signal timing of a signal whose AND circuit 143 is not a POE.

 <Back annotation device>

 Here, the configuration of the back annotation device will be described.

 FIG. 7 is a functional block diagram of a back-notation device 100 used for designing the semiconductor integrated circuit 1 described above.

As described above, the back annotation device 100 is a back annotation function unit of the CAD system, and FIG. Only the functional parts are shown.

The back annotation device 100 includes a storage unit, a layout parameter extraction unit 103, a POE identification unit 104, a delay value identification unit for each node connection 107, and a timing simulation execution unit 108. The storage unit stores mask layout information 101, a logic netlist 102, a standard logic cell library 105, and a POE logic cell library 106.

The mask layout information 101 is information on the layout and wiring of each layer of the semiconductor integrated circuit 1 created in the layout design. For example, information on the layout position and size of logic cells and electrode pads, wiring layout position And information on wiring width and parameter information on wiring resistance and capacitance.

 The logic netlist 102 is information indicating connection relations between logic cells constituting the semiconductor integrated circuit 1 created in the logic design. The connection between logic cells is generally called a node connection, which means wiring. Further, an instance indicating each logical cell described in the logical netlist 102 is associated with a logical cell library by a logical cell name.

In the logic design stage, all instances on the logic netlist 102 are associated with the standard logic cell library 105.

 The standard logic cell library 105 is composed of information indicating the logical expressions of various logic cells that are not POEs and information indicating the driving capability (power consumption, delay value, etc.). The POE logic cell library 106 includes various logic cells that are POEs. And information indicating the driving capability.

 The layout parameter extracting unit 103 has a function of extracting parameter information relating to the resistance and capacitance of the wiring from the mask layout information 101 stored in the storage unit. The extracted parameter information is sent to the delay value specifying unit 107 for each node connection.

 The POE identification unit 104 has a function of identifying whether a logic cell constituting a semiconductor integrated circuit is a POE based on the mask layout information 101 stored in the storage unit.

[0042] Specifically, the POE is detected by comparing information on the arrangement position and size of the electrode pad with information on the arrangement position and size of the logic cell, and the logical netlist 102 that is the detected POE is detected. Rewrite the logical cell name of the instance described in (1) so that it can be identified as POE.

 Here, an example of rewriting the logic cell name will be described.

FIG. 8 is a diagram showing a specific example of the logical netlist 102. FIG. 9 is a diagram showing that the FIG. 10 is a diagram showing an example of a logical netlist 102 in which the logical cell name of the specified logical cell has been rewritten.

 When it is detected that the instance “AND143” shown in FIG. 8 is a POE, the POE identification unit 104 outputs the instance “AND143” described in the logical netlist 102 as indicated by an instruction line 601 in FIG. Is rewritten to “AND” indicating the standard logic cell library 105 and “POE_AND” indicating the P〇E logic cell library 106.

The rewritten logical netlist 102 A is sent to the node connection-specific delay value specifying unit 107.

 The node connection-specific delay value specifying unit 107 includes the parameter information extracted by the layout parameter extracting unit 103, the logical netlist 102A rewritten by the P〇E identifying unit 104, and the standard stored in the storage unit. It has a function of specifying a wiring delay value for each node connection based on the logic cell library 105 and the POE logic cell library 106.

[0045] The wiring delay value includes the delay value of the logic cell, and the node connection-specific delay value identification unit 107 determines the standard logic cell library indicated by the logic cell name of the rewritten logic netlist 102A. Select the delay value that is described in 105 or POE logic cell library 106.

 The timing simulation execution unit 108 has a function of executing a timing simulation using the wiring delay value specified by the node connection-specific delay value specifying unit 107.

 As described above, according to the back annotation apparatus 100 of the present invention, the delay value of a logic cell is selected according to whether the logic cell is located at a position overlapping the electrode pad. Therefore, it is possible to accurately simulate the operation timing of a semiconductor integrated circuit in which a transistor element is arranged at a position overlapping with an electrode pad.

 Instead of storing the P〇E logic cell library 106, the delay value of the POE may be calculated by an operation using the delay value described in the standard logic cell library 105. In this case, it is conceivable that the back annotation apparatus 100 stores the coefficient used for obtaining the delay value of the POE in the storage unit.

[0047] Further, by inputting the pressure applied to the electrode pad, it is not necessary to calculate the delay value corresponding to the pressure. For example, electrical characteristics are inspected when the semiconductor integrated circuit is in a wafer state. At this time, a probe presses an electrode pad. Considering the pressure at this time, it is conceivable to specify the delay value of POE.

Further, the following modified examples are conceivable.

 <Modification 1>

 FIG. 10 is a diagram showing the pressure applied to the electrode pads of the semiconductor integrated circuit in a mounted state of the multilayer semiconductor integrated circuit.

 As shown in the figure, when the semiconductor integrated circuit 1A has a multi-layer structure of n layers, the pressure 111A directly received by the electrode pads 11 is dispersed by the number of layers. May be different.

 Therefore, the back-annotation device according to Modification 1 identifies the number of layers when the semiconductor integrated circuit to be designed has a multi-layer structure, and according to the identification result, determines the logic cell. Is selected.

 FIG. 11 is a functional block diagram of the back annotation apparatus 100A according to the first modification.

 [0050] The back annotation device 100A is different from the back annotation device 100 shown in Fig. 7 in that, instead of the POE identification unit 104A and the POE logic cell library 106, a layer-by-layer POE logic cell library is used. The first layer POE logic cell library 106A, the second layer POE logic cell library 106B, and the nth layer POE logic cell library 106C are stored in the storage unit, and the other configurations are the same.

 [0051] The POE identifying unit 104A identifies whether or not the logic cell constituting the semiconductor integrated circuit is a POE based on the mask layout information 101, and also determines whether the number of layers of the semiconductor integrated circuit is equal to the number of layers. It has the function of identifying.

 Specifically, the POE and the number of layers of the semiconductor integrated circuit were detected by comparing information on the arrangement position and size of the electrode pads with information on the arrangement position and size of the logic cell, and the The logic cell name of the instance described in the logic netlist 102 that is the POE is rewritten so that P〇E and the number of layers of the semiconductor integrated circuit can be identified.

[0052] For example, the PE identification unit 104A indicates that the instance "AND143" shown in FIG. When the semiconductor integrated circuit has a two-layer structure, the logical cell name of the instance “AND143” described in the logical netlist 102 is changed to “AND” indicating the standard logical cell library 105 as indicated by the indication line 901. Rewrite to “2—POE_AND” indicating the second layer POE logic cell library 106B. FIG. 12 is a diagram showing an example of the rewritten logical netlist.

 As described above, by using the back annotation apparatus according to the first modification, even when the delay value of the POE differs depending on the number of layers of the semiconductor integrated circuit, the POE can be correctly selected, and higher accuracy can be achieved. Timing simulation can be performed.

 Note that, instead of storing the P〇E logic cell library associated with the number of layers, the delay value of POE according to the number of layers is calculated by using the delay value described in the standard logic cell library 105. It is also conceivable to calculate the value. In this case, it is conceivable that the back-annotation device 100 stores in the storage unit a coefficient used for obtaining the delay value of P〇E, which is associated with the number of layers.

<Modification 2>

 FIG. 13 is a diagram showing the layout of the electrode pads of the semiconductor integrated circuit 1 and the layout of the logic cells arranged in the inner layer of the semiconductor integrated circuit 1 indicated by the dotted-line squares 13. The figure shows a state where only the n-type transistor region of the P-type transistor region and the n-type transistor region constituting the AND circuit overlaps the electrode pad.

As described above, it is assumed that the logic cell is arranged so as to partially overlap the electrode pad 11. In this case, since the influence of the applied pressure is different from the case where the entire logic cell overlaps the electrode pad, the change of the propagation delay time is also different.

 Therefore, the back-annotation apparatus according to the second modification is characterized in that the degree of overlap of the POEs is also identified, and the delay value of the logic cell is selected according to the identification result.

 [0056] Here, the degree of overlap means (1) a state where the pad and the n-type transistor region of the logic cell overlap, (2) a state where the pad and the p-type transistor region of the logic cell overlap, and (3) a state where the pad and the logic cell overlap. There are three states: the state where all the logic cells are overlapped.

FIG. 14 is a functional block diagram of the back annotation apparatus according to the second modification. The difference between the back annotation device 100B shown in FIG. 7 and the back annotation device 100 shown in FIG. 7 is that the POE identification unit 104B, the node connection-specific delay value identification unit 107B, and the POE logic cell library 106 Instead, the storage unit stores the P 演算 E delay value calculation coefficient 106D, which is used to determine the delay value corresponding to the propagation delay time that changes depending on the degree of overlap with the electrode pad of the POE and that is associated with the degree of overlap. The other points are the same.

 [0057] The POE identification unit 104B identifies whether or not the logic cell constituting the semiconductor integrated circuit is P〇E based on the mask layout information 101, and also determines the degree of overlap of the P〇E with the electrode pad. It has a function to identify even if it is dirty.

 More specifically, the information on the arrangement position and size of the electrode pad is compared with the information on the arrangement position and size of the logic cell to detect the degree of overlap between the POE and the electrode pad. The logical cell name of the instance described in the logical netlist 102 that is the POE is rewritten so that the POE and the degree of overlap can be identified.

 For example, if the POE identification unit 104B detects that the instance “AND143” shown in FIG. 8 and only the n-type transistor region overlaps, the POE identification unit 104B The logic cell name of the instance “AND143” is changed from “AND” indicating the standard logic cell library 105 as indicated by the indication line 1201 to “N—POE—AND” indicating that only the n-type transistor region overlaps. Rewrite to FIG. 15 is a diagram showing an example of the rewriting.

 [0059] The node connection-specific delay value specifying unit 107B selects a delay value of a logic cell based on the logic cell name described in the logic netlist 102. In other words, if the logic cell name indicates the standard logic cell library 105, the delay value described in the standard logic cell library 105 is selected, and the logic cell name S (N_POE_AND) or the like indicates POE. For example, using the POE delay value calculation coefficient 106D and the delay value described in the standard logic cell library 105, the delay value of the logic cell when only the n-type transistor region overlaps is calculated.

As described above, by using the back annotation apparatus according to the second modification, the electrode A different delay value can be correctly selected depending on the degree of overlap with the timing, and more accurate timing simulation can be performed.

 Note that instead of the POE delay value calculation coefficient 106, a POE logical cell library associated with the degree of overlap may be stored in advance in the storage unit.

 Embodiment 2>

 The present invention may be realized as a mask layout correcting device in addition to the above-described back annotation device.

Here, the mask layout correcting device means a functional unit that realizes a mask layout correcting function, which is one function of a CAD system used for designing a semiconductor integrated circuit. In the mask layout correcting apparatus according to the present invention, when a logic cell is arranged at a position that partially overlaps an electrode pad, the position of the logic cell is set to (1) a position that does not completely overlap the electrode pad, or (2) The feature is that the mask rate information is corrected so as to be at any one of the positions completely overlapping with the electrode pads.

FIG. 16 is a diagram used to describe a specific example of a mask layout correction process.

 As shown in the figure, when a logic cell is arranged at a position indicated by a dotted square portion 13a that partially overlaps with the electrode pad 11 of the semiconductor integrated circuit 1, the mask layout correction device (1) The arrangement position is changed to the position indicated by the dotted square portion 13a of the semiconductor integrated circuit la, that is, the position not overlapping the electrode pad at all, or (2) the arrangement position of the logic cell is changed to the dotted square rectangle of the semiconductor integrated circuit lb. Correction is performed to change the position to the position indicated by the portion 13b, that is, to change the position to completely overlap the electrode pad.

 [0063] This eliminates the need to specify different delay values depending on how the electrode pad and the logic cell overlap. In other words, it is only necessary to be able to specify the delay value of the logic cell when it is located in either of the above (1) or (2), so that the information necessary to specify the delay value is minimized. Can be

 In addition, as a result of the timing simulation performed by the above-described back annotation device, it is conceivable that a margin shortage is confirmed in any of the node connections.

In this case, in order to compensate for the margin shortage, the mask layout correction apparatus according to the present invention May be designed to compensate for the margin shortage by intentionally relocating a logic cell that does not overlap with the electrode pad and changing the layout to a position that overlaps with the electrode pad.

 In addition, when the delay value of the logic cell arranged at a position overlapping with the electrode pad changes, it is conceivable that the delay to which the logic cell is connected is earlier than the delay initially targeted at the design. Therefore, the mask layout correction apparatus according to the present invention employs a buffer in order to absorb a difference in delay value that is different depending on whether a logic cell is arranged at a position overlapping with an electrode pad or not. The correction may be performed in addition to the mask layout information.

For example, as shown in the logic circuit diagram of FIG. 17, when the AND circuit 143 is a POE, a buffer 140 is inserted between the connection between the AND circuit 143 and the AND circuit 144.

 As a result, it is possible to suppress the occurrence of a timing error such as a hold error due to the POE.

 <Supplement>

 The present invention is, of course, not limited to the above embodiments. The following are also included.

 (1) The present invention may be a back annotation method, or may be a program for realizing the above-described back annotation device and mask layout correcting device.

 [0066] The program can be recorded on a recording medium or distributed and distributed via various communication channels. Such recording media include an IC card, an optical disk, a flexible disk, and a ROM.

 (2) The present invention may be a method of manufacturing a semiconductor integrated circuit including P〇E.

 FIG. 18 is a view showing a process flow of the manufacturing method according to the present invention.

 The design process of a semiconductor integrated circuit can be broadly divided into a functional design process Sl, a logic design process S2, and a layout design process S3, and design is generally performed in this order.

The functional design process Sl, logic design process S2, layout design process S3, process process S8, mounting process S9, and evaluation test process S10 are the same as in the past, so they will be briefly described. In the function design process SI, the specifications of the semiconductor integrated circuit to be designed are defined, and an algorithm composed of functional blocks for realizing the specifications is designed.

 In the logic design process S2, a logic circuit representing an electrical connection relationship is designed based on the algorithm designed in the function design process S1. In this step, the above-described logical net list is created.

 In the layout design step S3, a mask pattern of the semiconductor integrated circuit is designed based on the logic netlist designed in the logic design step S2. In this step, the above-described mask layout information is created.

 The back annotation performed after the layout design step S3 includes an identification step S4, a selection step S5, and a simulation step S6.

[0070] In the identification step S4, it is determined whether or not the logic cell constituting the semiconductor integrated circuit is a POE based on the mask layout information created in the layout design step S3. Specifically, the POE is detected by comparing information on the arrangement position and size of the electrode pads described in the mask layout information with information on the arrangement position and size of the logic cell, and the detected POE is detected. Rewrite the logical cell name of the POE instance on the logical netlist created in the logical design process S2 to be identified.

In the selection step S5, a delay value of a logic cell is selected based on the logic net list rewritten in the identification step S4, and a wiring delay value is calculated.

 In the simulation step S6, a timing simulation is performed using the calculated wiring delay value.

 The correction step S7 performs correction to reflect the result of the timing simulation performed in the simulation step S6 to the logical netlist and the mask layout information.

In process step S8, a mask and a wafer are manufactured based on the mask layout information corrected in correction step S7.

 In the mounting step S9, the semiconductor integrated circuit formed on the wafer is diced, and bonding and molding with other components are performed.

The evaluation test process S10 uses an automatic inspection device (tester) to power semiconductor integrated circuits. Tests for moral characteristics and reliability.

 [0073] Evaluation test step Tests that have been performed in step S10 and have passed the criteria are shipped.

 If a semiconductor integrated circuit including POE is manufactured by the above-mentioned manufacturing method, a simulation considering the characteristic change of P〇E will be performed in the timing simulation at the design stage. In the test process S10, it is possible to prevent a situation when a timing error due to a change in the characteristics of the POE is found. Industrial applicability

The present invention is useful for designing a semiconductor integrated circuit.

Claims

The scope of the claims

 [1] storage means for storing mask rate information including position information of each of an electrode pad and a logic cell of a semiconductor integrated circuit;

 Identification means for identifying, based on the mask layout information, whether or not the logic cell is arranged at a position overlapping the electrode pad;

 Selecting means for selecting a delay value of the logic cell in accordance with a result identified by the identifying means.

 A back annotation device characterized by the above-mentioned.

 [2] The storage means further includes a first delay value that is a delay value when the logic cell is arranged at a position not overlapping the electrode pad, and a first delay value arranged at a position where the logic cell overlaps the electrode pad. And the second delay value, which is the delay value when the

 The selection means selects one of the first delay value and the second delay value stored in the storage means as a delay value of the logic cell according to a result identified by the identification means.

 2. The back annotation device according to claim 1, wherein:

3. The back annotation device according to claim 2, wherein the second delay value is a value that changes according to a magnitude of a pressure applied to the electrode pad.

4. The pressure according to claim 3, wherein the pressure is a pressure at the time of contacting an electrode pad of a probe used for electrical characteristic detection in a manufacturing stage where the semiconductor integrated circuit is in a wafer state. The back annotation device according to the above item.

[5] The storage means further includes a first delay value, which is a delay value when the logic cell is disposed so as not to overlap the electrode pad, and a location where the logic cell overlaps the electrode pad. The coefficient used for calculating the second delay value, which is the delay value when the

 The selecting means determines, according to a result identified by the identifying means, either a first delay value stored in the storage means or a second delay value obtained by an operation using the coefficient. Select as delay value of logic cell

3. The back annotation device according to claim 2, wherein:

6. The coefficient according to claim 5, wherein the coefficient is a coefficient used for an operation for obtaining a second delay value that changes according to the magnitude of the pressure applied to the electrode pad. The back annotation device as described in the above.

[7] The semiconductor integrated circuit has a multilayer structure,

 The identification means further identifies, when the logic cell is arranged at a position overlapping the electrode pad, the number of wiring layers constituting the semiconductor integrated circuit.

 The selecting means selects a delay value of the logic cell according to all results identified by the identifying means.

 2. The back annotation device according to claim 1, wherein:

[8] The storage means further stores a delay value when the logic cell is arranged at a position not overlapping the electrode pad and a delay value when the logic cell is arranged at a position overlapping the electrode pad. The delay value associated with the number of each wiring layer,

 The selection means selects one of the delay values stored in the storage means as a delay value of the logic cell according to all results identified by the identification means.

 8. The back annotation device according to claim 7, wherein:

[9] The storage means may further include a delay value when the logic cell is arranged at a position not overlapping the electrode pad, and a delay value when the logic cell is arranged at a position overlapping the electrode pad. The coefficient used for the calculation for determining the number of wiring layers and the coefficient associated with the number of wiring layers are stored,

 The selection means is configured to calculate the delay value stored in the storage means and the coefficient associated with the number of each wiring layer in accordance with all the results identified by the identification means. Is selected as the delay value of the logic cell.

 8. The back annotation device according to claim 7, wherein:

[10] The identification means further identifies the degree of overlap between the logic cell and the electrode pad when the logic cell is arranged at a position overlapping the electrode pad,

The selecting means is responsive to all the results identified by the identifying means, Choosing cell delay values

 2. The back annotation device according to claim 1, wherein:

[11] The storage means may further include a delay value in a case where the logic cell is arranged at a position not overlapping with the electrode pad, and a delay value at which the logic cell and the electrode pad overlap in any overlap manner. The delay value, which is the delay value in the case of

 The selection means selects one of the delay values stored in the storage means as a delay value of the logic cell according to all results identified by the identification means.

 11. The back annotation device according to claim 10, wherein:

[12] The storage means is further arranged at a position where the logic cell and the electrode pad overlap each other when the logic cell is arranged at a position where the logic cell does not overlap the electrode pad. In the case of calculating the delay value in the case of the

 The selecting means determines, based on the result identified by the identifying means, the delay value stored in the storage means and each delay value obtained by calculation using a coefficient associated with each degree of overlap. 11. The back annotation device according to claim 10, wherein any one of them is selected as a delay value of said logic cell.

[13] The degree of overlap is one of a state where the pad and the n-type transistor region of the logic cell overlap, a state where the pad and the P-type transistor region of the logic cell overlap, and a state where the pad and the whole logic cell overlap. Is in the state of

 13. The back annotation device according to claim 12, wherein:

[14] storage means for storing mask rate information including position information of each of an electrode pad and a logic cell of a semiconductor integrated circuit;

According to the mask layout information, when the logic cell is arranged at a position that partially overlaps the electrode pad, the position of the logic cell does not completely overlap the electrode pad, or a position that completely overlaps the electrode pad. Correction means for correcting the mask layout information so as to satisfy A mask layout correction apparatus, characterized in that:

[15] storage means for storing mask rate information including position information of each of an electrode pad and a logic cell of a semiconductor integrated circuit;

 Identification means for identifying, based on the mask layout information, whether or not the logic cell is arranged at a position overlapping the electrode pad;

 Selecting means for selecting a delay value of the logic cell according to a result identified by the identifying means;

 Timing simulation means for performing timing simulation using the delay value of the logic cell selected by the selection means;

 Correcting means for correcting the mask layout information, wherein a logic cell arranged at a position not overlapping with the electrode pad is changed to a position overlapping with the electrode pad based on a timing simulation result.

 A mask layout correction apparatus, characterized in that:

[16] storage means for storing mask rate information including position information of each of an electrode pad and a logic cell of a semiconductor integrated circuit;

 Correction means for performing a correction for adding a buffer to the mask layout information for absorbing a difference between delay values which are different depending on whether the logic cell is arranged at a position overlapping with the electrode pad or not. Have

 A mask layout correction apparatus, characterized in that:

[17] an identification step of identifying whether or not the logic cell is arranged at a position overlapping with the electrode pad, based on mask rate information including positional information of each of the electrode pad and the logic cell of the semiconductor integrated circuit; ,

 Selecting the delay value of the logic cell according to the result of the identification in the identification step.

 A back annotation method characterized by the above-mentioned.

[18] A program for causing a computer to execute a back annotation process,

 The back annotation process comprises:

A cell including position information of each of the electrode pads and the logic cells of the semiconductor integrated circuit; An identification step of identifying whether or not the logic cell is arranged at a position overlapping the electrode pad based on the layout information;

 Selecting the delay value of the logic cell according to the result of the identification in the identification step.

 A program characterized by that.

 [19] A computer-readable recording medium recording a program for causing a computer to execute the back annotation process,

 The back annotation process comprises:

 An identification step of identifying whether or not the logic cell is arranged at a position overlapping with the electrode pad based on mask layout information including position information of each of the electrode pad and the logic cell of the semiconductor integrated circuit;

 Selecting the delay value of the logic cell according to the result of the identification in the identification step.

 A recording medium characterized by the above-mentioned.

[20] an identification step of identifying whether or not the logic cell is arranged at a position overlapping with the electrode pad, based on mask rate information including position information of each of the electrode pad and the logic cell of the semiconductor integrated circuit;

 A selecting step of selecting a delay value of the logic cell according to the result of the identification in the identifying step;

 A simulation step of performing timing simulation of the semiconductor integrated circuit using the delay value of the logic cell selected in the selection step;

 A correction step of correcting the mask layout information based on a result of the timing simulation performed in the simulation step;

 A manufacturing step of manufacturing the semiconductor integrated circuit based on the mask layout information corrected in the correcting step.

 A method for manufacturing a semiconductor integrated circuit, comprising: