JPH063420A - Test pattern generation method for combinational logic circuit - Google Patents

Abstract

PURPOSE:To make it possible to generate a test pattern efficiently for a short time by assigning to a head signal line in a combinational logic circuit a part of input variables of logical functions that are used for a shared binary decision diagram(BDD) and reducing the number of input variables thereby. CONSTITUTION:Logical functions that are specified respectively by signal lines B3 to B6 against input variables assigned to external input lines B1 and B2 and a head signal line HL, are stored as a shared BDD. Then, test pattern generation processing is started for stuck-at fault on internal signal lines B3 and B4 and the signal line HL. As an example of signal line B3, when assumed stuck-at fault is transferred to an external output line B5, a logical function XOR on an output line B5 during normal and out-of-order status on the signal line B3 is searched, and an input variable in which a logical function specifying the XOR becomes one is searched as a local test pattern. Further, after searching the value on external input lines A1-A3 that satisfies the value of the signal line HL in this pattern, these values are combined with the values on the input lines B1 and B2 so as to obtain a test pattern for entire combinational logic circuit for detecting stuck-at fault of the signal line B3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generation method used for fault inspection of a combinational logic circuit, and more particularly to a test pattern generation method for a combinational logic circuit using a shared BDD.

[0002]

2. Description of the Related Art Generally, when inspecting a failure of an LSI (integrated circuit) after manufacturing, a method of inputting a specific test pattern and monitoring an output state is adopted. Generation of a test pattern used for such a fault inspection requires a long time for calculation as well as an increase in the size and complexity of a circuit, and also a cost.

In particular, generation of a test pattern for fault inspection of a combinational logic circuit is performed by a D algorithm or PODEM.
(Path-oriented decision marking) When using a deterministic test pattern generation algorithm based on a tree search, the number of backtracks becomes very large,
Depending on the failure, the test pattern may not be found within a realistic time. For this reason, there have been problems that a sufficient fault coverage cannot be obtained or that a huge amount of calculation time is required to increase the fault coverage.

On the other hand, an algorithm using a shared BDD is known as a test pattern generation algorithm capable of efficiently processing a redundant fault which takes a very long time in such an algorithm based on tree search. . Before explaining shared BDD, reference [1]: REBrya
nt, Graph-Based Algolithms for Boolean FunctionMani
pulation, IEEE Trans.on Computers, Vol.C-35, No.8, Aug
ust, 1985, pp.677-691., BDD (Binary
Decision Diagram: A binary decision diagram will be explained.
BDD uses logical functions as DAG (Directed Acyclic Graph:
It is intended to efficiently perform various operations on it.

First, before constructing a BDD, the order of variables of a logical function (denoted by f) to be expressed by the BDD is determined. For this logical function f, a binary decision tree is created according to a predetermined variable order. In Fig. 5 (a), f
An example of a binary decision tree for a logical function of = X ₁ · X ₂ + X ₃ will be shown. The order of variables is defined as X ₁ → X ₂ → X ₃ . This binary decision tree includes isomorphic subgraphs as shown in FIG. 5 (a), and the nodes marked with ⊚ share the isomorphic subgraphs with other nodes. Therefore, if the node marked with ⊚ is deleted as a redundant node, the DAG becomes as shown in FIG. 5 (b), which becomes the BDD representing the logical function f. At this time, since the order of variables is defined, B is set for one logical function.
DD is uniquely determined.

The shared BDD expresses a plurality of logical functions with a small amount of memory by applying the same idea as the BDD to a plurality of different logical functions and sharing the same type of subgraph among the logical functions. Is what you are trying to do. In FIG. 5 (c), f = X ₁ .X ₂ + X ₃ , g = X ₁ .X
An example of a shared BDD in which three logical functions of ₂ + X ₁ · X ₃ and h = X ₂ + X ₃ are simultaneously expressed will be shown.

Reference [2]: Ioki, Ishiura, Yajima “Test Generation of Combinatorial Logic Circuits Using Shared Binary Decision Diagrams”, No. 3
Proceedings of the 8th Annual Conference of IPSJ, 2S-5, Mar.1983, pp.1
137-1144. Describes a method of generating a test pattern for a 0,1 stuck-at fault (a fault in which the value on the signal line is fixed at 0 or 1) of each signal line that is normally assumed, using the shared BDD described above. .

[0008] In this method, first, a shared BD shares a logical function taken by each signal line in a target combinational logic circuit.
It is represented by D and stored in the memory. Then, a BDD (0 or 1) that represents a fixed value due to the stuck-at fault on the signal line is assigned to the signal line assuming the stuck-at fault, and the BDD (0 or 1) is propagated in the combinational logic circuit, whereby the failed circuit The logic function of each signal line of the combinational logic circuit) is successively obtained. If the propagated result is equal to the logic function of the normal circuit (combinational logic circuit without failure), it is determined that the effect of the failure has disappeared, and the subsequent propagation is stopped.

In this way, the influence of the fault is propagated, and when the fault reaches the external output line, it is determined that there is a test pattern capable of inspecting the fault. At this time, the exclusive OR (XOR) of the logical function in the normal circuit of the external output line to which the fault is propagated and the logical function in the fault circuit
If the value of the input variable (the variable assigned to the external input line of the combinational logic circuit) is calculated such that the value of this function is 1, the test pattern for the failure is obtained. If all the effects of a fault disappear before reaching the external output line, then the fault is a redundant fault.

The above operation means that the symbol simulation is performed in the circuit, but if the shared BDD is used,
They can be done efficiently. Hereinafter, a specific example of test pattern generation by the method of reference [2] will be described. As a combinational logic circuit, consider the circuit shown in FIG.
For the external input lines P ₁ , P ₂ , P ₃ , X ₁ , X ₂ , X
Assuming that ₃ input variables are given, the logic function of each signal line in the normal circuit is as shown in FIG. 6 (a).
These logical functions are stored in the memory as shared BDD.

Next, let us consider a case where a test pattern for detecting a stuck-at-0 fault on the signal line P ₄ is obtained. For this reason, as shown in FIG. 6 (b), 0 is set as a logical function at the time of failure for the signal line P ₄ and stored in the memory. When the value on the signal line P ₄ is propagated to the signal line P ₅ , the logical function on P ₅ at the time of failure is 0 + X ₂ = X ₂ . Next, when the value on the signal line P ₅ is propagated to the signal line P ₆ , the logic function on P ₆ at the time of failure becomes X ₁ + X ₂ and becomes equal to the logic function at the normal time, and the signal line P 6 The effect of the fault assumed on the signal line P ₄ on ₆ disappears. Therefore, when the value on the signal line P ₅ is propagated to another signal line P ₇ , the logical function on the signal line P ₇ at the time of failure becomes X ₂ + X ₃ , which is the signal line P ₇ at the normal time. Is the above logical function / X ₁ + X ₂ + X ₃
Will be different from. The notation / X _i (i = 1,2, ...) Indicates the negation of X _i .

Since the signal line P ₇ is an external output line, the logical function / X ₁ + X ₂ + X on the signal line P _{7 in} a normal state is used.
_3, takes the XOR of the logic function X ₂ + X ₃ on failure time of the signal line P _7. As a result, the BDD shown in FIG. 6C is newly generated as a part of the shared BDD. The input variables for which the logical function taking this XOR is 1 are (X ₁ , X ₂ , X
₃ ) = (0,0,0), which is generated as a test pattern for the fault (0 stuck-at fault of the signal line P ₄ ).

In the test pattern generation method using the shared BDD as described above, a general tendency is that in the deterministic test pattern generation method based on the tree search, the number of backtracks increases and a redundant fault may take time. Considered to be effective against. This is because, in the case of a redundant failure, even if the effects of the failure are propagated, they always disappear before reaching the external output line, and the redundancy of the failure can be proved at that point. Therefore, it is considered that the tree search method is an effective method for dealing with a failure that causes a truncation failure.

However, in the conventional test pattern generation method using the shared BDD, when a test pattern of a large-scale and complex combinational logic circuit is generated, the combinational logic circuit is generated depending on the order of input variables and the nature of the logic function. The number of nodes in the shared BDD that expresses the logical function of each signal line in the inside becomes extremely large. Therefore, there is a problem that the required capacity of the memory for storing the shared BDD is increased and that the execution time of various operations in the test pattern generation is long.

[0015]

As described above, in the conventional method of generating the test pattern of the combinational logic circuit by the algorithm using the shared BDD, when the target combinational logic circuit becomes large and complicated, Since the number of nodes in the generated shared BDD is large, the shared BD is
There is a problem that a large capacity memory is required to store D, the execution time of various operations becomes long, and it takes time to generate a test pattern.

The present invention reduces the required memory capacity by reducing the number of nodes of the generated shared BDD, and
An object of the present invention is to provide a test pattern generation method for a combinational logic circuit that can efficiently generate a test pattern in a short time.

[0017]

In order to solve the above problems, the present invention considers the head signal line in a combinational logic circuit as a part of an external input line when generating a test pattern using a shared BDD. The basic feature is that at least a part of the input variables of the logic function is assigned to this and the logic function on each signal line in the normal state of the combinational logic circuit is generated as a shared BDD. Then, the logic function on the external output line when the influence of the failure on the signal line of the combinational logic circuit is propagated to any external output line of the combinational logic circuit, and the logic on the external output line stored as the shared BDD. A test pattern for the fault is generated from the function and.

In generating the test pattern, for example, the exclusive OR of these two logical functions is taken, and the input variable such that the logical function obtained by the exclusive OR becomes 1 is subjected to the test pattern.

In the present invention, more specifically, the combinational logic circuit is divided into a first circuit portion located on the input side of the head signal line and a second circuit portion other than the first signal line, and the second circuit portion is divided into the second circuit portion and the second circuit portion.
The input variable of the logic function is assigned to the external input line and the head signal line of the circuit part of 1 to generate the logic function on the signal line included in the second circuit part of the combinational logic circuit in the normal state as the shared BDD.

Then, with respect to a failure on the signal line and the head signal line included in the second circuit portion, first, on the external output line when the failure is propagated to the external output line of the second circuit portion. A local test pattern for the fault is generated from the logic function and the logic function on the external output line already stored as the shared BDD. Next, the value on the external input line of the first circuit portion that satisfies the value on the first signal line in the local test pattern thus generated and the value on the external input line of the second circuit portion of the local test pattern are set. By combining them, the test pattern of the entire combinational logic circuit for the failure on the signal line or the first signal line included in the second circuit portion is obtained.

On the other hand, with respect to the signal line included in the first circuit portion, on the condition that the test pattern generated as described above with respect to the failure on the head signal line already exists, The value on the external input line of the first circuit portion such that the influence of the fault on the signal line included in the first circuit portion appears on the head signal line, and the second circuit portion of the test pattern for the fault on the head signal line. And the value on the external input line are combined to obtain the test pattern of the entire combined logic circuit for the failure on the signal line included in the first circuit portion.

[0022]

In general, when a shared BDD is generated for a combinational logic circuit while performing symbolic simulation, BDDs for all external input lines are first generated and propagated to the output line side. The method is taken.

On the other hand, in the procedure for generating the test pattern of the present invention, when the first signal line (for example, a value of 0 or 1 is assigned to the signal line is assigned to the combinational logic circuit, the position on the input side of this signal line is set. If there is a signal line whose value on the external input line is uniquely determined, a shared BDD is generated by allocating at least a part of the input variable to the first signal line.

In this way, when an input variable is assigned to the head signal line, and if there is an external input line that is not located on the input side of the head signal line, the input variable is also assigned to that external input line. Shared BDDs generated by reducing the number of input variables required for shared BDDs, rather than assigning input variables to all external input terminals of the circuit
The number of DD nodes is greatly reduced. This allows a small amount of memory to store the shared BDD,
Also, the execution time required for various operations for generating the test pattern is shortened.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are flowcharts showing the procedure of test pattern generation according to an embodiment of the present invention.

As a concrete example of the test pattern generation in this embodiment, consider the test pattern generation of the combinational logic circuit shown in FIG. In this combinational logic circuit, the signal line HL is the head signal line. Further, this combinational logic circuit will be considered by dividing it into a portion (hereinafter, referred to as a first circuit portion) A on the input side of the head signal line HL and another portion (hereinafter, referred to as a second circuit portion) B.

First, as preprocessing, 0 is applied to the head signal line HL.
Alternatively, a value on the external input lines A ₁ , A ₂ , A ₃ of the first circuit portion A which assigns 1 is obtained and stored in the memory. This process can be easily realized by using a known operation such as a backward operation (also referred to as a matching operation) in the D algorithm.

Internal signal line B included in the second circuit portion B
Generation of test patterns for the stuck-at faults on B ₃ , B ₄ (the signal line not on the signal path from the head signal line HL to the external input line) and the head signal line HL is performed according to the flowchart shown in FIG.

First, the first signal line HL is regarded as a kind of external input line, and the external input lines B ₁ and B _{2 of} the second circuit portion B are considered.
And the input variable of the logic function is assigned to the head signal line HL to generate the shared BDD, which is stored in the memory (S11).
That is, the external input lines B ₁ and B ₂ and the head signal line HL
With respect to the input variable assigned to the above, the plurality of logical functions respectively taken by the signal lines B ₃ , B ₄ , B ₅ , and B _{6 of} the second circuit portion B are stored in the memory as shared BDDs.

Here, the head signal line HL is, for example, a document
[3]: H. Fujiwara and T. Shimono, "Onthe Acceleration
of Test Generation Algolithms, "IEEE Trans.on Comp
uters, Vol. C-32, December 1983, pp. 1137-1144. FAN algorithm (fan-out-oriented test
The signal line is a signal line that is used as a signal line on the external input line located on the input side from this when the value 0 or 1 is assigned to the signal line.

The shared BDD generated in this way is
Variables given to the external input lines B ₁ and B ₂ and the head signal line HL are used as input variables, and all the external input lines of the combinational logic circuit (in the example of FIG. 3, A ₁ , A ₂ , A ₃ ,
The number of input variables is smaller than in the conventional case where input variables are assigned to B ₁ and B ₂ ). Therefore, the number of nodes included in the shared BDD is significantly reduced, and the capacity of the memory for storing the shared BDD is reduced.

After the shared BDD is generated and stored in the memory in this way, the internal signal lines B ₃ , B ₄ and B of the second circuit portion B are processed in accordance with the procedure described with reference to FIGS. The test pattern generation process for the stuck-at fault on the head signal line HL is started (S12).

That is, for example, taking the case of generating a test pattern for the stuck-at fault on the signal line B ₃ as an example, it is checked whether the stuck-at fault assumed for the signal line B ₃ has been propagated to the external output line B ₅ ( S13), when it is determined that it has not been propagated, it is determined that the failure is a redundant failure (S14).

On the other hand, when the stuck-at fault assumed for the signal line B ₃ is propagated to the external output line B ₅ , the signal line B 3
External output line B _{5 in} case of normal and above ₃
An XOR of the above logical function is obtained, and an input variable for which the logical function obtained by this XOR is 1 (in this case, the external input lines B ₁ and B _{2 of} the second circuit portion B and the head signal line HL are The value) is obtained as a test pattern (S15). In this way, the test pattern when the head signal line HL is regarded as a part of the external input line (this is called a local test pattern)
Is required.

When the local test pattern is formed in step S15, the external input lines A ₁ , A ₂ and A _{3 of} the first circuit portion A that satisfy the value of the head signal line HL in the local test pattern are next. The above values are obtained, and these values are combined with the values on the external input lines B ₁ and B ₂ of the second circuit portion B of the local test pattern to obtain the combinational logic circuit of FIG. 3 for the stuck-at fault of the signal line B ₃ . The overall test pattern is obtained (S16). The test pattern for the stuck-at fault of the other internal signal line b ₄ and the like included in the second circuit portion and the head signal line HL can also be obtained by the same procedure as described above.

Next, test pattern generation for stuck-at faults on the internal signal lines A ₄ and A ₅ (the signal lines on the signal path from the head signal line HL to the external input line) included in the first circuit portion A is generated. Is performed according to the flowchart shown in FIG. First, according to the flow chart shown in FIG. 1, it is judged whether or not the test pattern generation processing for the (0, 1) stuck-at fault of the head signal line HL is completed (S2).
1). Here, if the test pattern generation processing for the stuck-at fault of the head signal line HL is not completed, the internal signal line A
_For the stuck-at fault on ₄ or A ₅ , a flag is added for processing after the test pattern generation for the stuck-at fault on the head signal line HL is completed (S22).

On the other hand, if the test pattern generation processing for the stuck-at fault on the head signal line HL is completed, it is subsequently determined whether or not the test pattern for the stuck-at fault on the head signal line HL exists (S23). When this test pattern does not exist, that is, when the stuck-at fault on the head signal line HL is a redundant fault, the stuck-at faults on all the signal lines A ₄ and A ₅ included in the first circuit portion A are redundant faults. (S24).

When a test pattern for the stuck-at fault of the signal line HL exists, the influence of the stuck-at fault on the internal signal lines A ₄ and A ₅ included in the first circuit portion A affects the head signal line HL. The external input lines A ₁ , A ₂ , A _{3 of} the first circuit portion A appearing (that is, the difference between the normal state and the defective state of the signal lines A ₄ and A ₅ appears on the head signal line HL).
The value on (the external input line leading to the head signal line HL) is obtained (S25). The processing in step S25 can also be easily realized by using various operations such as backward operation in the D algorithm.

Finally, the values of the external input lines A ₁ , A ₂ and A ₃ obtained in step S25 and the test pattern for the 0 and 1 stuck-at faults on the head signal line HL which have already been obtained are selected. The combinational logic circuit of FIG. 3 for the stuck-at fault on the internal signal lines A ₄ , A ₅ included in the first circuit part A by combining the values on the external input lines B ₁ , B _{2 of the} second circuit part B. The overall test pattern is obtained (S26).

In the above embodiment, the shared BDD is used for the head signal line (HL) of the combinational logic circuit and the external input lines (B ₁ and B _{2 in} the example of FIG. 3) not located on the input side of the head signal line HL. Assigned the input variable of the logic function in
If there is no external input line that is not located on the input side of the head signal line, input variables may be assigned only to the head signal line.

FIG. 4 shows an example of an automatic test pattern generation system including a test pattern generation section using the above-mentioned test pattern generation method. This system receives the circuit data 1 of the combinational logic circuit as an input, and tests the combinational logic circuit through a test pattern generation unit 2 using a random method, a deterministic algorithm test pattern generation unit 3 and a test pattern generation unit 4 using a shared BDD. It is configured to perform various kinds of data 5 regarding the test.

Test pattern generation unit 4 using shared BDD
By applying the above-described test pattern generation method according to the present invention to the above, the memory capacity required for storing the shared BDD can be small, and the execution time of various operations in the test pattern generation can be shortened accordingly. Generation can be performed quickly and efficiently.

[0043]

As described above, according to the present invention, the number of input variables can be reduced by allocating a part of the input variables in the logic function used for the shared BDD to the head signal line in the combinational logic circuit. As a result, the number of shared BDD nodes can be significantly reduced. Therefore, the capacity of the memory for storing the shared BDD can be small, the execution time of various operations in the test pattern generation procedure can be shortened at the same time, and the efficient test pattern generation can be performed.

[Brief description of drawings]

FIG. 1 is a flowchart showing a test pattern generation procedure for a stuck-at fault of a signal line in a second circuit section in a test pattern generation method according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a test pattern generation procedure for a stuck-at fault of a signal line in the first circuit section in the test pattern generation method according to the embodiment.

FIG. 3 is a diagram showing a specific example of a combinational logic circuit for test pattern generation.

FIG. 4 is a block diagram showing the configuration of an automatic test pattern generation system incorporating a test pattern generation unit that uses the test pattern generation method according to the present invention.

FIG. 5 is a diagram for explaining shared BDD.

FIG. 6 is a diagram for explaining a conventional test pattern generation method using shared BDD.

[Explanation of symbols]

A ... first circuit portion B ... second circuit portions _{A 1 ~A 3, B 1,} B 2 ... external input line HL ... head signal line _{A 4, A 5, B 3} , B 4 ... internal signal line B ₅ , B ₆ ...
External output line

Claims (5)

[Claims] 1. A shared BDD is used to generate a logical function on each signal line in a normal state of a combinational logic circuit with respect to an input variable, and a test pattern for inspecting a failure of the combinational logic circuit is generated using this shared BDD. The test pattern generation method for a combinational logic circuit according to claim 1, wherein at least a part of the input variable is assigned to a head signal line in the combinational logic circuit. 2. A test pattern generating method for generating a test pattern for inspecting a failure of a combinational logic circuit, wherein at least a part of an input variable of a logic function is allocated to a head signal line in the combinational logic circuit, A shared BDD generation step of generating a logical function on each signal line in a normal state of the combinational logic circuit as a shared BDD, and propagating the influence of a failure on the signal line of the combinational logic circuit to an arbitrary external output line of the combinational logic circuit. A test pattern generation step of generating a test pattern for the fault from the logic function on the external output line when the fault occurs and the logic function on the external output line stored as the shared BDD. Test pattern generation method for combinational logic circuits. 3. The test pattern generating step shares the effect of a failure on a signal line of the combinational logic circuit with a logic function on the external output line when the influence of a failure on the signal line of the combinational logic circuit is propagated to the external output line. An exclusive OR is taken with a logical function on the external output line stored as BDD, and the input variable whose logical function is 1 is generated as the test pattern. 3. The method for generating a test pattern for a combinational logic circuit according to claim 2. 4. A test pattern generating method for generating a test pattern for inspecting a failure of a combinational logic circuit, wherein the combinational logic circuit is located on an input side of a head signal line in the combinational logic circuit. And a second circuit portion other than that portion, and an input variable of a logic function is assigned to the external input line and the head signal line of the second circuit portion so that the second logic circuit in the normal state of the combinational logic circuit Shared logic function on the signal line included in the circuit part of B
A shared BDD generation step of generating as a DD, and a logic on the external output line when a fault on the signal line included in the second circuit portion or the head signal line is propagated to the external output line of the second circuit portion. From the function and the logical function on the external output line stored as the shared BDD,
A local test pattern generation step of generating a local test pattern for the fault; A test pattern generating step of combining values on the external input lines of the second circuit portion to obtain a test pattern of the entire combined logic circuit for a failure on a signal line or a head signal line included in the second circuit portion. A method for generating a test pattern of a combinational logic circuit, which is characterized by being provided. 5. A test pattern generation method for generating a test pattern for inspecting a failure of a combinational logic circuit, wherein the combinational logic circuit is a first circuit located on an input side of a head signal line in the combinational logic circuit. And a second circuit portion other than the above portion, and an input variable of a logical function is assigned to the external input line and the head signal line of the second circuit portion so that the second logical circuit in the normal state of the combinational logic circuit is allocated. Shared logic function on the signal line included in the circuit part of B
A shared BDD generation step of generating as a DD, and a logic on the external output line when a fault on the signal line included in the second circuit portion or the head signal line is propagated to the external output line of the second circuit portion From the function and the logical function on the external output line stored as the shared BDD,
A local test pattern generating step of generating a local test pattern for the failure; a value on the external input line of the first circuit portion that satisfies a value on the first signal line in the local test pattern; First test pattern generation for combining the values on the external input lines of the second circuit portion to obtain a test pattern of the entire combined logic circuit for a failure on a signal line or a head signal line included in the second circuit portion. And the effect of the fault on the signal line included in the first circuit portion, provided that a test pattern for the fault on the head signal line generated in the first test pattern generation step exists. For the value on the external input line of the first circuit portion that appears on the head signal line and for the failure on the head signal line A second test for obtaining a test pattern of the entire combinational logic circuit for a fault on a signal line included in the first circuit portion by combining the value on the external input line of the second circuit portion of the test pattern. A test pattern generation method for a combinational logic circuit, comprising: a pattern generation step.