JPH11352200A - Damage analysing method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a damage analysis method of a semiconductor integrated circuit capable of shortening the analysis time by reducing the candidates of a damaged portion and the number of steps for the damage analysis. SOLUTION: A non-compressed test pattern 110 and a non-compressed damage dictionary 111 are produced using a connection data 101 of a circuit. A test of a semiconductor integrated circuit 112 is carried out using the non-compressed test pattern 110 to produce a manufacture test result 114. The candidates of a damaged portion are extracted using the manufacture test result 114 and the non-compressed damage dictionary 111 to prepare a list 116. Damage analysis is carried out based on the list 116 to specify a damaged portion. Thus, the number of detectable damage candidates is reduced by the respective test patterns by using the non-compressed test patterns and a reduction of the number of analysis steps and shortening of an analysis time can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analysis method for specifying a failure site in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art When a semiconductor integrated circuit is determined to be defective, a failure analysis is performed to identify a failed part. The failure analysis is generally performed by using a failure simulator and a test pattern automatic generation process to generate a test pattern and a failure dictionary indicating candidates for a failure part detectable by the test pattern. The result obtained by analyzing the failure needs to be promptly fed back to the manufacturing process.

FIG. 11 shows a procedure of processing in a conventional failure analysis method. The connection data 901 indicating the logical connection relationship of the semiconductor integrated circuit and the test pattern automatic generation library 902 which collects information necessary for automatically generating a test pattern are provided to the test pattern automatic generation processing step 903. The test pattern automatic generation processing step 903 includes a step 904 of performing processing for compressing the generated test pattern. For example, a candidate for a failure part detectable in the test pattern 0 (010101) is a, a candidate for a failure part detectable in the test pattern 1 (100100) is b and c, and the test pattern 2 (011)
It is assumed that the candidates for the failure part detectable in 101) are a and c, and the candidates for the failure part detectable in test pattern 3 (111000) are a, b, and c. The test pattern 3 can detect all of the failure site candidates a, b, and c,
The test patterns 0 to 2 and the failure site candidates are overlapping. Therefore, these test patterns 0 to 2 are deleted,
By using only the test pattern 3, the data amount of the test pattern can be reduced, and the test time can be reduced. Further, the test pattern automatic generation processing step 903 includes:
A failure dictionary 906 is generated and output. This failure dictionary 90
Reference numeral 6 corresponds to the correspondence table between the test pattern and the candidates for the faulty part detectable by this pattern as described above.

[0004] The test pattern 905 thus compressed is input to a manufacturing test process 908. In the manufacturing test step 908, an electric signal or the like is applied to the semiconductor integrated circuit 907 actually manufactured based on the test pattern 905 to perform a test, and a manufacturing test result 909 is output.

[0005] The manufacturing test result 909 and the failure dictionary 906 are input to the failure part candidate extraction processing step 910, and a list 911 indicating the failure part candidates is output and sent to the failure analysis step 912.

In the failure analysis step 912, failure analysis is performed based on the failure part candidate list 911, and a failure part is specified.

In the above-described failure analysis method, a test is performed using a test pattern automatically generated in step 903. On the other hand, another conventional failure analysis method described below uses a test pattern created manually, and the procedure of this analysis method is shown in FIG.

The connection data 1001 indicating the logical connection relationship of the circuit and the test pattern 1002 and the failure simulator library 1003 are stored in the failure simulator 1
004. Thereby, the failure simulator 1
At 004, a failure dictionary 1005 is generated and output.

The output failure dictionary 1005 and test pattern 1002 are provided to a manufacturing test process 1007, a test is performed on the manufactured semiconductor integrated circuit 1006, and a manufacturing test result 1008 is output. In the failure part candidate extraction processing step 1009, this manufacturing test result 100
8 and the failure dictionary 1005 are used to generate a failure site candidate list 1010. This list 1010 is input to the failure analysis step 1011, and a failure analysis is performed to identify a failure part.

FIG. 13 shows the procedure of another conventional failure analysis method. In this analysis method, a test is performed by automatically generating a test pattern. The connection data 1101 and the test pattern automatic generation library 1102 are provided to an automatic test pattern generation processing step 1103, and a test pattern 1104 and a failure dictionary 1105 are generated. The test pattern 1104 is provided to a manufacturing test step 1107, and a test is performed on the manufactured semiconductor integrated circuit 1106 to output a manufacturing test result 1108.

Manufacturing test result 1108 and failure dictionary 1105
Is input to the failure part candidate extraction processing step 1109, a failure part candidate list 1110 is generated, and the failure analysis step 1109 is performed.
111. In the failure analysis step 1111, a failure analysis is performed using the failure part candidate list 1110, and a failure part is specified.

[0012]

However, as the size of the semiconductor integrated circuit increases, the number of candidates for a faulty part which can be detected by one test pattern increases, and it becomes difficult to specify the faulty part. . In other words, if the number of failure site candidates increases, the number of steps in the failure analysis process 912, 1011 or 1111 increases, and the analysis process becomes complicated. Especially,
When the test patterns compressed in the test pattern automatic generation processing step 903 are used, the number of patterns decreases as described above, but the number of candidates for a faulty part that can be detected by one pattern increases. Increase.

In circuit design, a testability design method for easily controlling and observing a fault has been established, but a design method for facilitating identification of a faulty part has not been established.

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention facilitates the identification of a faulty part by reducing the number of candidates for a faulty part that can be detected by one test pattern, and reduces the man-hour for failure analysis and shortens the analysis time. It is an object of the present invention to provide a method for analyzing a failure of a semiconductor integrated circuit, which is capable of performing the above.

[0015]

A failure analysis method for a semiconductor integrated circuit according to the present invention is a method for performing a test by giving a test pattern to a semiconductor integrated circuit and performing an analysis for specifying a failure portion. A step of generating an uncompressed test pattern and a failure dictionary corresponding to the test pattern using the connection data of the integrated circuit; and performing a test on the semiconductor integrated circuit using the generated test pattern. Generating a result, using the test result and the failure dictionary, extracting a candidate for a failure part, performing failure analysis based on the extracted candidate for the failure part, and specifying the failure part And a process.

By using uncompressed test patterns, the number of fault candidates detectable by each test pattern is reduced, and the number of analysis steps and the analysis time can be reduced.

Further, in the failure analysis method for a semiconductor integrated circuit according to the present invention, a primary test pattern and a primary failure dictionary corresponding to the primary test pattern are generated using connection data of the semiconductor integrated circuit. Performing a test of the semiconductor integrated circuit using the generated primary test pattern, and generating a primary test result, the primary test result and the primary failure dictionary Extracting a candidate for a failure site to create a primary failure site candidate list; andusing the primary failure site candidate list to assume that a failure exists at a specific site. One or a plurality of test patterns to be propagated to the specific part are created, and when the test pattern is one set, this test pattern is used as a secondary test pattern, and the test pattern is duplicated. If there is a set, the step of selecting the smallest number of detectable failure sites as the secondary test pattern, and creating a secondary failure dictionary corresponding to the secondary test pattern, Performing a test of the semiconductor integrated circuit using the secondary test pattern, generating a secondary test result, and using the secondary test result and the secondary failure dictionary to determine a candidate for a failed part. The method includes the steps of extracting and creating a secondary failure site candidate list, and performing a failure analysis using the secondary failure site candidate list to identify a failure site.

Alternatively, the method for analyzing a failure of a semiconductor integrated circuit according to the present invention uses the information indicating candidates for a specific failure site unique to the semiconductor integrated circuit and the test pattern as the candidate for the specific failure site. A step of creating an edited test pattern edited for propagation and a step of creating a failure dictionary corresponding to the edited test pattern; and performing a test of the semiconductor integrated circuit using the created edited test pattern to generate a test result. Using the test result and the failure dictionary to extract a candidate for a failed part; performing a failure analysis based on the extracted candidate for the failed part; and identifying a failed part. Have.

Further, the method for analyzing a failure in a semiconductor integrated circuit according to the present invention uses the connection data of the semiconductor integrated circuit and information indicating a candidate for a specific failure site specific to the semiconductor integrated circuit. Performing a process of adding a circuit that improves the observability when propagating the test pattern to the candidate, and using the connection data of the semiconductor integrated circuit after the circuit is added, using the test pattern and the test pattern. A step of creating a corresponding failure dictionary; a step of performing a test of the semiconductor integrated circuit using the created test pattern; and a step of generating a test result; and Extracting candidates;
Performing a failure analysis based on the extracted failure site candidates to identify the failure site.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

The failure analysis method for a semiconductor integrated circuit according to the first embodiment of the present invention performs processing according to the procedure shown in FIG. The circuit connection data 101 and the test pattern automatic generation library 102 are given to the test pattern automatic generation processing step 103, and a test pattern and a fault dictionary are generated. Here, the step 103 includes a test pattern compression process 104, a compressed test pattern 105, a dictionary 106 corresponding to the test pattern 105, a test pattern discarded by the compression process, and a discarded pattern. Is generated and output.

As described above, the test pattern before compression can be detected, for example, in test pattern 0 (010101) as a candidate for a failure part, and test pattern 1 (10010
0), b and c are candidates for a failure site that can be detected in the test pattern 2 (011101), a and c are candidates for a failure site that can be detected in the test pattern 3 (111000), and a is a candidate for a failure site that can be detected in the test pattern 3 (111000). , B and c. In this case, as the test pattern after compression, only the test pattern 3 including all the failure site candidates a, b, and c is extracted, and the other test patterns 0 to 2 are discarded by compression and included in the uncompressed information 107. It is.

The compressed test pattern 105 and the manufactured semiconductor integrated circuit 112 are provided to a manufacturing test step 118, where a test is performed and a manufacturing test result 119 is output.
If it is determined in step 120 that a failure exists using the manufacturing test result 119, the subsequent processes 108, 10
Move to 9.

Compression test pattern 105 and uncompressed information 1
07 is input to the non-compressed test pattern generation processing step 108, and the test pattern 110 before compression is generated and output. That is, taking the above test patterns 0 to 3 as an example, all the test patterns 0 obtained by synthesizing the test pattern 3 after compression and the test patterns 0 to 2 included in the compression information.
Returned to ~ 3.

Similarly, the failure dictionary 106 and the non-compression information 107 indicating the correspondence between the compressed test pattern and the candidates of the failure parts detectable by the test pattern are input to the non-compression failure dictionary creation processing 109, An uncompressed failure dictionary 111 corresponding to a correspondence table between the previous uncompressed test pattern 110 and a candidate for a failure part that can be detected thereby is generated. The uncompressed test pattern 110 and the semiconductor integrated circuit 112 having a failure are provided to a manufacturing test step 113 to perform a test, and a manufacturing test result 114 is output. The manufacturing test result 114 and the uncompressed failure dictionary 111 are input to the failure part candidate extraction processing step 115, and a failure part candidate list 116 is generated. In the failure analysis step 117, a failure analysis is performed using the failure part candidate list 116, and a failure part is specified.

As described above, in the present embodiment, a failure site is specified using the uncompressed test pattern 110 and the uncompressed failure dictionary 111 corresponding to the test pattern 110.
As described above, the uncompressed test pattern 110 has a larger test pattern data amount than the compressed test pattern 105, but has a smaller number of failure site candidates that can be detected by each test pattern. Therefore, the number of steps for failure analysis is reduced, and the time required for analysis can be reduced.

The second embodiment of the present invention includes steps as shown in FIG. As in the first embodiment, the circuit connection data 201 and the test pattern automatic generation library 202 are provided to the test pattern automatic generation processing step 203. This step 203 includes a test pattern compression processing step 204. Unlike the first embodiment, in step 203, a compressed / uncompressed mixed test pattern 205 in which an uncompressed test pattern before compression and a test pattern after compression are mixed, and the mixed test pattern 205 A compressed / non-compressed mixed fault dictionary 206 indicating the relationship between 205 and a detectable fault site candidate is generated and output.

The compressed / uncompressed mixed test pattern 205 is input to an uncompressed test pattern extraction processing step 209,
An uncompressed test pattern 209 is output. Further, the compressed / non-compressed mixed fault dictionary 206 is input to the non-compressed fault dictionary extraction processing 208, and the non-compressed fault dictionary 210 is output.

The uncompressed test pattern 209 is provided to the manufacturing test step 212, and the manufactured semiconductor integrated circuit 211 is manufactured.
Are tested, and a production test result 213 is output. The uncompressed failure dictionary 210 and the manufacturing test result 213 are given to the failure part candidate extraction processing step 214, and a failure part candidate list 215 is generated and output to the failure analysis step 216.
Failure part candidate list 215 in failure analysis step 216
A failure analysis is performed on the basis of the data, and a failure site is specified.

In the present embodiment, by extracting the uncompressed test pattern 209 and the uncompressed fault dictionary 210 and specifying the fault site, the number of fault site candidates detectable in each test pattern is reduced. In addition, the man-hour and time for the failure analysis can be reduced.

The third embodiment of the present invention has a configuration as shown in FIG. Circuit connection data 301;
The test pattern automatic generation library 302 is provided to a test pattern automatic generation processing step 303. Step 3
03 includes a test pattern compression processing step 304, in which the compressed test pattern 40
5 and an uncompressed test pattern 307 before compression are generated, and a failure dictionary 306 and an uncompressed failure dictionary 308 corresponding to the compressed test pattern 305 are generated and output.

Of the information output from step 303, only the uncompressed test pattern 307 and the uncompressed failure dictionary 308 are used in the subsequent steps. The uncompressed test pattern 307 and the manufactured semiconductor integrated circuit 309 are provided to the manufacturing test step 310, where the test is performed and the manufacturing test result 311 is output. The manufacturing test result 311 and the non-compressed failure dictionary 308 are used as a failure part candidate extraction processing step 312.
And a failure site candidate list 313 is generated.
In the failure analysis step 314, the failure part candidate list 31
3 is used to perform a failure analysis, and a failure site is specified.

According to the present embodiment, a failure site is specified using the uncompressed test pattern 307 and the uncompressed failure dictionary 308, so that the number of failure site candidates detectable in each test pattern is reduced. In addition, the number of man-hours for failure analysis and the analysis time can be reduced.

In the above-described first to third embodiments, the test and the extraction of the failure site candidate are performed using the uncompressed test pattern and the uncompressed fault dictionary. On the other hand, the fourth, fifth, and sixth embodiments described below use a compressed test pattern and a fault dictionary.

The fourth embodiment of the present invention has a configuration as shown in FIG. Here, connection data 40
1. Automatic test pattern generation library 402, primary test pattern automatic generation processing step 403, primary test pattern 404, primary failure dictionary 405, semiconductor integrated circuit 406, primary manufacturing test step 407, first test pattern Next manufacturing test result 408, first failure site candidate extraction processing step 40
9. The respective processing steps and information leading to the primary failure site candidate list 410 are connection data 1101 shown in FIG.
Test pattern automatic generation library 1102, process 1
103, test pattern 1104, failure dictionary 1105,
Semiconductor integrated circuit 1106, manufacturing test step 1107, manufacturing test result 1108, failure part candidate extraction processing step 110
9, the same as the failure part candidate list 1110.

That is, the connection data 401 and the test pattern automatic generation library 402 are provided to the primary test pattern automatic generation processing step 403, and the compressed primary test pattern 404 and the compression corresponding to this test pattern are compressed. The later primary failure dictionary 405 is output. In the first manufacturing test step 407, the first test pattern 404
Is input, a test is performed on the manufactured semiconductor integrated circuit 406, and a first manufacturing test result 408 is output.

The primary production test result 408 and the primary failure dictionary 405 are input to the primary failure site candidate extraction processing step 409, and the primary failure site candidate list 410 is output. In the process shown in FIG.
After the 110 is generated, a failure analysis process is performed in a failure analysis step 1111 using the list 1110 to specify a failure part. In such a process, there is a problem that the analysis time is long because the number of candidates for the failed part is large as described above. On the other hand, the present embodiment is characterized in that after the primary failure site candidate list 410 is generated, a secondary test pattern is further generated to perform the test and the failure analysis. In this secondary processing step, failure analysis is performed by focusing on whether or not a specific failure at a specific location, for example, “0 condensate” exists at a specific location.

Second test pattern automatic generation processing step 4
11, connection data 401, primary failure site candidate extraction processing step 409, test pattern automatic generation library 4
02 is input, and a secondary test pattern 412 and a secondary failure dictionary 413 indicating a failure part candidate detectable by this pattern are generated.

FIG. 5 shows the procedure of the processing in the secondary test pattern automatic generation processing step 411. Step 4
11, a primary failure site candidate list 410 is input. In the failure assumption processing step 501, processing is performed for assuming that a failure exists at a specific part shown in the list 410.

Next, in the fault propagation processing step 502,
In order to detect a failure of the assumed specific part, a process of determining a signal path to be propagated to this part is performed. In the test pattern creation processing step 503, a test pattern to be propagated to the route determined in the step 502 is created.

In the undetermined signal allocation processing step 504, when there is a signal whose value is undetermined, a process of temporarily allocating a value is performed. Specifically, in the created test pattern, a test pattern to be propagated to a specific portion where a failure is assumed to be provided is provided, and a result that the test pattern is provided to the specific portion is obtained from a desired terminal. , The value of the undecided signal is temporarily assigned. Also, a value is temporarily assigned to an irrelevant signal that does not affect the specific part and whose value has not been determined so that the propagation processing can be performed.

In the process 505 for counting the number of detected faults,
When the propagation process is performed using the test pattern whose values are all determined, the number of detectable failure site candidates is totaled.
Here, in general, there are many cases where a plurality of combinations exist in the assignment of the undecided signal values in the step 504. Thus, in step 506, it is determined whether another assignment is possible for the assignment to the undecided signal. If another assignment is possible, the process returns to the assignment processing step 504 to assign another value, and the number of candidates for the detectable failure site in this case is totaled in step 505. Thus, step 5
By repeating the processing of steps 04 to 506, all combinations of undetermined signal values are obtained, and the number of candidates for each detectable fault site is totaled.

Further, in step 507, it is determined whether or not another propagation path exists for the assumed specific part. If there is, the processing of steps 502 to 507 is repeated. Move to

In the final test pattern selection processing step 508, the numbers of detected faults in all the propagation paths for detecting the fault of the assumed specific part are compared, and the test pattern with the smallest detectable number of faults is selected. .

Here, a more specific procedure of the process of counting the number of detectable faults in step 505 will be described. FIG. 6 shows an AND circuit AN1 as an example of a logic circuit.
1 shows a configuration including ＡＮAN3 and OR circuits OR1 and OR2. Now, it is assumed that in the step 501, the signal line G connected to the output terminal of the AND circuit AN1 has "1" degeneration short-circuited to the power supply line. Such a signal line G
Can be detected by transmitting a signal that correctly outputs "0" from the AND circuit AN1. Therefore, the signal lines (D, E) connected to the input terminals of the AND circuit AN1 (D, E) =
It can take three values: (0, 0), (0, 1), (1, 0). Furthermore, in order for the value of the signal line G to be propagated to the signal line J in order to detect the failure of the signal line G, it is necessary to consider the value of the signal line C, and (C,
D, E) = (1, 0, 0) and (1, 1, 0).

According to the above procedure, the failure assumption processing step 50
1, through the fault propagation processing step 502, the test pattern creation processing 503, and the undecided signal allocation processing 504,
Test patterns # 1 and # 2 are obtained as shown in FIG. Test pattern # 1 is a signal (A, B, C, D, E)
= (1, 1, 1, 0, 0), including, for example, “0 degenerate” of the signal line A and “0 degenerate” of the signal line B 7
The number of failed parts can be detected. Test pattern # 2 has signals (A, B, C, D, E) = (1, 1, 1,.
1, 0), and can detect eight faulty parts. Further, in step 507, it is determined whether or not there is another propagation path. As a result of considering the path for transmitting the value of the signal line G from the signal line H to the signal line I and taking out the value,
Further test patterns # 3, # 4, and # 5 are obtained, and the number of detectable failure site candidates becomes 6, 7, and 7, respectively. In the test pattern selection processing step 508, the test pattern # with the smallest number of candidates for the failure part that can be detected most
3 is selected.

According to such a procedure, step 41 in FIG.
In step 1, a test pattern is created and output as a secondary test pattern 412. Further, it generates and outputs a secondary failure dictionary 413 indicating the correspondence between the secondary test pattern 412 and the detectable failure site candidates.

The second test pattern 412 is input to the second manufacturing test step 414, and the first manufacturing test step 407 is input.
The test is performed again on the semiconductor integrated circuit 406 tested in the above, and the second manufacturing test result 415 is output. In the secondary failure site candidate extraction processing step 416, a process of inputting the secondary manufacturing test result 415 and the secondary failure dictionary 413 and extracting a secondary failure site candidate is performed. The candidate list 417 is output. The secondary failure site candidate list 417 is given to the failure analysis step 418, and a failure analysis is performed to identify a failure site.

As in the prior art, when a test is performed using a test pattern used in a normal test and an attempt is made to specify a failed part from the obtained test results, it takes a long time to analyze the number of candidates for the failed part. Needed. On the other hand, according to the present embodiment, a test is performed using a test pattern used in a normal test as a primary test pattern, and a primary failure site candidate list obtained by this test is The fault location is narrowed down using this method, a secondary test pattern that is effective only for propagation of the fault location and has a small number of fault candidates is generated, and a secondary test is performed for failure analysis. The analysis can be performed more narrowly, and the analysis time is reduced.

FIG. 8 shows a fifth embodiment of the present invention.
This will be described with reference to FIG. The test pattern 601 and the specific failure information 602 created manually are provided to the test pattern editing processing step 603. Here, the specific failure information 602 is obtained through a normally used failure part candidate extraction processing step 600 for extracting a failure part candidate, and is information indicating the identified failure part. More specifically, this information 602 makes it possible to narrow down the failure site candidates to specific locations in advance for each integrated circuit,
It shows a narrowed down part unique to the circuit. In a test pattern editing processing step 603, based on the specific failure information 602, a given test pattern 60
A pattern with a small number of detectable failure candidates is selected from among 1, and is output as an edit test pattern 604.

The edit test pattern 604 is given to the manufacturing test step 608, and a test is performed on the manufactured semiconductor integrated circuit 607, and a manufacturing test result 609 is output. Further, the edit test pattern 604 is input to the failure simulation step 605, and the edit test pattern 6
A failure dictionary 606 indicating the relationship between the 04 and the detectable failure site candidate is created. Failure site candidate extraction processing step 61
0, and a failure site candidate list 611 is generated. In the failure analysis step 612, failure analysis is performed based on the failure part candidate list 611, and a failure part is specified.

According to the present embodiment, the test pattern is edited by using the specific fault information 602 in which the candidates for the faulty part are previously narrowed down to a location specific to the circuit, so that the test pattern with a small number of fault candidates is used. Perform a test to identify the failure site. Therefore, the number of candidates for a failure part that can be detected in each test pattern is reduced, and the number of steps for failure analysis can be reduced, and the analysis time can be reduced.

The sixth embodiment of the present invention has a configuration as shown in FIG. Circuit connection data 701
And the specific failure information 702 obtained through the failure part candidate extraction processing step 700 are combined with the failure analysis circuit addition processing step 70.
3 is input. In step 703, a test pattern is propagated to a portion where a fault is assumed to exist by using a conventionally used technique, and a circuit is added so that the result can be easily observed.

Here, processing for adding a circuit for improving observability will be described with reference to FIG. For example, an AND circuit AN1 as shown in FIG.
1 to AN13, an AND circuit A
It is assumed that the signal line E of N11 has "0 degeneration". In this case, regardless of the output value of the AND circuit AN12, the value of the signal line E is changed to the AND circuit AN13.
Can be taken out from the signal line G connected to the output terminal, the observability is improved. Therefore, the AND circuit AN1
An OR circuit OR11 is added between the signal line F connected to the output terminal of the AND circuit 13 and the input terminal of the AND circuit 13, and the signal line H is connected to another input terminal of the OR circuit OR11. By setting the value of the signal line H to “1”, the value of the signal line F is always fixed to “1” regardless of the values of the signal lines C and D. As a result, the value of the signal line E can be observed from the output of the AND circuit AN13.

The logical connection data 704 after adding a circuit using such a method is generated from the step 703. The connection data 704 and the test pattern automatic generation library 705 are provided to an automatic test pattern generation processing step 706, and a test pattern 707 and a failure dictionary 708 are generated. The test pattern 707 and the manufactured semiconductor integrated circuit 709 are provided to a manufacturing test step 710, where a test is performed and a manufacturing test result 711 is output. The manufacturing test result 711 and the failure dictionary 708 are input to a failure part candidate extraction processing step 712, and a failure part candidate list 713 is generated. In the failure analysis step 713, a failure analysis is performed using the failure part candidate list 713, and a failure part is specified.

In the present embodiment, a test pattern 707 for improving the signal observability when a signal is propagated to a fault at a specific portion is generated, and the test pattern 707 and a fault dictionary 708 corresponding to the test pattern 707 are used. Since the failure part is specified, the number of failure part candidates that can be detected by the test pattern can be reduced, and the analysis time can be reduced.

The above embodiments are merely examples, and do not limit the present invention. For example, the first
In the third to third embodiments, the test pattern generation steps 103, 203 and 303 include the test pattern compression processing steps 104, 204 and 303, but such steps need not necessarily be included. ,
What is necessary is just to have the structure which performs a test using an uncompressed test pattern.

[0058]

As described above, the method for analyzing a failure in a semiconductor integrated circuit according to the present invention performs a test on a semiconductor integrated circuit using a test pattern for detecting a failure in a specific portion. The number of failure site candidates that can be detected by the pattern can be reduced, and the number of analysis steps and the analysis time can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure in a failure analysis method of a semiconductor integrated circuit according to a first embodiment of the present invention for each process.

FIG. 2 is a flowchart showing a process procedure in a failure analysis method of a semiconductor integrated circuit according to a second embodiment of the present invention for each process.

FIG. 3 is a flowchart showing a processing procedure in a failure analysis method of a semiconductor integrated circuit according to a third embodiment of the present invention for each process.

FIG. 4 is a flowchart showing a processing procedure in a failure analysis method of a semiconductor integrated circuit according to a fourth embodiment of the present invention for each process.

FIG. 5 is a flowchart showing a processing procedure in a secondary test pattern automatic generation processing step in FIG. 4 for each step;

FIG. 6 is a circuit diagram showing an example of a logic circuit for explaining the contents of processing in steps 501 to 505 in FIG. 5;

FIG. 7 is an explanatory diagram showing a relationship between each test pattern obtained by performing the processes of steps 501 to 505 in FIG. 5 and a detectable failure site.

FIG. 8 is a flowchart showing a processing procedure in a failure analysis method of a semiconductor integrated circuit according to a fifth embodiment of the present invention for each process.

FIG. 9 is a flowchart showing a processing procedure in a failure analysis method of a semiconductor integrated circuit according to a sixth embodiment of the present invention for each process.

FIG. 10 is a circuit configuration diagram for explaining the contents of a circuit addition process in step 703 in FIG. 9;

FIG. 11 is a flowchart showing the steps of a process in a conventional failure analysis method for a semiconductor integrated circuit for each process.

FIG. 12 is a flowchart showing a procedure of a process in another conventional method for analyzing a failure of a semiconductor integrated circuit for each process.

FIG. 13 is a flowchart showing a processing procedure in another conventional method for analyzing a failure of a semiconductor integrated circuit for each process.

[Explanation of symbols]

 AN1 to AN3 AND circuit OR1 to OR2 OR circuit

Claims (4)

[Claims] 1. A failure analysis method for a semiconductor integrated circuit in which a test is given to a semiconductor integrated circuit to perform a test and an analysis for specifying a failure portion is performed, wherein the compression analysis is performed using connection data of the semiconductor integrated circuit. Generating a test pattern and a failure dictionary corresponding to the test pattern; performing a test of the semiconductor integrated circuit using the generated test pattern; and generating a test result; and Using a failure dictionary and extracting a candidate for a failure portion; and performing a failure analysis based on the extracted candidate for the failure portion to identify a failure portion. Circuit failure analysis method. 2. A failure analysis method for a semiconductor integrated circuit, in which a test pattern is given to a semiconductor integrated circuit to perform a test and an analysis for specifying a failure portion is performed, wherein a primary test is performed using connection data of the semiconductor integrated circuit. Generating a pattern and a primary failure dictionary corresponding to the primary test pattern; performing a test of the semiconductor integrated circuit using the generated primary test pattern; Generating, using the primary test result and the primary failure dictionary,
Extracting a failure site candidate to create a primary failure site candidate list; and using the primary failure site candidate list to assume that a failure exists at a specific site; and One or more sets of test patterns to be propagated to the part
When the set is a set, the test pattern as a secondary test pattern, when there are a plurality of test patterns, the step of selecting the smallest number of detectable failure sites as the secondary test pattern, Creating a secondary failure dictionary corresponding to the secondary test pattern; performing a test of the semiconductor integrated circuit using the secondary test pattern to generate a secondary test result; Using the secondary test results and the secondary failure dictionary,
Extracting a candidate for a failure site to create a secondary failure site candidate list; and performing a failure analysis using the secondary failure site candidate list to identify a failure site. Failure analysis method for a semiconductor integrated circuit. 3. A failure analysis method for a semiconductor integrated circuit, in which a test pattern is applied to a semiconductor integrated circuit to perform a test, and an analysis for specifying a failure location is performed, wherein a specific failure location candidate specific to the semiconductor integrated circuit is identified. Using the information shown and the test pattern to create an edited test pattern edited to propagate to the specific failure site candidate, and further creating a failure dictionary corresponding to the edited test pattern; Performing a test of the semiconductor integrated circuit using the edited test pattern, and generating a test result; and extracting a candidate for a failure part using the test result and the failure dictionary. Performing a failure analysis based on a candidate for a failed part to specify the failed part. 4. A failure analysis method for a semiconductor integrated circuit for performing a test by giving a test pattern to the semiconductor integrated circuit and performing an analysis for specifying a failure portion, comprising the steps of: connecting data of the semiconductor integrated circuit; Using the information indicating the specific failure site candidate, a process of adding a circuit that improves the observability when propagating a test pattern to the specific failure site candidate, and adding the circuit A step of creating a test pattern and a failure dictionary corresponding to the test pattern by using the connection data of the semiconductor integrated circuit later; performing a test of the semiconductor integrated circuit by using the created test pattern; Generating, using the test result and the failure dictionary, extracting a failure site candidate, based on the extracted failure site candidate Performed disabilities analysis, failure analysis method of a semiconductor integrated circuit, comprising the steps of: identifying a failure area, a.