JPH11110430A - Waveform information display system in logic simulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the man-hour for signal selection by selecting an arbitrary signal and displaying a waveform by extracting information related to that signal from signal information making the connection condition and signal change condition of each signal correspondent to the related signal. SOLUTION: In a logic simulation, a signal connection information extraction processing part 130 extracts the signal connection information from a logic description file 100 storing the signal connection information of an electronic circuit. A signal change information extraction processing part 140 extracts the signal change information in the logic simulation. A waveform processing part 170 generates signal information making the connection condition and signal change condition of each signal correspondent to the related signal based on the signal connection information and the signal change information extracted by the signal connection information extraction processing part 130 and the signal change information extraction processing part 140. Based on an extracted signal connection information file 160, an arbitrary signal is selected, information concerning that signal is extracted from signal information, and the waveform is displayed on a waveform display input/output device 190.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation technique for reproducing the operation of an electronic circuit on a computer, and more particularly to a method for efficiently confirming the operation of an electronic circuit.

[0002]

2. Description of the Related Art As a method of confirming the operation of an electronic circuit at a design stage, a logic simulation is generally used. In the logic simulation, the operation of the electronic circuit is reproduced on a computer based on a logical description file storing the logical connection information of the electronic circuit, and it is checked whether the electronic circuit operates as expected by the designer. By doing so, it is verified whether there is a defect in the logic being designed. In this logic verification, if a case does not work as expected, the most effective analysis of the cause of the malfunctioning part by referring to the signal operation state in the electronic circuit at the time of executing the logic simulation based on the waveform of the logic simulation result is most effective. It is one of the means. In the operation check based on the waveform of the logic simulation result, the signals between the logic blocks are displayed on the waveform screen in order to identify which logic block has a defect. Since the names of input, output, and input / output signals between logical blocks are displayed in random order, input, output, and input / output signal names must be manually input to display a waveform screen on signals between arbitrary logical blocks. It is necessary to select and display signals one by one in the order of input, output, and input / output so that the flow of operation of the electronic circuit can be understood from the signal list in which the order is out of order. For the input / output signals, whether the displayed content is an input-side signal or an output-side signal, it is difficult to determine just by looking at the input / output signal, so the input / output division is determined. It is necessary to display the SET signal and the input and output signals together. In addition, when the specific logical block causing the failure is identified, the operation in the logical block is checked as the next step, but again, the input, output, and input / output names are manually out of order. It is necessary to select and display one by one from the signal list list. Further, as a known example closest to the present invention, JP-A-5-258005 is cited.

[0003]

As described above, in order to display a signal operation state in an electronic circuit as a result of a logic simulation on a waveform screen, it is necessary to manually select a signal. Selecting one signal at a time takes a lot of man-hours for signal selection. Further, since a signal display for making the operation flow of the electronic circuit easy to understand is performed, many man-hours are required. The purpose of the present invention is
An object of the present invention is to provide a means for reducing the number of signal selection steps.

[0004]

In order to achieve the above object, the present invention has the following arrangement.

(1) In a logic simulation system, first extraction means for extracting signal connection information from a logic description file storing signal connection information of an electronic circuit, and second extraction for extracting signal change information in a logic simulation Means, and means for generating signal information associated with a signal relating a connection state of each signal and a signal change state based on the signal connection information and the signal change information extracted by the first and second extraction means. An arbitrary signal is selected based on the extracted signal connection information file, and information related to the signal is extracted from the signal information and displayed in a waveform.

(2) In the case of (1), information to be extracted from the signal information can be selected for an arbitrary block.

(3) In the cases of (1) and (2), as a signal information display method, signals such as input, output, and input / output are displayed for each signal.

(4) In the cases of (1) and (2), as a signal information display method, signals are displayed in order of the number of signal changes.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram of a logic simulation system for verifying the logic of an electronic circuit. In this embodiment, it is assumed that a logic simulation is performed on an LSI having partial circuits of blocks A to C as shown in FIG. It is assumed that the logical description file 100 is composed of three files corresponding to blocks A to C as shown in FIG. Test data file 110
Is a file storing an input pattern given to an electronic circuit for logic simulation, and is created for each test item. Logic simulation processing unit 120
Are the logical description file 100 and the test data file 1
With 10 as an input, the internal state of the electronic circuit is determined and output to the result file 150. When the signal connection information extraction processing unit 130 receives the input of the logical description file 100,
Each block A to C in the logical description file 100
The input / output of the file and the signal of the input / output signal definition part are extracted, and a signal information extraction result file 160 is created. The method of extracting signal information in the present embodiment is described in the logical description file 100.
Will be described with reference to the block A file in the example. 31 in FIG.
0 is the input (IN) and output (OU) of the block A file
T) and signal definitions for each input / output (INOUT) section.
AA1 to AA in the IN definition described in this part
3. Extract the signal names of AC1, AC2 in the OUT definition, and AB1 to AB3 and AC3 in the INOUT definition, and set the signal names in the signal column 410 divided for each section in the signal information extraction result file shown in FIG. . Further, 320 in FIG. 3 is a definition of a connection destination block name and an inter-block signal name.
Block names defined here, blocks A, B, C
Is set in the connection destination column 420 shown in FIG. 4 in correspondence with the signal name. In addition, 330 in FIG.
It is a definition part of a SET signal, a block-side input signal, and a block-side output signal for signals AB1 to AB3 and AC3, which determine input / output division. The SET signal of input / output signal and related signal (block side input / output signal) from this 330 definition part
Is set in the SET signal column 430 shown in FIG. 4 in association with the SET signal, the related signal column 440, and the related signal column 450 with the input / output signal. Next, the signal change information extraction processing unit 140 will be described. The signal change information extraction processing unit 140 obtains information on the signal change state at the time of executing the logic simulation as follows. A counter is provided for every signal line in the electronic circuit, and the value of the signal line is changed from 0 to an indefinite value (X) or a high impedance value (Z).
1 to indefinite value (X) or high impedance value (Z), indefinite value (X) or high impedance value (Z) to 0, indefinite value (X) or high impedance value (Z) to 1 The counter provided for each signal is incremented by +1 for each change to, and at the end of the logic simulation, the count value of each signal is set in the signal change column 4 shown in FIG.
Set to 60. This completes the signal information extraction. Next, the waveform checking operation in the result checking operation after the execution of the logic simulation will be described. If the result of the logic simulation shows that there is a defect, a waveform display operation for displaying the internal state of the electronic circuit on a waveform screen is performed. The waveform display processing unit 170 is a processing unit that displays a logic simulation result waveform. This waveform display processing unit 170
Is the result file 150 and the signal information extraction result file 1
60 and input designation information from the waveform display input / output device 190 are input information. First, a logic designer obtains a logic block name or a signal name to be referred from a logic circuit diagram, and sets a logic block name or a signal name belonging to a logic block from the waveform display input / output device 190. In this embodiment, first, a case where the logical block name A is set will be described. The waveform display input processing unit 180 recognizes the set block name A and outputs the signal information extraction result file 1
60, the waveform display input / output device 190 displays the connection destination block name for which the block name A is the target as block connection information as shown in FIG. The logic designer arbitrarily selects a selection number including a signal to be displayed from the selection numbers 1 to 5 shown in FIG. 5 from the waveform display input / output device 190, thereby selecting the selection number from the signal information extraction result file 160. The block signal corresponding to the content is linked to the result file 150 and displayed on the waveform display input / output device 190. In this embodiment, the result of selecting the selection number 1 is shown in FIG.
FIG. 6 shows IN (input), OUT (output), and INOUT indicated by the block name A of the signal information extraction result file 160.
The signal name is displayed from the (input / output) section, and the signals having the largest number of signal changes in the section are displayed in order from the top. In addition, signals that affect the signals between logical blocks indicate a SET signal for determining an input / output division and related signals. In FIG. 6, an inter-block signal AC3, a SET signal SETAAC3,
Block side output signal OAAC3, block side input signal I
Display is performed in the order of AAC3. The case where one signal name belonging to a logical block is set will be described.
In this embodiment, it is assumed that AA1 of the logical block A is set. The waveform display input processing unit 180 recognizes the AA1 set by the waveform display input / output device 190, searches the signal information extraction result file 160 for a logical block in which the AA1 exists, and searches for the target block in the same manner as when setting the logical block name. Is displayed as the block connection information from the waveform display input / output device 190 as shown in FIG. Hereinafter, the display procedure on the waveform screen is the same as when the logical block name is set. FIG. 7 is a process flow showing the operation of the waveform display method in the logic simulation in FIG. 70
1 to 703 are processing flows for extracting signal connection information. Reference numerals 704 to 706 denote processing flows for extracting signal change information. Reference numerals 707 to 712 denote processing flows from confirmation of the result of the logic simulation to signal output to the waveform screen.

[0010]

According to the present invention, by specifying a logical block name or a signal name belonging to a logical block,
All signals connected to the logical block corresponding to the specified content or signals of an arbitrary selected logical block can be automatically displayed on the waveform screen. In addition, since input, output, and input / output signals can be classified and automatically displayed on the waveform screen, the number of signal selection steps on the waveform screen of the signal operation state inside the electronic circuit in the logic simulation can be reduced. .

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a logic simulation.

FIG. 2 illustrates an LSI to be subjected to logic simulation.

FIG. 3 is a description of a logical description file.

FIG. 4 is an explanation of a signal information extraction result file.

FIG. 5 is an explanation of a display block connection information file on a waveform screen.

FIG. 6 is a waveform screen display example.

FIG. 7 is a processing flow of a waveform information display method in a logic simulation.

[Explanation of symbols]

100: logical connection information file, 110: test data file, 120: logical simulation processing unit, 130: signal connection information extraction processing unit, 140: signal change information extraction processing unit, 150: result file, 160
... Signal information extraction result file, 170: Waveform display processing unit, 180: Waveform display input processing unit, 190: Waveform display input / output device, 700 to 712: Processing flow of waveform information display method in logic simulation.

Claims (4)

[Claims] 1. A logic simulation system for executing a logic simulation for reproducing an operation of an electronic circuit on an electronic computer based on a logic description file for storing signal connection information of an electronic circuit, First extraction means for extracting from the description file; second extraction means for extracting signal change information in the logic simulation; signal connection information and signal change information extracted by the first and second extraction means Means for generating signal information associated with a signal relating the connection status of each signal and the signal change status, and a display for selecting an arbitrary signal and extracting information relating to the signal from the signal information and displaying a waveform. A waveform information display method having input processing means. 2. A waveform information display method according to claim 1, wherein the information extracted from the signal information in the waveform information display method is information relating to an arbitrary logical block. 3. A waveform information display method in a logic simulation, wherein a signal information display method of the display input processing means according to claim 1 or 2 is performed by displaying signals such as input, output, and input / output. 4. A waveform information display method in a logic simulation according to claim 1 or 2, wherein the display input processing means displays the signal information in the order of the number of signal changes.