JP2001076024A - Logic circuit simulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit a terminal outputting a logic value which does not match with an expectation value to simulate an associated logic circuit with less operation quantity and less data storage capacity by logic-simulating a dump part as the input/output terminal of a final block in a partial logic circuit through the use of the net list and the partial pattern of the partial logic circuit as the input/output terminal of a final block in the partial logic circuit. SOLUTION: In an inconvenient logic group extraction step 101, a net where inconvenience occurs is traced from an entire net list, and one logic group is extracted. In a model generation step 102, the net list is generated from an inconvenient logic group extracted by the processing of the step 101. In a pattern cut step 103, a pattern where nonconformity occurs is extracted from the entire patterns. In a simulation step 104, logic simulation is executed, by using the net list from which only the nonconformity logic group is extracted and the pattern only on the nonconformity logic group.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating a logic circuit, and more particularly to verifying on a computer whether or not a designed logic circuit generates an expected output pattern as expected for a test input pattern. For how to.

[0002]

2. Description of the Related Art A conventional method of simulating a defective portion will be described with reference to FIG.

[0005] As shown in FIG. 9, since it is not possible to automatically extract a faulty logic group and execute a simulation, the simulation is usually performed separately in a primary process and a secondary process. In addition, it is necessary to recreate the netlist and patterns manually each time. In addition,
The pattern consists of a test input pattern and an expected output pattern.

Next, each step will be described in detail.

First, in step M of the primary processing,
Simulation of the entire chip using a netlist A (201) of the entire circuit, a simulation pattern A (208) of the entire circuit, and a simulation command file file5 (901) in which a dump of a terminal of a block to be checked is designated. And output the list (9
02) and a pattern F (903). There is also a step of converting the netlist into a load module that can be input by the simulator before executing the simulation, but is omitted for simplification of the description.

Next, in step N of the secondary processing, a list output (9
02) and the pattern F (903), the waveform of the expected value of the terminal of the block to be checked is confirmed, and the simple netlist D (90) is manually input using a circuit diagram editor or the like.
4) is created.

In step P of the secondary processing, step M
Output (902), which is the output of the simulation of
And the pattern F (903), the waveform of the expected value of the block terminal to be checked is confirmed, and the simulation pattern G (90) is manually performed using a waveform editor or the like.
5) is created.

In step Q of the secondary processing, step N
, The simulation pattern G created in step P (905), and the simulation command file file6 (906)
, Execute the simulation, and output the list (9
07) and a pattern H (908).

To check the result of the simulation in step Q, a visual check of the list output (907) or a visual check of the pattern H (908) using a waveform editor is performed.

The technique disclosed in Japanese Patent Application Laid-Open No. 3-89179 (Prior Art 1) is an apparatus for specifying an abnormal portion of an actually manufactured logic circuit. When an abnormal part that outputs a logical value different from the expected output logical value is detected by a performance test in a test mode that verifies each part using the serial input / output interface after changing the configuration so that it does not include the circuit, Regardless of whether or not there is a logical relationship with the input of the abnormal part, all parts are extracted as faulty circuits, and simulations are performed by sequentially generating exhaustive contingencies in all parts of the faulty circuit, and When the output result of the simulation matches the actual abnormal output, it is determined that the place where the supposed failure has occurred is broken.

The technique disclosed in Japanese Patent Application Laid-Open No. 7-36953 (Prior Art 2) is based on the fact that the logic values of all the signal lines and all the periods are converted into a logic circuit that does not consider the delay and a logic circuit that considers the delay. The two logic circuits are exhaustively determined by simulation, and signal lines having different logic values between the two logic circuits are extracted for each period. The format of the table shown in FIG. 3 in JP-A-7-36953 is shown in FIG. In the same period, extract only the highest-order signal line from the upper-lower relationship among the signal lines with logical value mismatch in the same period, and identify the highest-order signal line as a faulty part of the logic circuit considering delay Is what you do.

[0012]

The flow of FIG. 9 is a simulation of a specific defective portion. In the case of the defect location search simulation, steps M to Q are repeated. However, the whole circuit simulation is performed every time, and the amount of calculation of a computer that executes each step of the simulation and a file for storing a file used in the simulation are stored. Since it is not possible to reduce the used capacity of the main storage device and the external storage device of the computer, and the number of simulation events is the same each time, TAT (Turnaround Time)
Cannot be reduced.

According to the prior art 1, it is possible to specify a faulty part of an actually manufactured logic circuit. However, in the design stage, it is determined whether or not the logic circuit under design outputs a logic value as expected at first. Cannot be used to verify

In the prior art 2, since the simulation must be performed for all the signal lines and for all the test patterns, the amount of calculation for the simulation is enormous. In addition, in order to specify the failure relation, it is necessary to extract the highest signal line from the signal lines of which the logic values do not match in the same period. It is necessary to simulate a test pattern.

An object of the present invention is to provide a logic circuit simulation method capable of simulating a logic circuit associated with a terminal outputting a logic value that does not match an expected value with a small amount of calculation and a small data storage capacity. With the goal.

[0016]

According to the logic circuit simulation method of the present invention, a netlist of a partial logic circuit that outputs a logic value that does not match an expected value and whose designated terminal is logically dependent has been stored. A first step of extracting from a netlist of the entire logic circuit and storing the extracted netlist, and a second step of extracting and storing a partial pattern of the entire logic circuit from a stored pattern of the entire logic circuit, A third step of performing a logic simulation using the netlist of the partial logic circuit and the partial pattern.

Further, in the logic circuit simulation method according to the present invention, in the above-described logic circuit simulation method, the first output terminal having a logic value that does not match the expected value newly detected in the third step is output from the first terminal. And a third step is repeated.

Furthermore, in the logic circuit simulation method according to the present invention, the entire logic circuit storing a netlist of a partial logic circuit that outputs a logic value that does not match the expected value and whose designated terminal is logic dependent. A first step of extracting and storing a partial pattern relating to the logic circuit from a stored pattern relating to the entire logic circuit, and a second step of extracting and storing a partial pattern relating to the entire logic circuit; A third step of performing a logic simulation using the netlist and the partial pattern and using the dump location as an input / output terminal of the last block in the partial logic circuit; and generating and storing a netlist for the last block Generating and storing a pattern relating to the last block from the dump output obtained in the fourth step and the third step. A step of the fifth, and having a sixth step of performing a logic simulation using a pattern according to the last block with the net list according to the last block.

Further, in the logic circuit simulation method according to the present invention, in the above-described logic circuit simulation method, in the first step, a logic value that does not match the expected value is output from the input terminals of the partial circuit. It is characterized in that input terminals whose terminals are not logically dependent are clamped.

Further, in the logic circuit simulation method according to the present invention, in the above-described logic circuit simulation method, in the fourth step, a logic value that does not match the expected value is output from the input terminals of the last block. It is characterized in that input terminals whose terminals are not logically dependent are clamped.

Further, in the logic circuit simulation method according to the present invention, in the above-described logic circuit simulation method, the first step refers to a state transition truth table relating to each block constituting the entire logic circuit. It is characterized by performing.

A computer-readable recording medium according to the present invention is characterized by recording a program for causing a computer to execute the steps of the above-described logic circuit simulation method.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an outline procedure of an embodiment of the present invention, in which a failure logic group extraction step 101, a model generation step 102, and a pattern extraction step 1 are described.
03, a simulation step 104, and a screen display step 105.

Next, the respective steps of the present embodiment will be described with reference to FIG.

In the faulty logical group extraction step 101, a faulty net is tracked from the entire net list to extract one logical group.

In step A of step 101, a process of designating an output terminal of a certain block among one or more blocks constituting the entire circuit and outputting a logical value that does not match an expected value I do. The specification is, for example,
The user points the terminal in the circuit diagram displayed on the screen with a pointer such as a mouse, and the computer compares the pointed coordinates with the coordinates of each part of the displayed circuit diagram.

In step B of step 101, a library (204) prepared in advance is used to determine the input terminals of the block to which the terminal specified in step A belongs and to which the terminals specified in step A are logically dependent. Seek and ask. The library (204) is a library in which logical relationships between input terminals and output terminals of all basic blocks are stored in a database, and information of a state transition truth table of all terminals as illustrated in FIG. have. In FIG. 5, X1 and X3 are block names, and Hxx (xx = 01, 0
2,... Are input terminals, Nxx (xx = 01, 02,
..) indicates an output terminal, A indicates a hold, and X indicates indefinite. The state transition truth table is a table in which, for combinational circuits, the logical value of the input terminal is a condition, and the logical value of the output terminal is the result. For the sequential circuit, the logical value of the input terminal before clock input, the internal terminal 5 is a table showing, as conditions, the logical value of the internal terminal and the logical value of the output terminal after inputting the clock, on condition of the logical value of the output terminal and the logical value of the output terminal.

In step C of step 101, the terminal preceding the input terminal obtained in step B
The net composed of all the terminals whose input terminals are logically dependent on the input terminal is traced, and a faulty logic group is extracted. When extracting a faulty logic group, from the external output terminal that is the last stage of the netlist and output a value that does not match the expected value, trace the net from such an external output terminal There is a method of extracting a net up to the obtained external input terminal at the first stage (flow of step M) and a method of cutting out a specific block (including a customer macro) (flow of step N). This classification must be specified in step A in advance.

In the model generation step 102, a net list is generated from the faulty logic group extracted in the processing of step 101. The netlist generated in step D of step 102 does not include nets of normal blocks, and has a smaller capacity than the entire netlist.

In the pattern extracting step 103, a pattern causing a problem is extracted from the entire pattern. In step E of step 103, only the pattern relating to the input external terminal existing in the faulty logic group extracted in the processing of step 101 is extracted from the entire pattern and generated.

In the simulation step 104, a logic simulation is performed using a netlist from which only the faulty logic group is extracted and a pattern relating to only the faulty logic group. The netlist and the pattern used for the logic simulation differ depending on whether the flow of step M or the flow of step N is executed.

In screen display step 105, step 1
A waveform and a logic diagram as a result of the simulation in step 04 are displayed on the screen.

Further, an embodiment of the present invention will be described with reference to FIGS.

First, in step A, the netlist A (2
01) is input from the storage device, and the output terminal of a certain block, which is the output terminal to be checked (the terminal outputting a logical value that does not match the expected value), is changed from the screen of the machine as shown in FIG. Input by directly specifying with a mouse or the like (arrow 401) or by reading from definition file 1 (202).

As an option specification of the simulation method, a specific defect location simulation (a method of performing a simulation by specifying a specific block (including a customer macro) (steps A to E and H to K)) or a defect location Search simulation (simulate by extracting nets from the output terminal that outputs a logical value that does not match the expected value to the top external input terminal obtained by tracking the net from such an output terminal, Either of the methods of searching for a defective part by repeating the same simulation for the output terminal at the preceding stage where it is detected by the simulation that a logical value that does not match the expected value is output (repetition of steps A to G) Specify options. This option is specified by the user through input means such as a keyboard and a mouse, and is used in the branch of step F. As a method of using the simulator of the present embodiment, when selecting an output terminal other than the external output terminal as the output terminal, the user selects the specific defect location simulation or the defect location search simulation, but selects the external output terminal as the output terminal. Normally, only the failure point search simulation is selected. This is because the output terminal and the external output terminal of the final stage block are treated as separate ones.

In step A, the intermediate file tmp1
(203) is output to the storage device. Intermediate file tmp
1 (203) includes information that defines the output terminal specified in step A.

In step B, the intermediate file tmp1
(203) or input file File1 (202)
The block input terminal whose operation is dependent on the block output terminal specified by (1) is set to the library (204) shown in FIG.
Then, an information file tmp2 (205) including information defining such a block input terminal and the output terminal specified in step A is generated in the storage device.

In step C, the net to which all the input terminals defined in the intermediate file tmp2 (205) generated in step B are connected is stored in the library (2
04), referring back to the state transition truth table, going back and forth, and finally tracing up to the external input terminal to extract the faulty logic group, and to store the faulty logic group connection information file tmp3 (206). Generate and output to storage. Connection information file tmp3 generated here
(206) is a file in which a logical group related to a logical mismatch of the output terminal specified in step A is extracted.
Further, the connection information file tmp3 (206) has not yet been formed as a net list in terms of format.

In step D, based on the connection information file tmp3 (206) generated in step C, a netlist B (207) of the logical group model relating to the defect is generated and output to the storage device. The netlist B (207) generated here is a netlist relating to a circuit in which only the portion causing the failure is extracted as shown in FIG. Also,
At the time of generation of the netlist B (207), the input terminal for which it has become clear that the output terminal to be checked does not depend at step B is a clamp connection, that is, the logical value High
Alternatively, a clamp block is connected to such an input terminal so as to be connected to a logical value Low.

In step E, the netlist A (20
Based on the simulation pattern A (entire pattern) (208) corresponding to 1) and the connection information file tmp3 (206) generated in step C, generate and store a simulation pattern B (209) of the faulty logic group. Output to the device. The pattern of the fault logical group generated here is the connection information file t generated in step C.
The pattern relates to only the external input terminal defined in mp3 (206) and the output terminal specified in step A. In the simulation, an external output terminal is automatically connected to the output terminal specified in step A.

From step F, the process proceeds to step G or step H depending on the simulation option specified in step A. If the specific defect location simulation has been selected, the process proceeds to step H, and if the defect location search simulation has been selected, the process proceeds to step G.

In the process of repeating steps A to G by returning from step G to step A, a terminal which is considered to output a logical value that does not match the expected value in step A is designated, and a net related thereto is designated. A simulation is performed in step G using the list and the pattern,
Based on the result of the simulation, the next step A designates a block output terminal that outputs a logical value that does not match the expected value of the previous stage from the block output terminal designated in the previous step A, and newly designates the block output terminal. This is a flow in which a netlist and a pattern of a failure logic group are generated, and a simulation is repeated to search for a failure portion. In this way, by repeating the processing from step A to step G, the analysis is performed by limiting the places where the logical values that do not match the expected values are output.

In step G, the netlist B (207) generated in step D, the pattern B (209) generated in step E, and the command file File3 (21)
A simulation is performed using the method (0). An operating frequency, a timing check item, a timing check time, and the like are specified by the command file File3 (210). FIG. 7 shows the result of executing the simulation.
It is possible to confirm from the screen of the machine as shown. The screen display function will be described later with reference to FIGS.

If the process of the simulation for a specific defective portion is designated in step A, step G and subsequent processes are performed without executing step G.

Next, in the processing flow of steps H to K, an output terminal which is not an external output terminal as indicated by an arrow 601 in FIG. 6 is designated as an output terminal for outputting a logical value which does not match the expected value in step A. Is executed when the specific defect location simulation is specified as an option.

In step H, based on the information file tmp2 (205) generated in step B, a command file F used in the dump simulation of step I
ile3 (211) is generated. In the command file generated in step H, the pattern of the output terminal specified in step A and the input terminal belonging to the block to which the output terminal belongs, the output terminal of which depends on the operation is output in the dump simulation. And other information necessary for the dump simulation. This is because, in simulations other than the dump simulation, only the pattern of the external input terminal and the pattern of the external output terminal are handled. In the dump simulation, the pattern of the terminal designated as the dump is also output.

In step I, a dump simulation is executed using the netlist B (207) generated in step D, the pattern B (209) generated in step E, and the command file File3 (211) generated in step H. . In the dump simulation, unlike a normal simulation used in steps G and K, a pattern of a terminal specified by the command file F is generated in addition to an external input terminal and an external output terminal.
If the command file File3 (211) does not exist, patterns of all the terminals in the netlist B (207) are generated using default value information as information necessary for the dump simulation.

In step J, from the pattern C (212) of the dump simulation result output in step I,
Intermediate file tmp2 (205) output in step B
The dump pattern of all the terminals (input terminal and output terminal) of the block defined in (1) is extracted, and a simulation pattern D (213) of the faulty logic unit model is generated.

In step K, the block defined in the intermediate file tmp2 (205) output in step B is cut out from the netlist B (207) generated in step D, and as shown in FIG. A netlist C (214) of the faulty logic unit model in which the input / output terminal is added to the input / output external terminal is generated. Note that, among the input terminals of the blocks defined in the intermediate file tmp2 (205), the connection destination of the input terminal which does not depend on the output terminal to be checked does not depend on the netlist C to which the clamp block is added so as to be a clamp. (214) is generated.

In step L, a single simulation is executed using the simulation pattern D (213) generated in step J, the netlist C (214) generated in step K, and the single simulation command file File4 (215). I do. If the command file File4 (215) does not exist, information of a default value is used.

At step L, the contents to be checked by outputting the simulation result to the screen are shown. The simulation result can be confirmed on each of the screen 218 and the list 216. In the case of the screen output 218, as shown in FIGS. 7 and 8, the screen list has a function of displaying a net list and a pattern on separate Window screens, and a window screen for displaying a pattern waveform (Window 2 in FIG. 7, Window 4 in FIG. 8). ), The position of the time (or pattern unit) to be confirmed is indicated by the arrow 701 in FIG. 7 or the arrow 80 in FIG.
1, the window screen for displaying the netlist (Window in FIG. 7, W1 in FIG. 8)
In the window 3), there is a function of displaying the input / output logical value of each block with respect to the time (or pattern unit). In addition, a net showing a logical value that does not match the expected value is displayed in a different color to highlight or blink (switching between the two is optional) in order to distinguish it from a normal net. The waveform displayed here is the content of the pattern E (217) that is the result of the simulation in step G or step L.

The screen shown in FIG. 7 (Window 1, Wi
(ndow2) shows an example in which the simulation result of the faulty logic group in step G of the faulty part search simulation is displayed on the screen. Further, the screens (Window 3 and Window 4) in FIG. 8 show an example in which the simulation result of the defect single model in step K of the specific defect location simulation is displayed on the screen.

In the debug function for confirming on the screen, the netlist A (201) and the simulation pattern A (208) are displayed in addition to the display of the simulation results (results of extraction of the faulty logic group) in steps G and L. ), It is also possible to confirm on the screen the result of executing the logic simulation of all nets. In this case, in order to distinguish the net having the expected value mismatch from the normal net, it is possible to make a clear determination by changing the color and highlighting or blinking.

The method according to the above-described embodiment is realized by a computer reading and executing the program from a recording medium such as a CD-ROM on which a program for causing the computer to execute each step of the method is recorded. You can also. Also, a pattern for input / output in each step, a file for storing the netlist, a temporary file (a file whose name starts with “tmp”)
The library DB is stored in an external storage device or a main storage device of the computer.

At this time, usually, the CPU of the computer is used.
After the program is once transferred from the recording medium to the main memory by the operating system, the program is read from the main memory and executed.

The above program may be generated by a text file in which an interpreter-format instruction is described, and an interpreter which reads this file and converts it into an execution instruction.

[0058]

As described above, according to the present invention, a logic part caused by a defect is made into one model,
Since the number of blocks to be read when starting the simulator can be reduced, and the number of simulation events can be reduced by extracting the pattern of the defect, the amount of machine memory used in proportion to the number of blocks excluded from modeling can be reduced. It is possible to reduce the TAT as well as the TAT.

Further, since the pattern and the circuit diagram can be displayed on the screen in conjunction with each other, the analysis of the simulation result can be easily performed.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating schematic steps of a logic circuit simulation method according to an embodiment of the present invention.

FIG. 2 is a first flowchart illustrating detailed steps of a logic circuit simulation method according to an embodiment of the present invention.

FIG. 3 is a second flowchart for explaining detailed steps of the logic circuit simulation method according to the embodiment of the present invention;

FIG. 4 is a diagram illustrating an example of how a terminal outputting a logical value that does not match an expected value is specified on a circuit diagram of a screen according to the embodiment of the present invention.

FIG. 5 is a diagram showing an example of a state transition truth table according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating another example of how a terminal outputting a logical value that does not match an expected value is specified on a circuit diagram of a screen according to the embodiment of the present invention.

FIG. 7 is a diagram showing an example of a screen displayed in the course of a defect location search simulation according to the embodiment of the present invention.

FIG. 8 is a diagram showing an example of a screen displayed in a specific failure portion simulation according to the embodiment of the present invention.

FIG. 9 is a flowchart illustrating steps of a conventional logic circuit simulation method.

[Explanation of symbols]

 101 failure logic group extraction step 102 model generation step 103 pattern extraction step 104 simulation step 105 screen display step

Claims (7)

[Claims] 1. A netlist of a partial logic circuit that outputs a logical value that does not match an expected value and whose designated terminal is logically dependent is extracted from the stored netlist of the entire logical circuit and stored. A first step, a second step of extracting and storing a partial pattern relating to the logic circuit from a stored pattern relating to the entire logic circuit, and using a netlist of the partial logic circuit and the partial pattern. And a third step of performing a logic simulation by using the logic circuit simulation method. 2. The logic circuit simulation method according to claim 1, wherein the first to third steps are performed for a terminal that outputs a logic value that does not match the expected value newly detected in the third step. A logic circuit simulation method characterized by repeating the above. 3. A netlist of a partial logic circuit that outputs a logic value that does not match an expected value and whose designated terminal is logic-dependent is extracted from the stored netlist of the entire logic circuit and stored. A first step, a second step of extracting and storing a partial pattern relating to the logic circuit from a stored pattern relating to the entire logic circuit, and using a netlist of the partial logic circuit and the partial pattern. And performing a logic simulation using the dump location as the input / output terminal of the last block in the partial logic circuit.
A fourth step of generating and storing a netlist relating to the final block; and a fifth step of generating and storing a pattern relating to the final block from the dump output obtained in the third step. And a sixth step of performing a logic simulation using the netlist relating to the final block and the pattern relating to the final block. 4. The logic circuit simulation method according to claim 1, wherein in the first step, a logic value that does not match the expected value is output from the input terminals of the partial circuit. A logic circuit simulation method, wherein input terminals whose logic terminals do not depend on logic are clamp-connected. 5. The logic circuit simulation method according to claim 3, wherein, in the fourth step, among the input terminals of the last block, a terminal outputting a logical value that does not match the expected value does not depend on the logic. A method for simulating a logic circuit, wherein an input terminal is connected by a clamp. 6. The logic circuit simulation method according to claim 1, wherein the first step refers to a state transition truth table relating to each block constituting the entire logic circuit. And a logic circuit simulation method. 7. A computer-readable recording medium storing a program for causing a computer to execute each step of the logic circuit simulation method according to claim 1. Description: