JPH0520382A - Logic circuit verification device - Google Patents

Abstract

PURPOSE:To verify the conventional simulator incapable of stopping the propagation of a state value using an input pattern not taking sequence relationship into account. CONSTITUTION:A flip-flop disconnection means 1 disconnects the output of the flip-flop on logic circuit information A and B. An input/output terminal generation means 2 changes the output destination of the disconnected flip-flop, to an output terminal, and the input destination of the logic element which is the output destination of the disconnected flip-flop to the input terminal, prepares logic circuit information C and D making the logic circuit information A and B into combined logic circuit, and output it to a logic circuit simulator 4. An input pattern generation means 3 prepares the input pattern information to comparatively verify the logic circuit information C and D and outputs it to the logic circuit simulator 4. A result comparison means 5 discriminates the equality of the logic circuit information C and D from the simulation result of the logic circuit simulator 4 and discriminates the equality of the logic circuit information A and B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit verification device, and in particular, a logic circuit simulator is connected to the outside, and the details expressed in the same logic circuit are different through simulation by this logic circuit simulator.
The present invention relates to a logic circuit verification device that verifies the matching of two pieces of sequential logic circuit information by combining these pieces of sequential logic circuit information into a combined logic circuit.

[0002]

2. Description of the Related Art Conventionally, in this type of logic circuit verification device,
When verifying the consistency of two pieces of sequential logic circuit information that are expressed in the same logic circuit and have different details, it is possible to easily create an input pattern without considering the temporal context (order of operations). In order to do so, the propagation of the state value at each point of the circuit is stopped by the flip-flop, and the state value of the flip-flop is also treated as an input pattern to execute the simulation by the logic circuit simulator and verify it.

[0003]

In the conventional logic circuit verification device described above, in the verification of the sequential logic circuit, the existing simulator connected to the outside is caused to stop the propagation of the state value by the flip-flop, and the flip-flop is used. If there is no function to handle the state value of as an input pattern, the simulator has a drawback that the consistency of the sequential logic circuit information cannot be verified without modifying the simulator.

It is an object of the present invention to use an existing simulator in which the propagation of a state value is stopped by a flip-flop and the state value of the flip-flop cannot be treated as an input pattern, and the input without considering the order relation is input. It is to provide a logic circuit verification device that enables verification using a pattern.

[0005]

The logic circuit verification apparatus of the present invention is used by being connected to a logic circuit simulator, and is expressed in terms of the same input logic circuit. Two sequences having different levels of detail are shown. A logic circuit verification device for verifying the consistency between first logic circuit information and second logic circuit information, which are logic circuit information, comprising: (A) the first logic circuit information and the second logic circuit information. Flip-flop disconnecting means for disconnecting the output of the flip-flop with respect to the circuit information; (B) changing the output destination of the flip-flop disconnected by the flip-flop disconnecting means to an output terminal and disconnecting by the flip-flop disconnecting means. By changing the input destination of the logic element which is the output destination of the flip-flop to the input terminal, the first logic circuit information is combined with the logic circuit. The third logic circuit information, which is the information of the logic circuit, and the fourth logic circuit information, which is the information of the logic circuit obtained by combining the second logic circuit information, are created, Input terminal / output terminal generating means for outputting, (C) receiving the third logic circuit information and fourth logic circuit information from the input terminal / output terminal generating means, and inputting pattern information for comparison verification. Input pattern generating means for creating and outputting to the logic circuit simulator, (D) inputting the simulation result information from the logic circuit simulator, and checking the consistency between the third logic circuit information and the fourth logic circuit information. The result comparing means for determining the matching between the first logic circuit information and the second logic circuit information by the determination is provided.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a logic circuit verification device of the present invention.

The logic circuit verification apparatus 6 of this embodiment shown in FIG.
Is logic circuit information A (first logic circuit information) which is information of the sequential logic circuit, and logic circuit information having different levels of detail expressed for the same logic circuit as the logic circuit represented by the logic circuit information A. B (second logic circuit information) and flip-flop disconnecting means 1 for disconnecting the output of the flip-flop, and the output destination of the flip-flop disconnected by the flip-flop disconnecting means 1 is changed to an output terminal,
Also, by changing the input destination of the logic element which is the output destination of the flip-flop cut by the flip-flop cutting means 1 to the input terminal, the logic circuit information which is the information of the logic circuit in which the logic circuit information A is combined into a logic circuit. C (3rd
Of the logic circuit) and the logic circuit information D (fourth logic circuit information), which is information of the logic circuit obtained by combining the logic circuit information B into a logic circuit, and outputs it to an external logic circuit simulator. / Output terminal generating means 2, input pattern generating means 3 for creating input pattern information for comparison verification using the logic circuit information C and the logic circuit information D, and outputting it to the external logic circuit simulator 4, Result comparing means for determining the match between the logic circuit information A and the logic circuit information B by inputting the simulation result information from the logic circuit simulator 4 and determining the match between the logic circuit information C and the logic circuit information D It is composed of 5.

Next, the operation of the apparatus will be described, and thereafter, the operation will be described by taking concrete circuit information as the logic circuit information A and B as an example.

In FIG. 1, first, the flip-flop disconnecting means 1 inputs the logic circuit information A and then inputs the logic circuit information A.
For the inside flip-flop, it is determined whether or not its output is connected to another logic element or flip-flop, and if it is connected, the connection of the output of the flip-flop is cut off, and the logic circuit information E is created. Similarly, the logic circuit information B is input, and it is determined whether or not the output of the flip-flop in the logic circuit information B is connected to another logic element or flip-flop. The output connection is disconnected and the logic circuit information F is created.

Next, the input terminal / output terminal generating means 2
Inputting the logic circuit information E, the flip-flop disconnecting means 1
An output terminal for connecting the output of the flip-flop cut by is generated, and the output of the flip-flop cut by the flip-flop cutting means 1 is connected to the generated output terminal. Then, an input terminal for connecting the input of the logic element or the flip-flop whose input side is connected to the flip-flop cut by the flip-flop cutting means 1 is generated, and the generated input terminal is connected to the logic element or the flip-flop. The logic circuit information C is created by connecting the inputs.

Similarly, the logic circuit information F is input, an output terminal for connecting the output of the flip-flop disconnected by the flip-flop disconnecting means 1 is generated, and the generated output terminal is disconnected by the flip-flop disconnecting means 1. Connect the output of the flip-flop. Further, an input terminal for connecting the input of the logic element or the flip-flop whose input side is connected to the flip-flop cut by the flip-flop cutting means 1 is generated, and the generated input terminal is connected to the logic element or the flip-flop. The inputs are connected and the logic circuit information D is created.

As a result, in the logic circuit information C and the logic circuit information D, the output of the flip-flop is not input to the next flip-flop, so that the sequential logic circuit is converted into the combinational circuit.

Then, the input pattern generating means 3 inputs the logic circuit information C and the logic circuit information D, regards the logic circuit to be verified as a combinational logic circuit, generates an input pattern, and sets it in the input terminal. Input pattern information G holding a value is created.

In the logic circuit simulator 4 connected to the outside, when the input pattern information G, the logic circuit information C and the logic circuit information D are input, the state value set in the input terminal by the input pattern information G is set. To the input terminal,
According to the logic circuit operation represented by the logic circuit information C and the logic circuit information D, the simulation is performed respectively, and the simulation result information H which is the result of the simulation is created and output to the logic circuit verification device.

Finally, the result comparing means 5 of the logic circuit verification device inputs the simulation result information H from the logic circuit simulator 4, compares the simulation results with the logic circuit information C and the logic circuit information D, and confirms the agreement. judge.

Next, as the logic circuit information A and B, the operation will be described by taking concrete circuit information as an example.

FIG. 2 is a diagram showing a logic circuit concretely expressing the logic circuit information A input to the logic circuit verification apparatus of this embodiment.

The logic circuit information A is an image diagram representing a logic circuit, and the input terminals M to Q are input,
Output terminal R via connection a to connection i and flip-flop I, flip-flop J, logic element K, and logic element L
It represents the logic circuit that outputs to.

In FIG. 3, the logic circuit information E created by the flip-flop disconnecting means 1 of the logic circuit verification device of this embodiment by inputting the logic circuit information A expressed in FIG. 2 is specifically expressed. It is a figure which shows a circuit.

The logic circuit information E is an image diagram expressing a logic circuit, and the input terminals M to Q are input,
Connection a to connection e, connection f ₁ , connection f ₂ , connection g, connection h
₁ , a connection h ₂ , a connection i and a flip-flop I, a flip-flop J, a logic element K, and a logic element L are used to represent a logic circuit that outputs to an output terminal R.

However, the connections f ₁ and f ₂ are connections generated by the flip-flop disconnecting means 1 disconnecting the connection f in FIG. 1. Similarly, the connections h ₁ and h ₂ are The connection h in 1 is a connection generated by the disconnection of the flip-flop disconnecting means 1.

That is, the flip-flop disconnecting means 1
Pays attention to the connection f which is the connection of the output of the flip-flop I in the logic circuit information A. Since the connection f is connected to the logic element K, the connection f is disconnected and the connection f ₁ and the connection f ₂
Change to. Similarly, paying attention to the connection h which is the connection of the output of the flip-flop J in the logic circuit information A, the connection h
Is connected to the logic element L, the connection h is disconnected and the connection is changed to the connection h ₁ and the connection h ₂ .

FIG. 4 specifically expresses the logic circuit information C created by the input terminal / output terminal generating means 2 of the logic circuit verification device of this embodiment inputting the logic circuit information E expressed in FIG. It is a figure which shows the logic circuit which did.

The logic circuit information C is an image diagram representing a logic circuit, and the input terminals M to Q and the input terminal I ₁ and the input terminal J ₁ are input, and the connection a to the connection e, the connection f ₁ and the connection are made. f ₂ , connection g, connection h ₁ , connection h ₂ , connection i
And a flip-flop I, a flip-flop J, a logic element K, and a logic element L to represent a logic circuit for outputting to an output terminal R, an output terminal I ₂ , and an output terminal J ₂ .

Here, the input terminal / output terminal generating means 2
Connects the connection f ₁ which is the input connection of the logic element K in the logic circuit information E after generating the input terminal I ₁ ,
Similarly, the connection h ₁ which is the input connection of the logic element L in the logic circuit information E is connected after the input terminal J ₁ is generated. In addition, the flip-flop I in the logic circuit information E
The connection f ₂ which is the output connection of the flip-flop J is connected after the output terminal I ₂ is generated. Similarly, the connection h ₂ which is the output connection of the flip-flop J in the logic circuit information E is connected to the output terminal J ₂ And then connect.

As a result, in the logic circuit diagram represented by FIG. 4, the output of the flip-flop is not input to another logic element or the flip-flop, but the input pattern state value is given to the input terminal to perform the simulation. The logic operation can be verified only by confirming the simulation result with the state value of the output terminal, that is, by using the input pattern that does not consider the order relation of the input patterns.

As described above, with respect to the logic circuit information representing the sequential logic circuit, by providing means for cutting the output of the flip-flop to form a combinational logic circuit, the logic simulator connected to the outside propagates the state value. Even in the case of the existing simulator in which the flip-flop is stopped and the state value of the flip-flop cannot be treated as the input pattern, the verification by the input pattern without considering the order relation can be enabled.

[0029]

As described above, the logic circuit verification device of the present invention is provided with means for cutting the output of the flip-flop for the logic circuit information representing the sequential logic circuit to form a combinational logic circuit. Verification by an input pattern that does not consider the order relation even in the case of an existing simulator in which an externally connected logic simulator stops the propagation of state values by flip-flops and the state values of flip-flops cannot be handled as input patterns Has the effect of enabling

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a logic circuit verification device of the present invention.

FIG. 2 is a diagram showing a logic circuit that specifically expresses logic circuit information A input to the logic circuit verification device of the present embodiment.

FIG. 3 shows the logic circuit information A represented by FIG. 2 in the flip-flop disconnecting means 1 of the logic circuit verification device of this embodiment.
It is a figure which shows the logic circuit which expressed concretely the logic circuit information E input by inputting.

FIG. 4 is a logic circuit concretely expressing logic circuit information C created by inputting the logic circuit information E expressed by FIG. 3 by the input terminal / output terminal generating means 2 of the logic circuit verification device of the present embodiment. FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Flip-flop disconnection means 2 Input terminal / output terminal generation means 3 Input pattern generation means 4 Logic circuit simulator 5 Result comparison means 6 Logic circuit verification device

Claims (1)

Claim: What is claimed is: 1. Information on two sequential logic circuits having different levels of detail, which are used for connecting to a logic circuit simulator and are expressed for the same input logic circuit. A logic circuit verification device for verifying the consistency between the first logic circuit information and the second logic circuit information, comprising: (A) a flip-flop for the first logic circuit information and the second logic circuit information. Flip-flop disconnecting means for disconnecting output, (B) changing the output destination of the flip-flop disconnected by the flip-flop disconnecting means to an output terminal, and the output destination of the flip-flop disconnected by the flip-flop disconnecting means By changing the input destination of a certain logic element to an input terminal, it is information of a logic circuit obtained by combining the first logic circuit information into a combination logic circuit. And third logic circuit information and fourth logic circuit information which is information of a logic circuit obtained by combining the second logic circuit information into a logic circuit,
Input terminal / output terminal generating means for outputting to the logic circuit simulator, (C) receiving the third logic circuit information and fourth logic circuit information from the input terminal / output terminal generating means, and for comparing and verifying Input pattern generating means for creating the input pattern information and outputting it to the logic circuit simulator, (D) inputting the simulation result information from the logic circuit simulator, and inputting the third logic circuit information and the fourth logic circuit information.
Logic circuit verification, which comprises: result comparing means for determining the match between the first logic circuit information and the second logic circuit information by determining the match with the logic circuit information. apparatus.