JPH01170873A - Test circuit for digital circuit - Google Patents

Abstract

PURPOSE:To restart a normal operation in a shift operation state without inputting from a serial data input by switching the serial data input of an FF in a first stage to the output signal of an FF in the last stage by a loop back control signal. CONSTITUTION:When an operation state selection signal MODESEL and a loop back control signal LOOPSEL are set to the low level, the output Q of an FFm is outputted from a serial data output SOUT and is inputted to the data input D of an FF0 through selectors SEL and SEL0. Meanwhile, the output Q of the FF0 is inputted to the data input D of an FF1 through a selector SEL1. Data outputs Q of FFs in preceding stages are inputted to data inputs D of an FF2 and following FFs. When a clock CLK is inputted, inputs D of respective FFs are set to respective FFs and are successively outputted as outputs Q. As the result, data Qm-1 set to an FFm-1 is outputted from the output SOUT. When this operation is repeated m-number of times, data set to all FFs are outputted from the output SOUT and all FFs are set to the states before the clock input.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital circuits, and particularly to a test circuit for synchronous circuits.

[Prior Art] Conventionally, there is a circuit as shown in FIG. 3 as a test circuit for this type of digital circuit. This will be explained below with reference to FIG. In FIG. 3, in the normal operating state, the operating state selection signal M
Set ODESEL to high level. At this time, flip-flops FFO and FFI.

FF2. ...+ Selectors 5ELO, 5ELI, 5IEL2. −・
・The output signal of the silk matching circuit is input manually via SELm. On the other hand, in the shift operation state, the operation state selection signal MOD
Set ESEL to low level. At this time, the serial data input signal SIN is input to the data input D of the flip-flop FFO through the selector 5ELO, and the data input signal SIN of the next stage flip-flop FF1 is inputted to the data input D of the flip-flop FFO through the selector 5EL1. Signal Q is input. For flip-flops FF2 to FFm, similarly to flip-flop FFI, the output signal Q of the previous stage flip-flop is input to the data input via the selector, and the output signal Q of flip-flop FF'm is input to the serial data output signal S, Output as OU and 'T'. Therefore, flip-flops FFO to FFm have input terminals CLK, SIN, SO.
U and T are manually clocked, serial data manually,
It operates as a shift register with serial data output.

When verifying the operation of combinational circuits and sequential circuits using this circuit, when confirming and setting data set in each flip-flop in the normal operating state, switch to the shift operating state using the operating state selection signal MOD E S E L. Flip-flop FFO.

FFI, FF2.・・＋、FFm clock human power C
Shifted by LK, serial data output signal 5OU
At the same time, check the serial data input signal SIN.
Output data Q of flip-flops FFO to FFm is set. By repeating this operation several times, it is possible to shorten the test pattern for verifying the operation.

[Problem to be Solved by the Invention] The conventional digital circuit test circuit described above verifies the data set in the flip-flop during operation in the normal operating state during operation verification, and then continues to operate in the normal operating state. When operating with
After switching to the shift operation state with OD E S E L and checking the data set in all flip-flops with the serial data output 5OUT, the data set in the flip-flops at that time must be set again with the serial data input. Must not be. Therefore, a new setting operation is required, which takes extra time and effort, and data setting errors also occur.

[Means for Solving the Problems] The digital circuit test circuit of the present invention uses an operation state selection signal to convert the input signal of each flip-flop constituting the sequential circuit to the output signal of the normal ♀■ matching circuit and the previous stage flip-flop. This is a synchronous circuit that can operate all flip-flops as shift registers (This is a test circuit that is about to be tested. When all flip-flops and shift registers are operated, the first stage flip-flop is The main point is that a switching means for supplying the output signal of the final stage flip-flop to the input serial data of the flip-flop is provided.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In Figure 1, 5ELO, 5ELI, ..., SEL
m is a selector that can be switched between the normal operating state and the shift operating state by the operating state selection signal MOD E S E L, FFO, FFI, ..., FF111 is D
type flip-flop, SEL is the first stage flip-flop FFO in response to the loop control signal LOOPSEL.
Serial data input signal of STN
and the output Q of the final stage flip-flop FFm. Return control signal LOOP
Since SEL is valid only in the shift operation state, the operation in the shift operation state will be described here.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention. First of all, flip-flop F in section A
Confirmation of data set in FO, FFI, ..., FFQ will be explained.

When the operating state selection signal MODESEL is set to a low level and the return control signal LOOPSEL is set to a low level in section A, the data output Qrn of the flip-flop FFm is outputted from the serial data output 5OUT and simultaneously outputted from the flip-flop FFO via the selectors SEL and 5ELO.
is input to the data input DO. On the other hand, the data output QO of the flip-flop FFO is inputted to the data input D1 of the flip-flop FFI via the selector 5ELI.

Flip-flop FF2. ..., FFQ data input D2. . . , Dm is also input with the data output of the flip-flop in the previous stage. And when the clock is input from the lock CLK, the flip-flop F
FO, FFI, ...*, FFrn data input Do
, DI, . . . , Dm are set to each flip-flop, followed by outputs QO, Ql.

..., are sequentially output to Qm. As a result, before the clock is input from the serial data output 5OUT, FFrr
Data Qm-1 set at t-1 is output.

By repeating these operations m times, FFO is obtained from the serial data output 5OUT.

FF 1. ..., all the data set in FFm is output, and FFO, FFI, ....

F F m is set to the state before the clock is input in section A.

Next, flip-flop FFO in section B.

Confirmation of data set in FFI, . . . , FFm and data settings of some flip-flops will be explained. Here, flip-flops FF1 and FF
Suppose that only the data of O is rewritten.

In section B, the operating state selection signal MOD E S E
Set L to low level and return control signal L00PSEL
is set to a high level only during the first clock and the m-1th clock, and is set to a low level at other times.

When the return control signal LOOPSEL is at a high level, it is FF.
Since the data from the serial data input SIN is input to the data input D and 0 of O through the selectors SEL and 5ELO, input the data Drn to be set to FFm during the 1st clock, and also input the data Drn set to FFm during the 1st clock. F during the clock
To input data D1 to be set in FI, enter FFI and F
DI and Dm are respectively set for Fm, and FFI and F
Flip-flops other than Fm have section B as well as section A.
The data before the clock is input is set, and the serial data output 5OUT outputs FFO, FFI,
..., all data set in FFQ are output.

By performing these operations, even if the normal operating state is switched to the shift operating state and the data set in the flip-flop is output, the normal operating state can be continued again. It is also possible to continue normal operation by rewriting data in some flip-flops.

[Operations and Effects of the Invention] As explained above, the digital circuit test circuit of the present invention can switch from the normal operating state by switching the serial data input of the first-stage flip-flop to the output signal of the last-stage flip-flop using a return control signal. When switching to the shift operating state and checking the data set in the flip-flop, it is possible to continue the normal operating state again without having to be conscious of the data set in the flip-flop and enter the serial data manually. I can do what I want to do. It is also possible to rewrite only the data in some flip-flops. Therefore, there will be no data setting errors when checking the data set in the flip-flop in the shift operation state during circuit operation verification.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the embodiment of FIG. 1, and FIG. 3 is a block diagram showing a conventional example. F F O-F F m...Flip-flop, S
ELO-SELm...Selector, SEL...Selector (switching means). Patent Applicant: NEC Corporation Representative, Patent Attorney: Kiyoshi Kuwai − No. 1

Claims (1)

[Claims] The input signal of each flip-flop that makes up the sequential circuit is switched between the output signal of the normal combinational circuit and the output signal of the previous stage flip-flop using the operating state selection signal, and all flip-flops are added to a synchronous circuit that can operate as a shift register. In test circuits for digital circuits,
A test circuit for a digital circuit characterized by having a switching means for supplying an output signal of a final stage flip-flop to a serial data input of a first stage flip-flop by a return control signal when all flip-flops are operated as a shift register.