JPH03108068A - Electrical inspection system for logic circuit - Google Patents

Abstract

PURPOSE:To discover connection errors due to technology conditions early and automatically by executing a condition check with the technology correspondence in a logic circuit diagram in which symbols that possess different technology coexist. CONSTITUTION:When the logic circuit information of a circuit information file is inputted to an input part 3, the information of symbols which are connected in a net in units of one net are fetched, and the technology information for all symbols are obtained from an information file 6. Next, the flow of electricity is decided by the input/output attribution of the pin of the symbol connected to a net, and thereby, the checking of the connection condition of the transmission technology and reception technology is executed by a connecting condition storage part 8. And, the information of the checked result is outputted to a checked information file 7. Next, the check is executed to all the nets, and the results are filed in the file 7. Thus, the connection errors of technology correspondence can be discovered early.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electrical inspection method for logic circuits, and in particular to connection of logic elements having the same functionality but different electrical ratings and prices. This article relates to an electrical inspection method for logic circuit diagrams to be tested.

[Conventional technology]

In the conventional electrical inspection method for this type of logic circuit, the designer of the logic circuit visually traces the connections in the circuit and determines which circuit symbol (symbol) has specific characteristics (hereinafter referred to as technology). It was decided whether or not the connection was permissible based on whether electricity flowed to the symbol with the technology.

[Problem to be solved by the invention]

The conventional electrical inspection method for logic circuits described above has the disadvantage that connection errors due to technology conditions often remain undiscovered on the logic circuit diagram, resulting in a deterioration in design quality.

[Means to solve the problem]

The electrical inspection method for logic circuits of the present invention includes a main memory that stores program data necessary for arithmetic processing, a CPU that executes arithmetic processing based on the program data, an input/output section for processing data, and a logic circuit diagram. A circuit information file in which circuit information is stored in advance, a unique characteristic information file in which unique characteristics of circuit symbols are defined and stored, and a connection condition storage unit corresponding to unique characteristics in which connection conditions corresponding to the unique characteristics are defined and stored in advance. , a connection condition check unit corresponding to unique characteristics that checks whether or not the connection is allowed depending on the attributes of the input/output terminals of the circuit symbols connected to each net of the logic circuit, and stores the results of checking the connection conditions of all nets. It has a check information file.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment includes a main memory 2 that stores program data necessary for arithmetic processing, a CPU that executes arithmetic processing using the program data in the main memory 2, input/output units 3 and 4 for processing data, and a logic circuit diagram. A circuit information file 5 in which circuit information is stored in advance and a circuit symbol (symbol)
A technology information file 6 that defines and stores the unique characteristics (technology) of the technology, and a technology-compatible connection condition storage section 8 that stores connection conditions that are compatible with the technology defined in advance.
, a technology-compatible connection condition checking unit 9 that checks whether or not the connection is permissible based on the attributes of the input/output terminals of the symbols connected to each net, and a check information file 7 that stores the results of checking the connection conditions of all nets. It is composed of

FIG. 2 is a flowchart illustrating the operation of this embodiment, FIG. 3 is a diagram illustrating an example of whether technology-compatible connections are possible, and FIG. 4 is an example of a technology information file that defines and stores the technology of a symbol. The figure shown in FIG. 5 and FIG. 5 are diagrams showing an example of a logic circuit.

Next, the operation of this embodiment will be explained using the flowchart shown in FIG.
This will be explained with reference to FIGS. 3, 4, and 5. Electrical flow conditions corresponding to technology are defined in advance (FIG. 2, 11) and stored in the technology-compatible connection condition storage section 7. When the logic circuit information in the circuit information file 5 is input from the input section 3, information on symbols connected to each net is taken in (FIG. 2, 13). In the example shown in FIG. 5, information on symbols a, b, c, and d connected to the net 201 is taken in.

Furthermore, regarding the technology of symbols connected to the net, information about the technology of all symbols is obtained by searching from the technology information file 6 in which symbol technologies are defined (FIG. 2, 16). Symbol a in FIG. Information about technology B is obtained from the technology information file shown in FIG. 4, information about symbol b is technology B, symbol C is technology A, and symbol d is technology C.

Next, the flow of electricity is determined by the combination of the input and output attributes of the bins of all symbols connected to one net (Fig. 2, 17).

In the case of the net 201 in Figure 5, since the combination of input and output attributes of the bins of all connected symbols is output, input, input, input, the electric flow X flowing from the output bin to each input bin is It turns out that there is something. Through the flow of electricity, the connection conditions between the technology of the transmitting side symbol and the technology of the receiving side symbol are checked by the technology compatible connection condition storage unit 8, which obtains information on the conditions. In the net 201 in FIG. 5, the connection conditions of the connection 202 from the transmitting side symbol a to the receiving side symbol b are checked, the connection 203 from the transmitting side symbol a to the receiving side symbol C is checked, and the connection condition from the transmitting side symbol a to the receiving side is checked. Three connection conditions of the connection 204 of symbol d are checked. The technology of the transmitting symbol a of the connection 202 is technology B (FIG. 4, 41), and the receiving symbol is symbol b.
technology is technology B (Fig. 4, 42), and it is found that the connection from sending technology B to receiving technology B is possible (○) (Fig. 3, 38), and similarly, connection 203 is connected to receiving technology from sending technology B. Technology A cannot be connected (×
) (Figure 3 32), it is found that the connection 204 is a connection from technology B to technology C and is possible (O) (Figure 3 33), and it is found that the net 201 in Figure 5 has one connection that is not possible. . The check result information is output to the check information file 7 on the net. The above series of processing technology compatible connection condition checking means were performed on all networks, and Figure 2.1
If the end is determined in step 4, the operation ends.

〔Effect of the invention〕

As explained above, the present invention provides current, voltage, speed,
For technologies determined by different heat 2 prices, etc., in logic circuit diagrams where symbols with different technologies are mixed, by checking conditions based on technology support, automatically discover connections that are not allowed with technology support. This has the effect that errors can be corrected at an early stage and the quality of logic circuit diagrams can be improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a flowchart for explaining the operation of this embodiment, Fig. 3 is a diagram showing an example of technology-compatible connection conditions, and Fig. 4 is technology information. FIG. 5 is a diagram showing an example of the contents of a file, and FIG. 5 is a diagram showing an example of a logic circuit. 1...CPU, 2...Memory, 3...Input section, 4
... Output section, 5... Circuit information file, 6... Technology information file, 7... Net check information file, 8... Technology compatible connection condition storage section, 9
...Technology compatible connection condition checking section.

Claims (2)

[Claims] (1) A main memory that stores program data necessary for arithmetic processing, a CPU that executes arithmetic processing based on the program data, an input/output unit for processing data, and circuit information in which circuit information of a logic circuit diagram is stored in advance. Logic characterized by having a file, a unique characteristic information file that defines and stores the unique characteristics of a circuit symbol, and a unique characteristic corresponding connection condition storage section that defines and stores connection conditions corresponding to the unique characteristics in advance. Electrical testing method for circuits. (2) A connection condition check unit corresponding to unique characteristics that checks whether or not the connection is allowed depending on the attributes of the input/output terminals of the circuit symbol connected to each net of the logic circuit, and stores the check results of the connection conditions of all nets. 2. The electrical testing method for logic circuits according to claim 1, further comprising a check information file for checking.