JPH0744258B2 - CML type gate LSI - Google Patents
CML type gate LSIInfo
- Publication number
- JPH0744258B2 JPH0744258B2 JP62194953A JP19495387A JPH0744258B2 JP H0744258 B2 JPH0744258 B2 JP H0744258B2 JP 62194953 A JP62194953 A JP 62194953A JP 19495387 A JP19495387 A JP 19495387A JP H0744258 B2 JPH0744258 B2 JP H0744258B2
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- gate array
- type gate
- cml
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はCML型ゲートアレーLSI、特に複数の端子と入力
回路と出力回路とを有し、多品種を構成する大規模なCM
L型ゲートアレーLSIに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a CML type gate array LSI, and particularly to a large-scale CM having a plurality of terminals, an input circuit and an output circuit, which constitutes a large variety of products.
L type gate array LSI.
従来、この種のCML型ゲートアレーLSIは配線系のみの変
更により論理の異なる多数の品種を作ることができ、入
力回路および出力回路の配置と複数の端子との接続は作
成しようとするLSIの論理回路から決められるだけであ
る。従って、これらの品種が同様な論理を有する場合
は、それぞれの入力回路と出力回路との配置および端子
接続もほぼ同様なものとなる。Conventionally, this kind of CML type gate array LSI can make a large number of products with different logic by changing only the wiring system, and the layout of the input circuit and output circuit and the connection with multiple terminals are It can only be determined from the logic circuit. Therefore, when these types of products have the same logic, the arrangement of the input circuits and the output circuits and the terminal connections are also substantially the same.
上述した従来のCML型ゲートアレーLSIは入力回路および
出力回路の配置、およびそれらの回路と複数の端子との
接続が論理回路によってのみ決まるため、１つのゲート
アレーにおいて多数の個別の品種を作った場合、全品種
で端子に関する規則性が全くなく、配線完了の製品は必
ず品種を明らかにして取扱わねばならないと云う問題点
を有している。In the conventional CML type gate array LSI described above, the layout of the input circuit and the output circuit and the connection between these circuits and a plurality of terminals are determined only by the logic circuit. In this case, there is a problem that all products have no regularity regarding terminals and that products for which wiring is completed must always be handled by clarifying the product type.
本発明の目的は、CML型ゲートアレーLSIの端子の中の少
なくとも特定の複数の端子に接続される入力回路と出力
回路との組合せを品種によって異なるものとすることに
よって、電気的に品種を特定することのできるCML型ゲ
ートアレーLSIを提供することにある。An object of the present invention is to electrically specify a product type by making a combination of an input circuit and an output circuit connected to at least a plurality of specific terminals of a CML type gate array LSI different depending on the product type. The purpose is to provide a CML type gate array LSI that can be used.
本発明のCML型ゲートアレーLSIは複数の端子とその端子
に接続される複数の入力回路と出力回路とを有するゲー
トアレーLSIにおいて、前記各端子の中の特定の複数端
子にゲートアレーの品種に対応して予め設定された組合
せに従ってCML型の入力回路および出力回路を接続する
ことにより、ゲートアレーの品種を識別できるようにし
たことを特徴とする。The CML type gate array LSI of the present invention is a gate array LSI having a plurality of terminals and a plurality of input circuits and output circuits connected to the terminals. It is characterized in that the type of the gate array can be identified by connecting the CML type input circuit and the output circuit according to the corresponding preset combination.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のレイアウト図で、（ａ）は
Ａ品種を示し、（ｂ）はＢ品種を示す。（ａ）および
（ｂ）は共に同一のCML型ゲートアレーを用いて配線系
の変更によりそれぞれ必要な論理を有していて、端子１
〜４が特定端子である場合を示している。（ａ）のＡ品
種は端子１と２とにそれぞれ出力回路を接続し、端子３
と４とにはそれぞれ入力回路を接続している。また
（ｂ）のＢ品種では端子１と３とにそれぞれ入力回路を
接続し、端子２と４とには出力回路が接続されている。FIG. 1 is a layout diagram of an embodiment of the present invention, in which (a) shows A type and (b) shows B type. Both (a) and (b) have the necessary logic by changing the wiring system using the same CML type gate array.
4 shows the case where 4 are specific terminals. In the A type of (a), output circuits are connected to terminals 1 and 2, respectively.
Input circuits are connected to 4 and 4, respectively. In the B product of (b), an input circuit is connected to terminals 1 and 3, respectively, and an output circuit is connected to terminals 2 and 4.
第１表は第１図に用いられるCML型ゲートアレーの特定
端子の入力と出力との組合せを示す表である。ここでＡ
品種の端子１〜４は第１図（ａ）で示した組合せを有
し、Ｂ品種の端子１〜４は第１図（ｂ）で示した組合せ
を有し、さらにその他の品種についても他のそれぞれ異
なった組合せを有している即ち、この端子１〜４の入力
と出力との組合せは各種によって全て異なっている。Table 1 is a table showing combinations of inputs and outputs of specific terminals of the CML type gate array used in FIG. Where A
The terminals 1 to 4 of the product type have the combination shown in FIG. 1 (a), the terminals 1 to 4 of the product type B have the combination shown in FIG. 1 (b), and other types are also different. That is, the combinations of the inputs and outputs of the terminals 1 to 4 are all different from each other.
以上の実施例では４端子のみを特定端子としたが、更に
多数の端子を特定端子とすることにより、入力と出力と
の組合せのそれぞれと多数の品種とを対応させることが
できることは明らかである。 In the above embodiment, only four terminals are designated as specific terminals, but it is obvious that each combination of input and output can be made to correspond to a large number of types by making more terminals as specific terminals. .
なお、こゝで第１図のCML型ゲートアレーの電気検査の
方法について述べる。The method of electrical inspection of the CML type gate array shown in FIG. 1 will be described here.
第２図（ａ）は第１図（ａ）および（ｂ）の出力回路の
詳細回路図、第２図（ｂ）は第１図（ａ）および（ｂ）
の入力回路の詳細回路図である。さて、端子１〜４のそ
れぞれに1mAの一定電流を流した場合、第２図（ａ）で
示す出力回路では出力抵抗50Ωと1mAの電流とによって5
0mVの電圧が端子に発生する。また第２図（ｂ）で示す
入力回路では入力トランジスタのベースを通してコレク
タ側に流れる電流によりVBC0.8Vの電圧が端子に発生
する。従ってある端子に1mAの一定電流を流しその端子
電圧を測定することにより、その端子が入力回路と出力
回路のどちらに接続されているかを知ることが出来る。
この測定を第１図（ａ）及び（ｂ）に示した端子１〜４
に実施し、その結果を第１表の組合せと照合することに
より多数の品種の中のどの品種であるかを識別出来る。
これにより、多数品種の電気検査を行なう場合、人手に
より個々にどの品種か意識して検査プログラムを選択し
なくとも、前記した測定をテスタで行なうことにより、
テスタ自身が自動的に品種を識別し、検査プログラムを
選択して検査を行なうことができる。2 (a) is a detailed circuit diagram of the output circuit of FIGS. 1 (a) and 1 (b), and FIG. 2 (b) is shown in FIGS. 1 (a) and 1 (b).
3 is a detailed circuit diagram of the input circuit of FIG. Now, when a constant current of to 1 mA to each of the terminals 1-4, the output circuit shown in FIG. 2 (a) by the current of the output resistance 50Ω and 1 mA 5
0 mV voltage is generated at the terminals. In the input circuit shown in FIG. 2 (b), a voltage of V BC 0.8V is generated at the terminal due to the current flowing to the collector side through the base of the input transistor. Therefore, by flowing a constant current of 1 mA to a certain terminal and measuring the voltage at that terminal, it is possible to know whether the terminal is connected to the input circuit or the output circuit.
This measurement shows the terminals 1 to 4 shown in FIGS. 1 (a) and 1 (b).
Then, by comparing the result with the combination shown in Table 1, it is possible to identify which kind of many kinds.
By this, when conducting electrical inspections of a large number of products, even if the inspection program is not manually selected and the inspection program is manually selected, it is possible to perform the above-mentioned measurement with a tester.
The tester itself can automatically identify the product type and select an inspection program to perform the inspection.
以上説明したように本発明は、同一のCML型ゲートアレ
ーにより作られる多数の品種に対して、特定の複数の端
子について予め設定されたそれぞれ異なった組合せに従
ってCML型の入力回路および出力回路を接続することに
より、電気的に品種を識別することが出来ると云う効果
がある。As described above, the present invention connects CML type input circuits and output circuits to a large number of products made by the same CML type gate array in accordance with different combinations preset for specific terminals. By doing so, there is an effect that the product type can be electrically identified.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
のレイアウト図、第２図（ａ）は第１図の出力回路の回
路図、第２図（ｂ）は第１図の入力回路の回路図であ
る。1 (a) and 1 (b) are layout diagrams of an embodiment of the present invention, FIG. 2 (a) is a circuit diagram of the output circuit of FIG. 1, and FIG. 2 (b) is of FIG. It is a circuit diagram of an input circuit.
Claims (1)
の入力回路および出力回路を有するゲートアレーLSIに
おいて、前記各端子の中の特定の複数端子にゲートアレ
ーの品種に対応して予め設定された組合せに従ってCML
型の入力回路および出力回路を接続することにより、ゲ
ートアレーの品種を識別できるようにしたことを特徴と
するCML型ゲートアレーLSI。1. A gate array LSI having a plurality of terminals and a plurality of input circuits and output circuits connected to the terminals, wherein a plurality of specific terminals among the terminals are preset in accordance with the kind of the gate array. CML according to the specified combination
A CML type gate array LSI characterized in that the type of gate array can be identified by connecting the input and output circuits of each type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62194953A JPH0744258B2 (en) | 1987-08-03 | 1987-08-03 | CML type gate LSI |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62194953A JPH0744258B2 (en) | 1987-08-03 | 1987-08-03 | CML type gate LSI |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6437847A JPS6437847A (en) | 1989-02-08 |
| JPH0744258B2 true JPH0744258B2 (en) | 1995-05-15 |
Family
ID=16333073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62194953A Expired - Lifetime JPH0744258B2 (en) | 1987-08-03 | 1987-08-03 | CML type gate LSI |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744258B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002050910A1 (en) * | 2000-12-01 | 2002-06-27 | Hitachi, Ltd | Semiconductor integrated circuit device identifying method, semiconductor integrated circuit device producing method, and semiconductor integrated circuit device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274341A (en) * | 1984-12-25 | 1986-12-04 | Nec Corp | Semiconductor logic device |
-
1987
- 1987-08-03 JP JP62194953A patent/JPH0744258B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| 電子技術第２５巻第１３号、Ｐ．２９−３４ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6437847A (en) | 1989-02-08 |
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