JPS6437847A - Cml type gate array lsi - Google Patents
Cml type gate array lsiInfo
- Publication number
- JPS6437847A JPS6437847A JP62194953A JP19495387A JPS6437847A JP S6437847 A JPS6437847 A JP S6437847A JP 62194953 A JP62194953 A JP 62194953A JP 19495387 A JP19495387 A JP 19495387A JP S6437847 A JPS6437847 A JP S6437847A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- combination
- type
- gate array
- setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE:To enable the discrimination of types electrically by connecting an input circuit and an output circuit according to the combination of the setting of a plurality of specific different terminals. CONSTITUTION:A CMU output circuit is connected to terminals 1, 2 and a CML input circuit to terminals 3, 4 on the basis of the previously set combination of the specific four terminals 1-4 for a CML type gate array LSI, thus manufacturing a type A. When the combination of the setting of the terminals 1-4 is changed and a type B, a type C... are manufactured and each of the terminals connected to the output circuit and the terminals connected to the input circuit are supplied with constant currents, terminal voltage is made to differ in response to each of an output resistor and an input transistor, the combination of the setting of the terminals is decided and the types are discriminated electrically without sticking labels, etc.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62194953A JPH0744258B2 (en) | 1987-08-03 | 1987-08-03 | CML type gate LSI |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62194953A JPH0744258B2 (en) | 1987-08-03 | 1987-08-03 | CML type gate LSI |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6437847A true JPS6437847A (en) | 1989-02-08 |
JPH0744258B2 JPH0744258B2 (en) | 1995-05-15 |
Family
ID=16333073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62194953A Expired - Lifetime JPH0744258B2 (en) | 1987-08-03 | 1987-08-03 | CML type gate LSI |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0744258B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002045139A1 (en) * | 2000-12-01 | 2002-06-06 | Hitachi, Ltd | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61274341A (en) * | 1984-12-25 | 1986-12-04 | Nec Corp | Semiconductor logic device |
-
1987
- 1987-08-03 JP JP62194953A patent/JPH0744258B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61274341A (en) * | 1984-12-25 | 1986-12-04 | Nec Corp | Semiconductor logic device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002045139A1 (en) * | 2000-12-01 | 2002-06-06 | Hitachi, Ltd | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
WO2002050910A1 (en) * | 2000-12-01 | 2002-06-27 | Hitachi, Ltd | Semiconductor integrated circuit device identifying method, semiconductor integrated circuit device producing method, and semiconductor integrated circuit device |
US6941536B2 (en) | 2000-12-01 | 2005-09-06 | Hitachi, Ltd. | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
Also Published As
Publication number | Publication date |
---|---|
JPH0744258B2 (en) | 1995-05-15 |
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