JP2002296323A - Circuit and method for scan test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit and a method for scan test, wherein a circuit scale is reduced, as compared with that in a conventional inspection and the test time can be shortened when a combinational circuit is inspected by using the scan test. SOLUTION: The input of the combinational circuit 35 is set by an FF 34, and its operating result is selected by a selector 32 to be output to the outside of a semiconductor integrated circuit 31 via a scan path, to which an FF 33 is connected. Thereby, the inspection of the combinational circuit by using the scan test can be executed by reducing the circuit scale, as compared with that in the conventional inspection, the number of stages of a scan chain is reduced because the FFs are deleted, and the test time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scan test of a semiconductor integrated circuit for simultaneously testing a combinational circuit.

[0002]

2. Description of the Related Art Usually, a combinational circuit is inspected during a scan test in order to obtain a high failure detection rate in an inspection of a semiconductor integrated circuit. In this case, in order to shorten the input setting procedure of the combinational circuit and insert the combinational circuit into the scan path, the input to the target combinational circuit is received by a flip-flop (hereinafter, referred to as FF),
The output needs to be driven by FF.

FIG. 3 is a configuration diagram of a conventional semiconductor integrated circuit for performing a scan test. In FIG. 3, reference numeral 11 denotes a semiconductor integrated circuit, 12 denotes an FF, 13 denotes an FF, 14 denotes a combination circuit, 15 denotes a combination circuit, 16 denotes an FF for directly inputting a signal to the combination circuit 15 during a scan test, 1
Reference numeral 7 denotes a selector, and reference numeral 18 denotes an FF that outputs the output of the combinational circuit 14 to the outside of the semiconductor integrated circuit 11 through a scan test. Semiconductor integrated circuit 1 for performing a scan test
1 is provided with FF12 as the first stage input of the scan path,
An FF 13 is provided as a final stage output of the scan path. At the time of the scan test, the input of the combinational circuit 14 is the FF 12
Output from the semiconductor integrated circuit 1 via the FF 18.
1 is output to the outside. Similarly, the input of the combination circuit 15 is selected from the signal from the FF 16 by the selector 17, and the output is output to the outside of the semiconductor integrated circuit 11 via the FF 13.

The operation of the semiconductor integrated circuit configured as described above will be described below. During normal operation, first,
The selector 17 selects an input signal from outside the semiconductor integrated circuit 11 and inputs the signal to the combination circuit 15. As a result, the combinational circuit 15 is operated, and its output signal is output to the outside of the semiconductor integrated circuit 11 via the FF 13. The input of the FF 12 is input from outside the semiconductor integrated circuit 11, and the output signal is input to the combinational circuit 14 to operate the combinational circuit 14, and the semiconductor integrated circuit 1
1 Output to outside.

At the time of a scan test, first, the selector 1
7, the output signal of the FF 16 is selected. Next, an input for testing the combinational circuit 15 is set based on the output signal of the selected FF 16, and the combinational circuit 15 is operated. At the same time, an input for testing the combinational circuit 14 is set in the FF 12 using the scan path. Next, the output signal of the combinational circuit 15 is output to the outside of the semiconductor integrated circuit 11 through a scan test connected to the FF 13, and the output value is confirmed. At the same time, the output signal of the combinational circuit 14 is output to the outside of the semiconductor integrated circuit 11 via the scan test connected to the FF 18 to check the output value.

[0006] With the above configuration, it is possible to reduce the number of steps for setting the input during the test of the combinational circuit, to set the input of the combinational circuit through the scan path and to obtain the result of the semiconductor integrated circuit 1.
By performing the output to the outside, the failure detection rate of the semiconductor integrated circuit 11 is improved in the scan test.

However, as described above, in the conventional scan test circuit, an FF is inserted before the combination circuit in order to set an input, and an output is output to the outside of the semiconductor integrated circuit by a scan test. It is necessary to insert the FF at the subsequent stage. For this reason, there is a problem that the circuit scale increases due to the addition of the FF, and the test time increases because the number of stages of the scan chain increases due to the addition of the FF.

[0008]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. In addition, it is possible to execute a test of a combinational circuit using a scan test while suppressing an increase in circuit scale, and to increase a test time. It is an object of the present invention to provide a scan test circuit and a scan test method capable of suppressing the above.

[0009]

In order to achieve the above object, a scan test circuit according to claim 1 of the present invention comprises:
A scan test circuit in a semiconductor integrated circuit,
A scan path including a first flip-flop and a second flip-flop; a logic circuit group formed by an arbitrary combinational circuit, the output signal of which is input to the first flip-flop; A selector circuit for selecting one of an output signal and an input signal to the logic circuit group during normal operation and inputting the selected signal to the logic circuit group; The circuit group is operated.

A scan test circuit according to a second aspect of the present invention is a scan test circuit in a semiconductor integrated circuit, wherein the scan test circuit includes a scan path including a first flip-flop and a second flip-flop, and an arbitrary combinational circuit. And a logic circuit group to which an output signal of the first flip-flop is input, and one of an output signal of the logic circuit group and an input signal to the flip-flop 2 during a normal operation is selected to generate the second flip-flop. And a selector circuit for inputting the output signal to the flip-flop, and outputting the output signal of the logic circuit group to the outside of the semiconductor integrated circuit via a scan path connected to the second flip-flop.

According to a third aspect of the present invention, in performing a scan test on a semiconductor integrated circuit having the scan test circuit according to the first aspect, a signal output from the second flip-flop by the scan test is supplied to the selector circuit. Selecting, and inputting the selected signal to the logic circuit group to operate the logic circuit group; and inputting a signal output from the logic circuit group to the first flip-flop to switch the logic circuit group. Outputting to outside the semiconductor integrated circuit via a campus.

According to a fourth aspect of the present invention, in the scan test of a semiconductor integrated circuit having the scan test circuit according to the second aspect, a signal output from the first flip-flop by the scan test is applied to the logic circuit. Operating the logic circuit group by inputting it to a group, selecting a signal output from the logic circuit group by the selector circuit, and inputting the selected signal to the second flip-flop. Outputting to outside the semiconductor integrated circuit via a scan path.

As described above, the inspection of the combinational circuit using the scan test can be executed while suppressing an increase in circuit scale, and an increase in test time can be suppressed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a semiconductor integrated circuit that performs a scan test according to the first embodiment of the present invention.

In FIG. 1, reference numeral 21 denotes a semiconductor integrated circuit for performing a scan test. Reference numeral 23 denotes a combinational circuit that operates upon input of a signal from outside the semiconductor integrated circuit 21. Reference numeral 24 denotes an FF at the last stage of the scan path of the semiconductor integrated circuit 21, and this output signal is output to the outside of the semiconductor integrated circuit 21. A selector 22 selects one of an output signal from the FF 24 and an input signal from outside the semiconductor integrated circuit 21 and inputs the selected signal to the combinational circuit 23. 25 is an FF for inputting the output signal of the combinational circuit
Then, at the time of the scan test, the output signal of the combinational circuit 23 is output to the outside of the semiconductor integrated circuit 21 through the scan path to which the FF 25 is connected.

In the above configuration, during the scan test, the output signal of the FF 24 is selected by the selector 22 and input to the combinational circuit 23, and the output signal of the combinational circuit 23 is output to the outside of the semiconductor integrated circuit 21 through the scan path to which the FF 25 is connected. I do. As a result, when testing the combinational circuit using the scan test, the input of the combinational circuit 23 can be set by using the existing FF without adding an unnecessary FF.

Here, the signal input to the selector 22 is defined as the output signal from the FF 24 and the signal from outside the semiconductor integrated circuit 21. However, it is not necessary to directly input the signal from outside the semiconductor integrated circuit 21. There is no problem even if other combinational circuits are included between them.

FIG. 2 is a configuration diagram of a semiconductor integrated circuit for performing a scan test according to the second embodiment of the present invention. FIG.
In the figure, 31 is a semiconductor integrated circuit for performing a scan test. Reference numeral 33 denotes a first stage FF of the scan path of the semiconductor integrated circuit 31. A combination circuit 35 outputs a signal to the outside of the semiconductor integrated circuit 31. Reference numeral 34 denotes an FF for inputting an input signal to the combinational circuit 35, and the combinational circuit 35 operates by this signal. A selector 32 selects one of the output signal of the combination circuit 35 and the input signal from outside the semiconductor integrated circuit 31 and inputs the selected signal to the FF 33.

In the above configuration, at the time of the scan test, first, the input of the combination circuit 35 is set through the FF 34 on the scan path, and the combination circuit 35 is operated. Next, the output signal of the combinational circuit 35 is selected by the selector 32 and input to the FF 33,
The output signal of the combinational circuit 35 is output to the outside of the semiconductor integrated circuit 31 through the scan path connected to. As a result, when testing the combinational circuit using the scan test, the output signal of the combinational circuit 35 can be output to the outside of the semiconductor integrated circuit 31 through the scan path without adding an unnecessary FF.

Here, the signal input to the selector 32 is defined as the output signal from the combinational circuit 35 and the signal from outside the semiconductor integrated circuit 31. However, it is necessary to directly input the signal from outside the semiconductor integrated circuit 31. There is no problem even if other combinational circuits are included in between.

As described above, the inspection of the combinational circuit using the scan test can be executed while suppressing an increase in circuit scale, and an increase in test time can be suppressed.

[0022]

As described above, according to the scan test circuit and the scan test method of the present invention, when performing a test of a combinational circuit using a scan test, the existing FF is used and the input of the combinational circuit is performed. The setting and the output of the operation result of the combinational circuit can be performed through the scan path. As a result, the inspection of the combinational circuit using the scan test can be executed while suppressing an increase in the circuit scale, and the increase in the test time can be suppressed since the number of scan chains is not increased because the number of FFs is not increased.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit that performs a scan test according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a semiconductor integrated circuit that performs a scan test according to a second embodiment of the present invention;

FIG. 3 is a configuration diagram of a conventional semiconductor integrated circuit that performs a scan test.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 semiconductor integrated circuit 12 FF 13 FF 14 combination circuit 15 combination circuit 16 FF 17 selector 18 FF 21 semiconductor integrated circuit 22 selector 23 combination circuit 24 FF 25 FF 31 semiconductor integrated circuit 32 selector 33 FF 34 FF 35 combination circuit

Claims (4)

[Claims] 1. A scan test circuit in a semiconductor integrated circuit, comprising: a scan path including a first flip-flop and a second flip-flop; and an optional combinational circuit, the output signal of which is the first flip-flop. A selector circuit that selects one of an output signal of the second flip-flop and an input signal to the logic circuit group during normal operation and inputs the selected signal to the logic circuit group. Has,
A scan test circuit, wherein the logic circuit group is operated by an output signal of the second flip-flop. 2. A scan test circuit in a semiconductor integrated circuit, comprising: a scan path including a first flip-flop and a second flip-flop; and an arbitrary combinational circuit, wherein an output signal of the first flip-flop is A logic circuit group to be input; and a selector circuit that selects one of an output signal of the logic circuit group and an input signal to the flip-flop 2 during a normal operation and inputs the selected signal to the second flip-flop. A scan test circuit for outputting an output signal of the logic circuit group to the outside of the semiconductor integrated circuit via a scan path to which a second flip-flop is connected. 3. A step of selecting a signal output from the second flip-flop by a scan test by the selector circuit when performing a scan test on the semiconductor integrated circuit having the scan test circuit according to claim 1. Inputting the output signal to the logic circuit group to operate the logic circuit group, and inputting the signal output from the logic circuit group to the first flip-flop and passing the signal through a scan path to the semiconductor integrated circuit. A scan test method having a step of outputting to the outside. 4. A scan circuit for a semiconductor integrated circuit having the scan test circuit according to claim 2, wherein a signal output from said first flip-flop by a scan test is input to said logic circuit group and said logic circuit is provided. Operating a group; selecting a signal output from the logic circuit group by the selector circuit; inputting the selected signal to the second flip-flop and passing the semiconductor integrated circuit through a scan path. Outputting to the outside of the scan test method.