JP2003121508A - Burn-in testing circuit of semiconductor integration circuit, and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the toggle ratio in the burn-in testing of a functional macros, and to suppress developing time of the burn-in test. SOLUTION: The burn-in test is performed using a memory BIST circuit 202, designed so as to preliminarily perform all tests necessary for confirming the operation of a memory device 201 for not only enhancing the toggle ratio in the burn-in test of the memory device, but also to suppress the developing time of the burn-in testing. Further, by performing the scanning design of the memory BIST circuit 202, the burn-in test of the memory BIST circuit 202 is performed efficiently, and the toggle ratio of the whole of the burn-in test can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burn-in test circuit in a semiconductor integrated circuit, and more particularly to a burn-in test circuit for a function macro.

[0002]

2. Description of the Related Art A burn-in test circuit of a semiconductor integrated circuit having a conventional function macro will be described with reference to a memory device as an example with reference to the drawings.

FIG. 3 is a block diagram of a burn-in test circuit of a conventional semiconductor integrated circuit. In the figure, 301 is a memory device, 302 is a burn-in test control circuit, and 303 is a test program. The memory device 30 of the test program 303 is controlled by the control circuit 302 during the burn-in test.
1 is controlled, and the burn-in test of the memory device 301 is executed by the test program 303. Here, the test program 303 is the memory device 30.
It is created corresponding to 1.

However, according to the burn-in test circuit of the conventional semiconductor integrated circuit and the method thereof, since the toggle rate of the memory device that can be verified is determined by the test program 303, the test program 303 cannot secure a sufficient toggle rate. There was a point. Also, to improve the toggle rate, test program 3
There is also a problem that the development time of 03 becomes long and the development time of burn-in test becomes long.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, a burn-in test circuit for a semiconductor integrated circuit and a method thereof according to the present invention improve a toggle rate in a burn-in test of a function macro and develop a burn-in test. The purpose is to save time.

[0006]

In order to achieve the above object, a burn-in test circuit for a semiconductor integrated circuit according to the present invention is
Alternatively, there are provided two or more function macros, a built-in self-test circuit that performs a test corresponding to the function macro, and a control circuit that controls performing a burn-in test of the function macro by the built-in self-test circuit during a burn-in test. However, it is characterized in that the burn-in test of the previous function macro is performed by the built-in self-test circuit during the burn-in test.

A burn-in test circuit for a semiconductor integrated circuit according to a second aspect is the burn-in test circuit for a semiconductor integrated circuit according to the first aspect, wherein the scan path is operated by designing the built-in self-test circuit as a scan path. The burn-in test of the built-in self-test circuit is performed.

According to a third aspect of the present invention, there is provided a burn-in test method for a semiconductor integrated circuit, wherein a burn-in test of a semiconductor integrated circuit having a function macro is carried out by performing a burn-in test of the function macro portion in correspondence with the function macro. It is characterized in that the function macro is operated by a self-test circuit.

According to a fourth aspect of the present invention, there is provided a burn-in test method for a semiconductor integrated circuit, wherein a burn-in test of a semiconductor integrated circuit having a function macro is carried out by performing a burn-in test of the function macro portion corresponding to the function macro. The method includes a step of operating the function macro by a self-test circuit to carry out the function macro, and a step of performing a burn-in test by scanning the built-in self-test circuit.

With the above structure, the toggle rate in the burn-in test of the semiconductor integrated circuit can be improved and the development time of the burn-in test can be suppressed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a configuration diagram showing a burn-in test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

In the figure, 101 is a memory device, and 102 is a memory device.
Is a memory BIST circuit, 103 is a control circuit, and during the burn-in test, the control circuit 103 is the memory BIST circuit 1
02 is controlled to verify the memory device 102. Here, since the memory BIST circuit 102 autonomously verifies the memory device 101 for a predetermined operation state, a high toggle rate can be secured and it is not necessary to develop a test pattern.

The operation of the burn-in test circuit of the semiconductor integrated circuit having the above configuration will be described below. Memory device 10
In the burn-in test of 1, the memory BIST circuit 102 is operated to carry out the burn-in test as in the normal test.

In the burn-in test, first, the control circuit 103 inputs a signal for starting the burn-in test of the memory device 101 to the memory BIST circuit 102.
Next, in the memory BIST circuit 102, a signal that autonomously reproduces a predetermined operation of the memory device 101 is input to the memory device 101 to test the memory device 101.
Finally, the output value of the memory device 101 is input to the memory BIST circuit 102 to determine whether the operation of the memory device 101 is good or bad, and the result is output to the control circuit 103.

As described above, according to the burn-in test circuit for the semiconductor integrated circuit and the method thereof according to the first embodiment of the present invention, it is designed to carry out all the tests necessary for confirming the operation of the memory device in advance. By performing the burn-in test using the BIST circuit, the toggle rate in the burn-in test of the memory device can be improved and the development time of the burn-in test can be suppressed.

(Second Embodiment) FIG. 2 is a block diagram showing a burn-in test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

In the figure, 201 is a memory device, and 202
Is a scan-designated memory BIST circuit, 203 is a control circuit, and 204 is a scan signal. During the burn-in test, the control circuit 203 controls the operation of the memory BIST circuit 202 and verifies the memory device 202. At this time, the memory BIST circuit 202 is operated by the scan signal 204.

The operation of the burn-in test circuit of the semiconductor integrated circuit having the above structure will be described below. Memory device 20
At the time of the burn-in test of 1, the memory BIST circuit 202 is operated to perform the burn-in test, as in the normal test.

Here, in the burn-in test of the memory device, first, the control circuit 203 causes the memory BIST circuit 20 to operate.
A signal for starting the test of the memory device 201 is input to 2. Next, in the memory BIST circuit 202, a signal that autonomously reproduces a predetermined operation of the memory device 201 is input to the memory device 201 to test the memory device 201. Finally, the output value of the memory device 201 is set to the memory BIS.
The result is input to the T circuit 202, the quality of the operation of the memory device 201 is determined, and the result is output to the control circuit 203. Also,
Scan signal 2 separately from burn-in test of memory device
A scan signal is input from 04, and a burn-in test of the scan-designed memory BIST circuit 202 is performed.

As described above, according to the burn-in test circuit for semiconductor integrated circuits and the method thereof according to the second embodiment of the present invention, the burn-in test of the memory BIST circuit is efficiently performed by scan designing the memory BIST circuit. It can also improve the toggle rate of the entire burn-in test.

In the above description, the memory device has been described as an example of the function macro, but not limited to the memory device, any function macro can be similarly implemented.

[0022]

As described above, according to the burn-in test circuit for a semiconductor integrated circuit and the method thereof according to the present invention,
By performing a burn-in test using a BIST circuit designed in advance to perform all the tests necessary for confirming the operation of the function macro, the toggle rate in the burn-in test of the function macro is improved and the burn-in test is performed. Development time can be suppressed. further,
By designing a scan for the BIST circuit,
The burn-in test of the circuit can be performed efficiently and the toggle rate of the entire burn-in test can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a burn-in test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a burn-in test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a burn-in test circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

101 memory device 102 memory BIST circuit 103 control circuit 201 memory device 202 memory BIST circuit 203 control circuit 204 scan signal 301 memory device 302 control circuit 303 test program

Claims (4)

[Claims] 1. A one or more function macro, a built-in self-test circuit that performs a test corresponding to the function macro, and a control that performs a burn-in test of the function macro by the built-in self-test circuit during a burn-in test. A burn-in test circuit for a semiconductor integrated circuit, which has a control circuit for performing a burn-in test, and performs a burn-in test of a function macro in the previous period by a built-in self-test circuit. 2. The burn-in of a semiconductor integrated circuit according to claim 1, wherein the built-in self-test circuit is designed as a scan path to operate the scan path to carry out a burn-in test of the built-in self-test circuit. Test circuit. 3. When performing a burn-in test of a semiconductor integrated circuit having a function macro, the burn-in test of the function macro portion is performed by operating the function macro by a built-in self-test circuit that performs a test corresponding to the function macro. A burn-in test method for a semiconductor integrated circuit, comprising: 4. When performing a burn-in test of a semiconductor integrated circuit having a function macro, the burn-in test of the function macro portion is performed by operating the function macro by a built-in self-test circuit that performs a test corresponding to the function macro. And a step of performing a burn-in test by scanning the built-in self-test circuit.