JPH11219385A - Delay fault detection method for integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay fault detection method capable of suppressing the increase of inspection time even in a large-scale LSI and being realized by a relatively small-scale circuit for detection. SOLUTION: By selecting a route to be inspected from the result of a static actual wiring capacity simulation step 105, the scale of an additional means required for an inspection is suppressed. Further, by setting the initial state of the route to be inspected from a scanning route in an inversion means and control means insertion step 111, an initial value is optionally set without increasing a circuit scale. Delay fault detection is parallelly performed by inverting the state of the start point of the route by using the inversion means of simple constitution and the inspection time for the delay fault detection in a large-scale integrated circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting an internal delay fault in an LSI (Large Scale Integrated Circuit), and more particularly, to a method for detecting a delay fault using a scan path formed by cascading scanned flip-flops. About the method.

[0002]

2. Description of the Related Art As a conventional delay fault detection method using a scan path, there is a method described in, for example, Japanese Patent Publication No. 52-2863. In this method, an initial state is set by a shift operation, and a test pattern and a clock signal for taking in the test pattern are provided so that a signal value after the change signal is set as a data input of the flip-flop, and a state of the flip-flop is provided. To detect a delay fault. In another method disclosed in Japanese Patent Publication No. 64-43773, detection of a delay failure without scanning is performed by externally applying a control signal.
More generally, a method of detecting a delay fault by using a test pattern for function verification has been used.

[0003]

However, in the method of detecting a delay fault by substituting a test pattern for function verification, it is unclear whether or not a true critical path has been tested.

In the method of detecting a delay fault using only a scan path, it is easy to set an initial state, but it is very difficult to generate a test pattern in which a signal value after a change signal changes is set. Have difficulty. Furthermore, it can cause a flip-flop state change that does not need to be changed, and it is still unclear whether the true critical path is being tested.

In the method of detecting a delay fault independent of a scan path by applying a control signal from the outside, a delay fault can be detected at an arbitrary location. However, a control circuit is liable to be large and an external signal is applied. Therefore, it is difficult to detect a plurality of delay faults in parallel, and there is a problem that it is not possible to adapt to large-scale LSI.

The present invention solves the above-mentioned conventional problems, and provides a delay fault detection method which can suppress an increase in test time even in a large-scale LSI and can be realized by a relatively small-scale detection circuit. The purpose is to:

[0007]

A method for detecting a delay fault in an integrated circuit according to the present invention includes a first step of generating a netlist obtained by scanning flip-flops, and performing a static delay simulation on the netlist. A second step of extracting a path in which a delay fault is likely to occur, extracting information of a flip-flop or an external input signal serving as a starting point of the path, and initial value information in a case where the path is likely to cause a delay fault. Based on the external input signal information and the initial value information, a fourth step of inserting the inverting means for inverting the state of the flip-flop serving as the starting point, its control means, and the initial value holding means. After setting an initial value through the scan path, a signal for controlling the control means is given, and a state change of the detected path is generated to detect the delay fault. Cormorant and a fifth step.

According to the above configuration, the true critical path is selected from the result of the static delay simulation, and the start point information of the state change and the initial value information are extracted. Next, these values are given using a scan path used for logical fault detection, and a state change for detecting a delay fault, that is, by adding inversion means to a flip-flop that generates signal inversion, The true critical path can be tested in parallel on each part of the integrated circuit. Further, by extracting a path in which a delay fault is likely to occur by the static delay simulation and performing the inspection intensively, an increase in the size of the detection circuit and an increase in the test pattern can be suppressed.

Preferably, in the second step, a true critical path is determined by using an actual wiring capacitance obtained from a layout. It is also preferable to generate a list of the margin of operation time from the result of the static delay simulation, and select a path with a small margin as a path that easily causes a delay fault. The increase is suppressed.

[0010] It is preferable that the control means is scanned and a control signal is given through a scan path. Thereby, parallel control of the state inversion of an arbitrary flip-flop can be realized.

Further, it is preferable that the inverting means is configured to select an inverted signal of the output signal of the scan flip-flop or a non-scan input signal according to a selection signal. Alternatively, the configuration may be such that the inverted signal of the output signal of the scan flip-flop or the scan input signal is selected according to the selection signal. As a result, the configuration of the inversion means is minimized, and an increase in the circuit scale is suppressed. Further, the inverting means and the initial value holding means may be configured to select the output signal of the preceding scanning flip-flop on the scan path or the inverted signal thereof according to the selection signal. According to this configuration, only processing is performed on the scan path, and it is possible to prevent a delay or the like from being applied to the normal path.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a flowchart of a delay fault detecting method according to an embodiment of the present invention. Step 10
In step 102, scan insertion is performed on the netlist generated in step 1, and layout CAD is performed in step 103.
And so on. Based on the layout result, the actual wiring capacitance of each signal line is extracted in step 104,
In step 105, a static actual wiring capacitance delay simulation is performed.

From the simulation results, step 10
In step 6, a delay margin list is generated. Step 10
In step 8, based on the threshold 107, a route having a margin equal to or smaller than the threshold is selected from the delay margin list. In step 109, information of an input flip-flop or an external input signal for inverting the state in the selected path is extracted as start point information. Alternatively, in step 110, the initial value information of the selected route before performing the state inversion operation is extracted.

In step 111, when the start point information obtained in the start point information extraction step 109 is a flip-flop, inverting means and control means are inserted into the netlist for the flip-flop.
A means for holding the initial value information extracted in step (1) is inserted. In step 112, the layout according to the netlist changed in step 111 is executed.

In step 113, an initial value information pattern is generated based on the initial value information for the netlist changed in step 111. If the information obtained in the starting point information extracting step 109 is a flip-flop, a control signal pattern for inverting the input flip-flop is generated through the control means, and the starting point information extracting step 1 is performed.
If the information obtained in step 09 is an external input signal, a pattern for inverting the signal is generated.

In the test pattern synthesizing step 114,
The path test pattern generated in step 113 for each path is synthesized so as to be given through a scan path, and an LSI control signal pattern for delay fault detection is added to generate a delay fault detection pattern 115.

FIG. 2 is a circuit diagram showing a specific example of the circuit to be detected that has been scanned and inserted in step 102 described above.
FIG. 3 shows an example in which a circuit for realizing inversion means and control means based on the delay fault detection method of the present invention is inserted in the detected circuit of FIG. An operation example of the delay fault detection based on the present invention will be described with reference to these two figures.

In FIG. 2, a clock signal 206 is input to clock input terminals CK of flip-flops 201 to 205 with scan, and a scan shift control signal 207 is input to scan shift control terminal SC. Flip-flops with scans 201 to 205
Selects data from the scan input terminal DT when the scan shift control signal is “H” (high level),
In the case of L "(low level), the data from the normal signal input terminal D is selected.

The signal input 208 is connected to the normal signal input terminal D of the flip-flop with scan 201, and the scan input 209 is connected to the scan input terminal DT of the flip-flop with scan 201. The output signal terminal Q of the flip-flop 201 with scan is the net 21
0, it is connected to one input terminal of the NAND gate 218 and the scan input terminal DT of the flip-flop 202 with scan.

The normal signal input terminal D of the flip-flop with scan 202 is connected to the signal input 211, and the output terminal Q is connected via the net 212 to the other input terminal of the NAND gate 218 and the scan input terminal DT of the flip-flop with scan 203. It is connected to the. The normal signal input terminal D of the flip-flop with scan 203 is connected to the signal input 213, and the output terminal Q is connected via the net 214 to one input terminal of the NAND gate 219 and the scan input terminal DT of the flip-flop with scan 204. ing. The normal signal input terminal D of the flip-flop with scan 204 is connected to the signal input 215, and the output terminal Q is connected via the net 216 to the other input of the NAND gate 219 and the scan input terminal DT of the flip-flop with scan 205. I have.

The output of NAND gate 218 is
The output of the NAND gate 219 is connected to one input of the NOR gate 222 via a net 221.
The output of the NOR gate 222 is supplied via a net 223 to the normal signal input terminal D of the flip-flop 205 with a scan.
It is connected to the. Flip-flop with scan 20
5 is connected to the signal output 217. With the circuit as described above, the scan input 209 and the net 2
Signal output 21 via 10, 212, 214, 216
7 is configured.

When the steps from the layout step 103 to the detected path selection step 108 in FIG. 1 are executed on the detected circuit, the path having the least allowance is changed from “H” of the output of the flip-flop with scan 204 to “H”.
The change to L ″ is caused by the net 216 and the NAND gate 21.
9, net 221, NOR gate 222, net 223
, A path to be transmitted to the normal signal input terminal D of the flip-flop with scan 205 is selected.

At this time, starting point information extraction step 1 in FIG.
At 09, the flip-flop with scan 204 is extracted as the starting point to be inverted. Further, in the initial value information extraction step 110, the NOR gate 2 is controlled so that the change from “H” to “L” of the output of the flip-flop with scan 204 propagates to the end point of the selected path.
22 is set to “L”, that is, the output of the NAND gate 218 is set to “L”. Therefore, both the outputs of the flip-flops with scan 201 and 202 are set to “H”. Further, the output of the flip-flop with scan 203 is set to “H” so that the output of the NAND gate 219 changes with the value of the net 216. Such initial information is extracted.

Next, in the inversion means and control means insertion step 111, the inversion means and the control means are added to the flip-flop with scan 204 which is the starting point. Also,
In order to hold the initial value, holding means is added to the flip-flops with scans 201 to 203. FIG. 3 shows a circuit based on the netlist generated as a result.

In FIG. 3, portions which are not changed from the circuit of FIG. 2 are denoted by the same reference numerals as in FIG. Since the flip-flop with scan 204 in FIG. 2 is the starting point, it is replaced with the flip-flop with inversion means 301 in FIG. Flip-flop 301 with inversion means
Has a net 302 connected to the inversion control input terminal RV,
The output is inverted when the value of the net 302 is “H” and the scan shift control signal 207 is “L”.

Similarly, the flip-flops 201-203 with scan in FIG. 2 are replaced by flip-flops 303-305 with holding means in FIG. 3, respectively, and the net 302 is connected to their holding control signal terminals HLD. Flip-flops with holding means 303 to 305
Is held when the net 302 is “H” and the scan shift control signal 207 is “L”. The flip-flop with scan 306 is control means for controlling the inverting means and the initial value holding means, and its output terminal Q is connected to the net 302.

The flip-flop with scan 30
6, the clock signal 206 is connected to the clock terminal CK, the scan shift control signal 207 is connected to the scan control terminal SC, and the signal output 217 is connected to the scan input terminal DT.
Is connected to the ground and incorporated in the scan path.

The changed netlist is laid out again in the relayout step 112 of FIG. 1 and a test pattern is generated in the path test pattern generation step 113.

FIG. 4 shows an example of a pattern when a delay fault is detected by the circuit of FIG. In FIG. 4, clock signal 2
In the first cycle of 06, the scan shift control signal 207 and the scan input 209 are set to “H”. As a result, the following 2
At the cycle, the value of the net 210 becomes “H”. 2 more
When the scan shift control signal 207 and the scan input 209 are set to “H” also in the cycle, the values of the nets 210 and 212 become “H” in the next third cycle. Then, in the third cycle, the scan shift control signal 207 and the scan input 2
09 to “H”, the net 21 in the next fourth cycle
The values of 0, 212 and 214 are "H". Also in the fourth cycle, the scan shift control signal 207 and the scan input 209
Is set to “H”, the net 210,
The values of 212, 214, and 216 become "H". Furthermore, 5
When the scan shift control signal 207 and the scan input 209 are also set to “H” in the cycle, the nets 210, 212, 214, 216 and the signal output 217 in the next sixth cycle.
Becomes "H", and the initialization of the detected path is completed.
Since the control signal is supplied to the flip-flop with scan 306 which is the control means, if the scan shift control signal 207 and the scan input 209 are set to “H” in the sixth cycle, the net is held in the initial state in the seventh cycle. 302 becomes “H”.

In order to detect a delay fault, the scan shift control signal 207 and the scan input 20
9 is set to “L”. Thus, at the rising edge of the next eighth cycle of the clock signal 206, the output of the flip-flop 301 with the inversion means is inverted, and the state of the net 216 is inverted to "L". At this time, the flip-flops 303 to 305 with holding means are connected to the net 3
Since 02 is “H”, the “H” state of the output is held. The final output of the detected path reaches the normal signal input terminal D of the flip-flop with scan 205 through the net 223, is taken in at the rising edge of the next ninth cycle of the clock signal 206, and is output as the signal output 217. If the value is "L", it is understood that there is no delay fault, and if "H", it is understood that a delay fault has occurred. That is, by setting the time difference between the rising edge of the eighth cycle and the rising edge of the ninth cycle of the clock signal 206 to the target delay time, whether a delay fault exceeding the target delay time occurs in the detected path. Can be determined.

The flip-flop 30 with inversion means shown in FIG.
FIG. 5 shows a specific example of a circuit for realizing No. 1. In FIG. 5, the clock terminal CK of the flip-flop 400 is connected to the clock input 401, the output terminal Q is connected to the signal output 402, and the input terminal D is connected to the output of the selector 403. When the scan shift control signal input 406 is “H”, the selector 403 selects and outputs the scan shift input 404, and when the scan shift control signal input 406 is “H”,
In the case of L ", the value of the net 405 is selected and output. The net 405 is connected to the output of the selector 407.
The selector 407 selects and outputs the value of the signal input 408 when the inverted control signal input 410 is “L”, and selects and outputs the value of the net 409 when the inverted control signal input 410 is “H”. The net 409 is connected to the output of the inverter 411, and the input of the inverter 411 is the signal output 402.
It is connected to the.

With the above arrangement, when the scan shift control signal input 406 is "H", the scan shift input 40
The value of 4 is taken into the flip-flop 400 at the rise of the clock input 401, the scan shift control signal input 406 is "L", and the inversion control signal input 41
When “0” is “L”, the value of the signal input 408 is taken into the flip-flop 400 at the rising edge of the clock input 401. Also, a scan shift control signal input 406
Is “L” and the inversion control signal input 410 is “L”.
In the case of “H”, the inverted value of the signal output 402 is taken into the flip-flop 400 at the rise of the clock input 401. In this way, a desired flip-flop with inverting means is realized.

The flip-flop 30 with holding means of FIG.
FIG. 6 shows an example of a circuit that realizes steps 3 to 305. 6, the clock terminal CK of the flip-flop 500 is connected to the clock input 501, the output terminal Q is connected to the signal output 502, and the input terminal D is connected to the output of the selector 503. The selector 503 selects and outputs the value of the scan shift input 504 when the scan shift control signal input 506 is “H”, and outputs the selected value.
Is "L", the value of the net 505 is selected and output.

The net 505 is connected to the output of the selector 507. The selector 507 receives the hold control signal input 51
When 0 is “L”, the value of the signal input 508 is selected and output, and when the hold control signal input 510 is “H”,
09 is selected and output. Net 509 is connected to signal output 502.

With the above configuration, when the scan shift control signal input 506 is "H", the scan shift input 50
4 is taken into the flip-flop 500 at the rise of the clock input 501, the scan shift control signal input 506 is "L", and the hold control signal input 51
When “0” is “L”, the value of the signal input 508 is taken into the flip-flop 500 at the rise of the clock input 501. Also, a scan shift control signal input 506
Is “L” and the holding control signal input 510 is “L”.
H ”, the value of the signal output 502 is the clock input 5
At the rise of 01, it is taken into the flip-flop 500. Thus, a desired flip-flop with holding means is realized.

The flip-flop 30 with inversion means shown in FIG.
1 is shown in FIG. 7, the clock terminal CK of the flip-flop 600 is connected to the clock input 601, the output terminal Q is connected to the signal output 602, and the input terminal D
Are connected to the output of the selector 603, respectively.
The selector 603 selects and outputs the value of the scan shift input 608 when the output of the OR gate 612 is “L”, and selects and outputs the value of the net 605 when it is “H”. The net 605 is connected to the output of the selector 607. The selector 607 sets the inversion control signal input 610 to “
When L is "L", the value of the signal input 604 is selected and output, and when the inversion control signal input 610 is "H", the value of the net 609 is selected and output.
1 and the input of the inverter 611 is connected to the signal output 602. The inversion control signal 610 and the scan shift control signal input 606 are input to the OR gate 612.

With the above configuration, the scan shift control signal input 606 is "L" and the inversion control signal 61
When 0 is “L”, the output of the OR gate 612 becomes “L”.
L ”, and the value of the signal input 608 becomes the clock input 601.
At the rising edge of the flip-flop 600. When the scan shift control signal input 606 is “H” and the inversion control signal input 610 is “L”, the value of the scan shift input 604 is taken into the flip-flop 600 at the rise of the clock input 601. When the scan shift control signal input 606 is “L” and the inversion control signal input 610 is “H”, the inverted value of the signal output 602 is taken into the flip-flop 600 at the rise of the clock input 601. Thus, a desired flip-flop with inversion means is realized.

FIG. 8 shows an example of a circuit for realizing the inverting means and the initial value holding means in the delay fault detecting method according to the present invention. 8, the clock terminal CK of the flip-flop 700 is connected to the clock input 701, the output terminal Q is connected to the signal output 702, and the input terminal D is connected to the output of the selector 703. The selector 703 selects and outputs the value of the signal input 704 when the scan shift control signal input 706 is “L”, and selects and outputs the value of the net 705 when it is “H”.

The net 705 is connected to the output of the selector 707. The selector 707 has an inversion control signal input 71.
When 0 is “L”, the value of the scan shift input 708 is output, and when the inversion control signal input 710 is “H”, the output value of the inverter 709 is output. Inverter 7
The scan shift input 708 is connected to the input of 09.

With the above configuration, when the scan shift control signal input 706 is "L", the value of the signal input 704 is taken into the flip-flop 700 at the rising edge of the clock input 701. Scan shift control signal input 7
06 is “H” and the inversion control signal input 710
Is "L", the value of the scan shift input 708 rises at the rising edge of the clock input 701.
00 is taken in. Scan shift control signal input 70
6 is “H”, and the inversion control signal input 710 is “H”.
H ”, the inverted value of the scan shift input 708 becomes the flip-flop 7 at the rising edge of the clock input 701.
00 is taken in.

At this time, since the value of the scan shift input 708 is the output of the preceding flip-flop on the scan path or the external input, the value of the scan shift control signal
The value is known before inputting 6 or the inversion control signal 710. In other words, in the delayed fault detection path, the flip-flop input to the path is replaced with the circuit having the configuration shown in FIG. 8, and the inversion necessary for detecting the fault and holding of the initial value are performed by the scan shift control signal input 706 and This can be realized in combination with the inversion control signal 710.

FIG. 8 shows the delay fault detection circuit of FIG.
FIG. 9 shows an example using the inversion means and the initial value holding means. 9, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals.

The flip-flop with scan 20 shown in FIG.
9 are replaced by flip-flops 803, 804, 805, and 801 with holding / inversion means in FIG. Flip-flop 80 with holding / inverting means
The inversion control input terminals RV of 3 to 805 are connected to the net 809. Flip-flop with holding / inversion means 8
The inversion control input terminal RV of 01 is connected to the net 812. Also, a flip-flop 8 with holding / inversion means
01, scan shift control terminals SC of 803 to 805
Is connected to the net 807.

With the above configuration, the flip-flop 801 with holding / inverting means takes in the signal input 215 when the value of the net 807 is "L". When the value of the net 807 is “H”, if the value of the net 812 is “L”, the value of the net 214 is fetched.
The inverted value of 14 is fetched. When the state of the net 807 is “L”, the flip-flops 803 to 805 with holding / inverting means have respective signal inputs 208 and 2.
11 or 213, and if the state of the net 807 is “H” and the value of the net 809 is “L”, the value of the net 210, 212 or 214 is fetched and the value of the net 807 is read. If the state is “H” and the value of the net 809 is “H”, the net 210,
The inverted value of 212 or 214 is fetched.

The output terminal Q of the flip-flop with scan 306 is connected to the net 802, and the net 802 is connected to the N
One input terminal of OR gate 808, inverter 810
And one input terminal of the OR gate 806. The other input terminal of the NOR gate 808 and the other input terminal of the OR gate 806 are connected to the scan shift control signal 207. Inverter 810
Is connected to one input terminal of a NOR gate 811, and the other input terminal of the NOR gate 811 is also connected to the scan shift control signal 207. OR gate 80
6 is connected to net 807, the output of NOR gate 808 is connected to net 809, and the output of NOR gate 811 is connected to net 812.

With the above configuration, the values taken in the flip-flops 801 and 803 to 805 with holding / inversion means are controlled by the scan shift control signal 207 and the output value of the flip-flop with scanning 306 as the control means. be able to.

FIG. 10 shows an example of a pattern when a delay fault is detected by the circuit of FIG. In FIG. 10, the scan shift control signal 20
7 and the scan input 209 are set to “H”. As a result, the value of the net 807 is “H”, and the nets 809 and 812
Becomes "L", the scan shift path is activated, and the state is in the non-inverted state, so that the value of the net 210 becomes "H" in the next second cycle. In the second cycle, the scan shift control signal 207 and the scan input 209 are changed to "
H ", the nets 210 and 21 in the next third cycle
The value of 2 becomes "H". Subsequently, when the scan shift control signal 207 and the scan input 209 are set to “H” in the third cycle, the nets 210, 212, and 2 are set in the next fourth cycle.
The value of 14 becomes "H". If the scan shift control signal 207 and the scan input 209 are also set to “H” in the fourth cycle, the nets 210, 212, and 21 are set in the next fifth cycle.
The values of 4, 216 become “H”.

Further, when the scan shift control signal 207 and the scan input 209 are set to “H” in the fifth cycle, the nets 210, 212, 214, 21 in the next sixth cycle are set.
6 and the value of the signal output 217 become "H", and the initialization of the detected path is completed. Further, in order to supply a control signal to the flip-flop with scan 306 which is a control means,
When the scan shift control signal 207 and the scan input 209 are set to “H” in the sixth cycle, the net 802 is set to “H” in the seventh cycle while maintaining the initial state.

In order to detect a delay fault, the scan shift control signal 207 and the scan input 20
9 is set to “L”. When the net 802 is “H” and the scan shift control signal 207 is “L”,
Since the two inputs of the NOR gate 808 are “H” and “L”, the value of the net 809 of the NOR gate 808 is “
Since the two inputs of the NOR gate 811 are both "L", the value of the net 812 is "H".

As a result, the next 8 of the clock signal 206
On the rising edge of the cycle,
Flip-flop 8 with holding / inversion means holding inverted value of H "
01, and the state of the net 216 is inverted. "
At this time, since the flip-flops 803 to 805 with holding / inverting means are in the case where the net 807 is “H” and the net 809 is “L”, the output “H” state is changed. The final output of the detected path is supplied to the flip-flop with scan 20 through the net 223.
5 arrives at the normal signal input terminal D, and the clock signal 206
At the rising edge of the next 9th cycle,
The signal is output as a signal output 217. If the value is "L", it is understood that there is no delay fault, and if "H", it is understood that a delay fault has occurred. That is, by setting the time difference between the rising edge of the eighth cycle and the rising edge of the ninth cycle of the clock signal 206 to the target delay time, it is determined whether or not a delay fault exceeding the target delay time has occurred in the detected path. Can be determined.

For the sake of simplicity, the present embodiment is an example in which the present invention is applied to a part of an integrated circuit. The detection can be performed in parallel by adding an initial value holding unit and a control unit.

[0052]

As described above, according to the present invention, based on the result of the static delay simulation, the path for detecting the fault to be delayed is selected, and the initial value information of the path and the starting point information to be inverted are extracted. Next, an initial state is given using a scan path used for logical fault detection, and true state is provided by adding inversion means to a flip-flop that generates a state change, that is, signal inversion, in order to detect a delay fault. Of the critical path can be determined in parallel in each part of the LSI. Further, in the present invention, a path in which a delay fault is likely to occur is extracted by a static delay simulation, and the inspection is intensively performed, thereby suppressing an increase in a circuit scale and a test pattern.

According to the delay fault detecting method of the present invention,
The true critical path can be determined using the actual wiring capacitance obtained from the layout. Furthermore, it is possible to suppress the increase in the circuit scale and the test pattern by creating a list of the time margin from the result of the static delay simulation and selecting a path with a small margin as the detected path.

Also, by providing a control signal for controlling the inverting means by scan shift, it is possible to control the state inversion of any flip-flop in parallel. Further, it is possible to minimize the configuration of the inversion means and suppress an increase in the circuit scale. Further, the reversing means and the initial value holding means of the present invention only perform processing on the scan path, and can prevent the occurrence of delays and the like given to the normal path.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a delay fault detection method according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit including a delayed fault detection path.

FIG. 3 is a diagram showing a circuit obtained by adding means for detecting a delay fault to the circuit of FIG. 2;

FIG. 4 is a view showing a test pattern for the circuit of FIG. 3;

FIG. 5 is a diagram illustrating an example of an inversion control unit;

FIG. 6 is a diagram showing an example of an initial value holding unit.

FIG. 7 is a diagram illustrating an example of an inversion control unit;

FIG. 8 is a diagram illustrating an example of a holding / inverting unit;

FIG. 9 is a diagram showing a circuit to which a means for detecting a delay fault in the case of using a holding / inverting means is added.

FIG. 10 is a diagram showing a test pattern for the circuit of FIG. 9;

[Explanation of symbols]

101 Netlist 102 Scanning step 103 Layout step 104 Actual wiring capacity extraction step 105 Static real wiring capacity simulation step 106 Margin list generation step 107 Threshold 108 Detection path selection step 109 Start point information extraction step 110 Initial value information extraction Step 111 Inverting means and control means inserting step 112 Relayout step 113 Path test pattern generating step 114 Test pattern synthesizing step 115 Delay fault detecting pattern 201 to 205 Scanned flip-flop 206 Clock signal 207 Scan shift control signal 301 Flip with inverted means 303 to 305 flip-flop with holding means 306 flip-flop with scan 400 flip-flop Rop 403,407 selector 411 inverter 500 flip-flop 503,507 selector 600 flip-flop 603,607 selector 611 inverter 612 OR gate 700 flip-flop 703,707 selector 709 inverter 801,803,804,805 flip-flop with holding / inverting means 806 OR gate 807 Inverter

Claims (7)

[Claims] 1. A first step of generating a netlist in which flip-flops are scanned, and a second step of performing a static delay simulation on the netlist and extracting a path that easily causes a delay fault
A step of extracting information of a flip-flop or an external input signal serving as a starting point of the path and initial value information of the path when the path is likely to cause a delay fault; and a flip-flop serving as the starting point. A fourth step of inserting an inverting means for inverting the state of the loop and its control means, and an initial value holding means, based on the external input signal information and the initial value information,
Providing a signal for controlling the control means after setting the initial value through a scan path, and causing a state change of the detected path to perform a delay fault detection. Method. 2. The method according to claim 1, wherein in the second step, a static real wiring delay simulation is performed based on a result of the layout based on the netlist. 3. When selecting a route in which the delay fault is likely to occur, a list of a margin of operation time is generated, and a route in which the margin is less than a set value is selected as a route in which a delay fault is likely to occur. 3. The method for detecting a delay fault in an integrated circuit according to claim 1. 4. The method according to claim 1, wherein the control unit is scanned and a control signal is supplied through a scan path. 5. The delay fault of an integrated circuit according to claim 1, wherein the inverting means is configured to select an inverted signal of an output signal of the scanning flip-flop or a non-scan input signal according to a selection signal. Detection method. 6. The delay fault detection of an integrated circuit according to claim 1, wherein said inverting means is configured to select an inverted signal of an output signal of a scanning flip-flop or a scan input signal according to a selection signal. Method. 7. The inverting means and the initial value holding means are configured to select an output signal of a preceding scanning flip-flop on a scan path or an inverted signal thereof according to a selection signal. The method for detecting a delay fault of an integrated circuit according to the above.