JP6534592B2 - Scan test circuit and scan test apparatus - Google Patents

Description

  The present invention relates to a scan test circuit and a scan test apparatus that can be used for LSI testing.

  Conventionally, in the design stage of Design for Test (DFT), ATPG (Automatic Test Pattern Generation), which is an internally manufactured tool, is used as a scan test circuit configuration. In this ATPG, the reset operation of the asynchronous reset is suppressed (excluded) by the test circuit.

  As described above, in the scan test mode, the scan shift operation and the capture by the system operation also target only the data path between the FF registers as a failure detection target by suppressing the asynchronous reset operation of the FF (flip flop) register. In the above, ATPG pattern generation was performed to calculate the failure detection rate.

  Since further improvement, the ATPG of EDA vendor is configured to be able to detect the asynchronous reset operation of the register by adding the test terminal of the external operation.

  In this configuration, the ATPG pattern generation algorithm can perform asynchronous reset after setting ALL 1 in addition to setting ALL 0 and ALL 1 for all registers in order to verify the shift operation of the scan shift register. There is. With this configuration, it is possible to confirm the operation of the FF register alone, and thereafter set various data in the scan shift register and verify the combinational circuit between the registers and verify the delay value in the capture operation of the system operation. It has become.

  However, if the asynchronous reset path is released in the system operation after the shift operation in order to set the asynchronous reset path as a target of failure detection, the setting that is set by the shift operation is passed through the asynchronous reset path of the FF register. To clear the data one after another. In addition, there is a possibility that the reset condition set in the shift operation may be canceled by other register settings, which may cause a hazard.

  This is considered to be a failure in pattern generation of the ATPG tool, which is the reason why failure detection of the asynchronous reset path can not be 100%. That is, in the test circuit, the path of the asynchronous reset is excluded from the register output, and it can not be said that testing is performed efficiently.

  The flip-flops of the output signal of the logic circuit not to be tested are reset or set, and the input signal of the logic circuit to be tested is fixed to logically input the signal of the logic circuit to be tested. Patent Document 1 discloses a scan test circuit designed to avoid circuit design to be fixed.

  Also, signals from a control terminal for inputting control signals for controlling the mode switching of scan path test and normal operation, and a set terminal for setting and resetting the state of the flip flop are respectively inputted, and the control signals are for scan path mode. When it is shown, the scan path circuit includes a logic circuit that inhibits transmission of the set signal input to the set terminal and controls the state of the flip flop not to be set by the input set signal. It is shown in Patent Document 2.

  Furthermore, to the first flip-flop on each scan chain, a flip-flop with an asynchronous set reset for setting data to each flip-flop on each connected scan chain is connected, and the flip-flop with asynchronous set reset is connected Patent Document 3 discloses a scan test circuit configured to control an asynchronous set / reset terminal of a clock by a control circuit.

Japanese Patent Application Laid-Open No. 10-111345 JP 2003-43108 A JP, 2005-331480, A

  However, none of the above-described conventional techniques are concerned with measures that can prevent the data reset by successively clearing the setting set in the shift operation through the asynchronous reset path of the FF register, and the asynchronous reset It has not been configured to properly detect the failure of the route.

  The present invention has been made in view of the current state of the scan test circuit as described above, and its object is to penetrate the asynchronous reset path of the FF register and successively clear the setting set in the shift operation to successively carry out the data. It is an object of the present invention to provide a scan test circuit that does not break down. Another object of the present invention is to provide a scan test circuit having a configuration that can properly detect a fault in an asynchronous reset path.

A scan test circuit according to the present invention has a multiplexer for selecting either a normal input or a scan input, a flip-flop that receives an output of the multiplexer and can be set / reset by a reset signal, and a latch enable terminal. When the latch enable signal is applied to the latch enable terminal at an active level, the signal from the output terminal of the flip flop is latched, and when the latch enable signal is at an inactive level, the signal from the output terminal of the flip flop is An LD latch circuit for passing a signal, wherein the LD latch circuit to which the reset signal is not applied is provided, and in the case of resetting the flip flop, the LD connected to the flip flop prior to the reset Said latch of the latch circuit Giving a latch enable signal as an active level to enable terminal, wherein the signal from the output terminal of the flip-flop is latchable.

  In the scan test circuit according to the present invention, the flip flop is a flip flop with a reset terminal.

  In the scan test circuit according to the present invention, the flip flop is a flip flop with a set terminal.

  In the scan test circuit according to the present invention, a logical OR operation of a reset signal and a switching control signal of the multiplexer is performed, and an OR gate for sending an output to the reset terminal, a logical product of the reset signal and an output signal of the multiplexer. And an AND gate which performs an operation and sends an output to an input terminal of the flip flop.

  The scan test circuit according to the present invention is characterized in that the output of the Q terminal of the LD latch circuit is an output of the scan test circuit.

  A scan test apparatus according to the present invention comprises a plurality of scan test circuits according to any one of claims 1 to 5, and the output of the Q terminal of the LD latch circuit in the scan test circuit in the previous stage is It is characterized in that it is configured to send to the scan input of the multiplexer.

  According to the present invention, it is possible to prevent the destruction of data by successively clearing the setting set by the shift operation. In addition, failure detection of the asynchronous reset path can be properly performed.

1 is a configuration diagram of a scan test circuit according to a first embodiment of the present invention. The block diagram of the scan test apparatus comprised using multiple scan test circuits which concern on the 1st Embodiment of this invention FIG. 2 is a configuration diagram of a scan test circuit in which the LD latch circuit is removed from the scan test circuit according to the first embodiment of the present invention. FIG. 5 is a configuration diagram of a scan test circuit according to a second embodiment of the present invention. FIG. 6 is a configuration diagram of a scan test circuit in which an LD latch circuit is removed from a scan test circuit according to a second embodiment of the present invention. 5 is a timing chart when asynchronous reset is performed using the scan test circuit according to the first embodiment of the present invention. FIG. 7 is a configuration diagram of a scan test circuit according to a third embodiment of the present invention. The timing chart at the time of performing an asynchronous reset using the scan test circuit which concerns on the 3rd Embodiment of this invention.

  Hereinafter, embodiments of a scan test circuit and a scan test apparatus according to the present invention will be described with reference to the attached drawings. In each of the drawings, the same components are denoted by the same reference numerals and redundant description will be omitted.

  FIG. 1 shows a configuration diagram of a scan test circuit 100 according to the first embodiment. The scan test circuit 100 includes a multiplexer 10, a flip flop 20 and an LD latch circuit 30. Multiplexer 10 has an input terminal A0 for receiving normal input signal D and an input terminal A1 for receiving scan-in input signal TI, and a scan test enable signal TE applied to control input terminal S causes a normal input signal D and a scan-in input signal Select one of TI and output from output terminal Z.

  The flip flop 20 is a flip flop that can be reset by a reset signal CD applied to a reset terminal CD. The data input terminal D of the flip flop 20 and the output terminal Z of the multiplexer 10 are connected. The output signal of the output signal of the multiplexer 10 is taken in synchronization with the clock signal CK arriving at the clock terminal CP of the flip flop 20.

  The output terminal Q of the flip flop 20 is connected to the data input terminal D of the LD latch circuit 30. The LD latch circuit 30 is a latch circuit of a transparent type or the like, has a latch enable terminal GN, and the output of the flip flop 20 when a latch enable signal TG (H level) is applied to the latch enable terminal GN. The signal from the terminal Q is latched, and the signal from the output terminal Q of the flip flop 20 is passed when the latch enable signal TG is at L level. The output signal Q of the output terminal Q of the LD latch circuit 30 and the output signal QN of the output terminal QN of a signal obtained by logically inverting the output signal Q are output signals of the scan test circuit 100.

  In order to perform the scan test of the combinational circuit 200 as shown in FIG. 2, a plurality of scan test circuits 100 of the above configuration are used, and the scan test apparatus 1 is configured by configuring a shift register in which these are cascaded as shown in FIG. obtain. That is, the output of the Q terminal of the LD latch circuit 30 in the scan test circuit 100 at the front stage is connected to be sent to the scan-in input of the multiplexer 10 in the scan test circuit 100 at the rear stage.

  The output of the combinational circuit 200 is received by the input terminal A0 of the multiplexer 10 of each scan test circuit 100. In the scan test circuit 100 configured as described above, the scan test enable signal TE is set to the H level to set the scan test pattern from the scan in input signal TI to the flip flop 20 using the scan in input signal TI.

  The scan test pattern is input from the scan test circuit 100-1 of the first stage, shifted by applying the clock signal CK to the clock terminal CP of the flip flop 20, and the flip flops of the scan test circuits 100-1 to 100-n. Set the scan test pattern to 20.

  Next, capture. That is, the scan test enable signal TE is set to L level to set the system mode (normal mode), and the output of the combination circuit 200 is received by the flip-flops 20 of the scan test circuits 100-1 to 100-n by the clock signal CK.

  Next, the scan test enable signal TE is set to the H level to enter the scan mode, the clock signal CK is applied to the clock terminal CP of the flip flop 20 for shifting, and the result is scanned out from the output terminal of the scan test circuit 100-n. , And expected value (pattern without failure).

  For example, when resetting the required flip flops 20 of the scan test circuits 100-1 to 100-n when setting the above-mentioned scan test pattern, the LD latch circuit connected to the flip flops 20 before that is reset The latch enable signal TG is applied as an H level to the latch enable terminal GN of 30 and the signal from the output terminal Q of the flip flop 20 is latched.

  Although the required flip flop 20 is reset even if the required flip flop 20 is reset after the above latch is performed, in the scan test circuit 100, the scan test pattern set before the reset is the LD latch circuit 30. And can prevent the situation of clearing the scan test pattern. In addition, even if the required flip-flop 20 is reset by the latch by the LD latch circuit 30, the reset can not be transmitted to the next stage, which can be a countermeasure against the hazard of the internal reset signal generation. This makes it possible to avoid the difficulty of user pattern generation and to improve the efficiency of test verification.

  The above-described effect is obtained in the scan test circuit 90 shown in FIG. 3 in which the LD latch circuit 30 is removed from the scan test circuit 100 of this embodiment, the output signal of the scan test circuit 90 when the flip flop 20 is reset. Since Q is an output signal that has been reset and the reset is transmitted to the next stage, it is clear from the comparison with a circuit that may cause a hazard of internal reset signal generation.

  FIG. 4 shows the configuration of a scan test circuit 100A according to the second embodiment. The scan test circuit 100A uses a flip flop 40 with a set terminal in place of the flip flop 20 of the scan test circuit 100 according to the first embodiment. The flip flop 40 has a set terminal SD, and is a flip flop that can be set by a reset signal SD applied to the set terminal SD.

  The scan test circuit 100A according to the second embodiment has the same configuration as the scan test circuit 100 according to the first embodiment except for the above configuration. A plurality of scan test circuits 100A according to the second embodiment can be used to obtain a scan test apparatus as in FIG.

  Also in this scan test apparatus, for example, when setting the required flip flops 40 of the plurality of scan test circuits 100A at the time of setting the scan test pattern, the LD latch connected to the flip flops 40 before that. A latch enable signal TG is applied to the latch enable terminal GN of the circuit 30 to latch the signal from the output terminal Q of the flip flop 40.

  Although the required flip flop 40 is set even after the above latch is performed, the required flip flop 40 is set, but the scan test pattern set before the setting in the scan test circuit 100A is the LD latch circuit 30. And can prevent the situation of clearing the scan test pattern. Moreover, even if the required flip-flop 40 is set by the latch by the LD latch circuit 30, the set can not be transmitted to the next stage, and it is possible to take measures against the hazard of the internal set signal generation. This makes it possible to avoid the difficulty of user pattern generation and to improve the efficiency of test verification.

  The above-described effect is obtained in the scan test circuit 110 shown in FIG. 5 in which the LD latch circuit 30 is removed from the scan test circuit 100A of the second embodiment, when the flip flop 40 is set. It is clear from the comparison with the circuit that the output signal Q of is output to the set signal and the set is transmitted to the next stage, which may cause a hazard of the internal reset signal generation.

  By the way, the ATPG tool reads circuit information corresponding to design for testability (DFT), and calculates a scan-in data pattern and an expected value of scan-out after capture. When calculating the expected value using the scan test circuit according to the first embodiment of FIG. 1, when the waveform of each part is as shown in FIG. 6, it is possible to set the priority of asynchronous reset in the calculation of ATPG. It is expected to be difficult. In such a case, the ATPG tool is executed by replacing the circuit shown in FIG. 1 with a scan test circuit as shown in FIG.

  A scan test circuit 100B according to the third embodiment shown in FIG. 7 includes an OR gate 61 and an AND gate 62 with respect to the scan test circuit 100 according to the first embodiment. The OR gate 61 is configured to perform an OR operation of the reset signal and the switching control signal of the multiplexer 10 and to send an output to the reset terminal. The AND gate 62 is configured to perform an AND operation of the reset signal and the output signal of the multiplexer, and to send an output to the input terminal of the flip flop.

  In the scan test circuit 100B according to the third embodiment configured as described above, before resetting the flip flop 20, the latch enable terminal GN of the LD latch circuit 30 connected to the flip flop 20 is reset. The latch enable signal TG is applied to latch the signal from the output terminal Q of the flip flop 20.

  In synchronization with the latch enable signal TG, the scan test enable signal TE is set to the L level to make the system mode (normal mode), and the clock signal CK for the capture operation is sent (see FIG. 8).

  After the above latch is performed, the reset signal CD is enabled. As a result, when the L level signal is applied from the OR gate 61 to the reset terminal CD and the L level signal from the AND gate 62 is applied to the data input terminal D of the flip flop 20, the capture operation is performed. The clock signal CK arrives. That is, the output of the AND gate 62 is controlled by the reset signal CD, the output of the AND gate 62 is given to the input terminal D of the flip flop, and it is assumed that synchronous reset processing is performed. be able to. This makes it possible to set the reset priority in the ATPG calculation.

  The reset control of the entire circuit in the scan test mode and the reset control of the path of the asynchronous reset in each of the above embodiments will be described. Reset control of the entire circuit in the scan test mode is performed by the same configuration control as that of the conventional example. In addition, a configuration can be adopted in which a test terminal for reset control of the asynchronous reset path is newly added to perform reset control of the asynchronous reset path. Alternatively, a test terminal for reset control of the entire conventional circuit may be diverted, and the entire reset control may be integrated to perform reset control of the path of asynchronous reset. Furthermore, a configuration may be adopted in which reset control is separated, and reset control of the entire circuit is performed during scan shift, and reset control of an asynchronous reset path is performed in the system mode (at the time of capture).

DESCRIPTION OF REFERENCE NUMERALS 10 multiplexer 20 flip flop 30 LD latch circuit 40 flip flop 61 OR gate 62 and gates 90, 100, 100 A, 100 B scan test circuit

Claims (6)

A multiplexer for selecting either normal input or scan input,
A flip-flop that receives the output of the multiplexer and can be set / reset by a reset signal ;
It has a latch enable terminal, and latches the signal from the output terminal of the flip flop when the latch enable signal is applied at the active level to the latch enable terminal, and the flip flop when the latch enable signal is at the inactive level. An LD latch circuit for passing a signal from the output terminal of the flash memory, wherein the reset signal is not given ,
Equipped with
Before resetting the flip-flop, a latch enable signal is applied as an active level to the latch enable terminal of the LD latch circuit connected to the flip-flop, and a signal from the output terminal of the flip-flop is output. scan test circuit, which is a latchable.   The scan test circuit according to claim 1, wherein the flip flop is a flip flop with a reset terminal.   The scan test circuit according to claim 1, wherein the flip flop is a flip flop with a set terminal. An OR gate that performs an OR operation of a reset signal and a switching control signal of the multiplexer and sends an output to the reset terminal;
3. The scan test circuit according to claim 2, further comprising: an AND gate that performs an AND operation of the reset signal and an output signal of the multiplexer and sending an output to an input terminal of the flip flop.   The scan test circuit according to any one of claims 1 to 4, wherein an output of a Q terminal of the LD latch circuit is an output of a scan test circuit. A plurality of scan test circuits according to any one of claims 1 to 5, comprising:
A scan test apparatus characterized in that the output of the Q terminal of the LD latch circuit in the scan test circuit of the former stage is sent to the scan input of the multiplexer in the scan test circuit of the latter stage.