JP2006337289A - Semiconductor integrated circuit device and its testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device realizing detection of delayed failures on a memory boundary, and to provide its test method. <P>SOLUTION: In this device, a test circuit including a scan chain, consisting of first, second, third, and fourth FFs for detecting a failure of a logic circuit and a memory circuit, to which memory access is performed by the circuit, is used. The first and third FFs fetch first and third test signals for the memory circuit by a scan-in operation, synchronize with an internal clock, transmit the first test signal to the third FF through a selector, and transmits the third test signal to the memory circuit. The fourth FF fetches the output signal of the memory circuit. The memory circuit has a test signal path for transmitting the same signal to the fourth FF, at write-in operation in the test mode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a test method thereof, and more particularly, to a semiconductor integrated circuit device having a memory circuit that is accessed by a logic circuit and detecting a delay failure between the logic circuit and the memory circuit. It relates to effective technology.

As an example of a semiconductor integrated circuit device having a scan chain for testing a logic circuit and a memory circuit in a system LSI mounted with an embedded memory, and an example of a design method thereof, Japanese Patent Application Laid-Open Nos. 2004-280926 and 2004-053341 are disclosed. There is. In the above Japanese Patent Application Laid-Open No. 2004-280926, a boundary scan circuit is added in the memory core to realize a memory scan test and a high-speed random cycle write operation. In Japanese Patent Application Laid-Open No. 2004-053341, a memory scan test can be performed while reducing an increase in area by forming a memory input latch as a scan register.
JP 2004-280926 A JP 2004-053341 A

  Prior to the present invention, as shown in FIG. 15, as a system LSI on which an embedded memory is mounted, it was considered to mount a memory BIST circuit that detects a delay failure of the embedded memory. By performing a test in which the memory BIST circuit is operated at an actual speed, it is possible to detect a delay fault in the operation of the memory and a delay fault between the embedded memory and the memory BIST circuit. In addition, in order to test the entire system LSI including the peripheral circuit (logic) of the embedded memory, a delay fault of the entire system LSI can be detected by performing an actual speed scan test. As shown in FIG. 16, the embedded memory in the scan test is handled as a black box, and an FF (flip-flop circuit) 07 is provided for observing the value input to the memory and controlling the output value of the memory. In other cases, as in Patent Document 1 and Patent Document 2, it is conceivable to scan using the FF in the memory in the same way as scanning of the system LSI.

  However, in the studied technique, the delay fault at the memory boundary cannot be detected. This is because, in the memory BIST, the memory BIST circuit performs writing and reading of the memory, so that the timing of the actual user operation, that is, the memory writing and reading from the logic 18 is different. In the scan test, even if there is FF07 for observing / controlling the input / output of the memory, the FF is arranged at a position away from the memory by automatic layout. For this reason, the transfer timing becomes gradual, and it is not an effective means in terms of detecting a delay fault at the memory boundary. Even when the inside of the memory is scanned as in Patent Document 1 and Patent Document 2, even if it is possible to detect a delay fault in the memory input, the delay fault in the memory output should be detected. I can't.

  An object of the present invention is to provide a semiconductor integrated circuit device that realizes detection of a delay fault at a memory boundary and a test method thereof. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A test circuit including a scan chain including a logic circuit and first, second, third, and fourth flip-flop circuits for detecting a failure of the memory circuit to which memory access is performed is provided. In the first test mode, the first test signal taken into the first flip-flop circuit in synchronization with an internal clock is passed through the first selector, and the third flip-flop circuit and the third flip-flop circuit take the first test signal. The 3 test signal is transmitted to the memory circuit as a memory access input signal in synchronization with the internal clock. In the second test mode, the second test signal taken into the second flip-flop circuit in synchronization with the internal clock is passed through the first selector to the third flip-flop circuit in synchronization with the internal clock. The signal held in the 3 flip-flop circuit is transmitted to the memory circuit as an input signal for memory access in synchronization with the internal clock. The fourth flip-flop circuit takes in an output signal from the memory circuit in synchronization with the internal clock in the first test mode and the second test mode. The memory circuit is a test signal for transmitting the same signal as the write signal formed by the third flip-flop circuit to the fourth flip-flop circuit during a write operation in synchronization with the internal clock in the first test mode. Provide a route.

  The outline of other representative ones of the inventions disclosed in the present application will be briefly described as follows. A test circuit including a scan chain including a logic circuit and first, second, third, and fourth flip-flop circuits for detecting a failure of the memory circuit to which memory access is performed is provided. The first and second flip-flop circuits receive the first and second test signals for the memory circuit during the scan-in operation in the first and second test modes, and synchronize with the internal clock. To the third flip-flop circuit. The third flip-flop circuit forms an input signal for accessing the memory circuit in synchronization with the internal clock, and the fourth flip-flop circuit passes the second selector through the second selector in the first test mode. The output signal of the flip-flop circuit is captured in synchronization with the internal clock, and the output signal of the memory cell array is captured in synchronization with the internal clock through the second selector in the second test mode.

  The outline of still another representative one of the inventions disclosed in the present application will be briefly described as follows. A test method for a semiconductor integrated circuit device comprising a logic circuit and a test circuit having a scan chain including first and second flip-flop circuits for detecting a failure of a memory circuit to which memory access is performed. The first test signal for the memory circuit is input to the first flip-flop circuit in synchronization with the external scan clock, the write and read operations of the memory circuit are performed in synchronization with the internal clock, and the output signal is output. A first test operation transmitted to the first or second flip-flop circuit is performed, scanned out, read, and compared with an expected value. The second test signal for the memory circuit is input to the second flip-flop circuit in synchronization with the scan clock, the write and read operations of the memory circuit are performed in synchronization with the internal clock, and the output signal is output. A second test operation transmitted to the first or second flip-flop circuit is performed, scanned out, read out, and compared with an expected value. A delay fault between the logic circuit and the memory circuit is detected by a combination of the first test mode and the second test mode.

  Delayed faults can be detected at memory boundaries.

  FIG. 1 is a block diagram showing the principal part of an embodiment of a semiconductor integrated circuit device (system LSI) according to the present invention. The system LSI of this embodiment includes a logic unit 18 and an embedded memory 17. The memory 17 is accessed by the logic unit 18. Both the logic unit 18 and the embedded memory 17 are scanned in order to perform a test operation. In other words, the logic unit 18 is connected in a tandem configuration when flip-flop circuits (hereinafter simply referred to as FFs) 01 and 04 provided between logic stages to perform a logic sequence synchronized with an internal clock are in a test mode. It is made to constitute a scan chain. The memory 17 is also separated from the logic unit 18 by the selector 05 and is directly accessed by the FFs 13 and 14 of the scan chain constituting the memory BIST (Built in Self Test) circuit 10.

  An FF 22 is also provided at the input section of the memory 17 and is also scan-chained. In this embodiment, the embedded memory 17 has a write-through mode 20. The in-memory FF 22 is provided corresponding to the memory input 02 and captures an input signal, and captures and holds an input signal for accessing the memory 17. When the write-through mode 20 is enabled, the same signal as the signal written in the memory cell array 19 with the output value of the in-memory FF 22 passes through the memory cell array 19 and is output from the memory output 03. In this write-through mode, for example, the write system circuit is put into an operating state for a write operation, and at the same time, the read system circuit is put into an operating state. For example, both the write amplifier and the sense amplifier are activated, and the signal written in the memory cell is amplified and output by the sense amplifier.

  In this embodiment, the signal path for detecting a delay fault at the memory boundary is indicated by a solid line in FIG. In this delay detection of a memory boundary, a test signal is scanned in (serial input) to each of the flip-flop circuits FF01, FF04, FF22 and the like in synchronization with a scan clock with a relatively low speed supplied from the outside. . The logic 18 and the memory 17 are tested in parallel output in synchronization with the internal clock at the actual speed. The signal output from the user FF01 is latched in the in-memory FF22. As a result, it becomes possible to detect a delay fault between the FF01 which is the output stage of the logic 18 and the FF22 which is the input of the memory 17. Further, the test signal scanned into the in-memory FF 22 is transmitted to the memory 17 as an input signal for memory access. During this test, the memory 17 is in the write-through mode 20 enabled, and the output (write signal) of the in-memory FF 22 passes through the memory cell array 19 and is latched by the user FF 04 through the memory output 03. As a result, it becomes possible to detect a delay fault with the FF04 which is the input stage of the logic unit 18 through the output of the memory 17 from the in-memory FF22.

  The memory test operation in the memory BIST circuit 10 is the same as the test of FIG. In FIG. 1, the test signal path in the memory BIST circuit 10 is indicated by a dotted line. That is, the first test signal is taken into the FF 13 of the memory BIST circuit 10 in synchronization with a scan clock supplied from the outside at a relatively low speed, and the test input signal is inputted through the selector 05 in synchronization with the internal clock. This is transmitted to the FF 22 in the memory. At this time, a dummy signal is input to the in-memory FF 22. Or nothing is entered. Therefore, the first test signal is a dummy cycle in which the test signal is only input to the in-memory FF 22. Next, the second test signal is scanned in and transmitted to the in-memory FF 22 in synchronization with the internal clock in the same manner as described above. The first test signal held in the FF 22 stores the memory in the memory. Access is made. In this memory access, if a read operation is performed, a read signal is transmitted to the FF 14 of the memory BIST.

  The memory test operation in the memory BIST circuit 10 is to perform a so-called memory test in which the memory 17 is disconnected from the logic unit, and an address signal, a control signal, and a write signal are directly input in an arbitrary pattern by a scan-in operation. This is a test for correctly performing writing and reading operations for all memory cells, and requires a large number of test patterns.

  FIG. 2 shows a block diagram of an embodiment of the FF to be scan chained in FIG. The FF includes a master flip-flop circuit MFF and a slave flip-flop circuit SFF. The master flip-flop circuit MFF takes in and outputs the first input signal when the internal clock clk is at a low level. At this time, the slave flip-flop circuit SFF holds the input signal captured before the first input signal. When the internal clock clk changes to a high level, the master flip-flop circuit MFF holds the first input signal, and the slave flip-flop circuit SFF takes in the first input signal and outputs it. As a result, the first input signal is transmitted from the slave flip-flop circuit SFF to the scan output SO or the subsequent logic stage or memory as indicated by the dotted line.

  When the internal clock clk changes to a low level, the master flip-flop circuit MFF takes in the second input signal, but the slave flip-flop circuit SFF holds the fetched first input signal. In this way, the input signal Din or SI selected by the selector MUX is determined at the edge at which the internal clock clk changes to a high level, and the input signal is output from the output SO (DQ) at that timing. Therefore, in the scan operation, the signal of FF01 is sequentially transmitted to FF04 and the signal of FF04 is sequentially transmitted to FF13 and the like in one cycle of the clock clk. In the test operation, the delay fault is detected by detecting that the signal of FF01 is correctly transmitted to FF22 through the selector 05 and the signal of FF22 is correctly transmitted to FF04 through the memory cell array 19 within one cycle of the clock clk. The presence or absence can be detected.

  A selector MUX is provided at the input of the master flip-flop circuit MFF, and a scan-in SI that receives the scan-out SO of the preceding flip-flop circuit is selected in the scan operation by a selection signal (scan enable signal) SEN. Further, in the normal operation and the test operation, the input terminal Din that receives the output signal of the logic unit 18 or the like is selected. As a result, the selection signal SEN switches between the scan operation for acquiring the test input signal and outputting the test result, and the test operation for detecting the delay fault and the normal operation.

  FIG. 3 shows a block diagram of an embodiment of the in-memory FF of FIG. In this embodiment, a scan enable SEN is provided in addition to the address signals A0 to Am, the data signals D0 to Dn and the write enable signal WEN and the chip enable signal CEN as the memory input signals. The address signals A0 to Am, the data signals D0 to Dn, the write enable signal WEN as the control signal, and the chip enable signal CEN are input to the FF including the master flip-flop circuit MFF and the slave flip-flop circuit SFF via the selector MUX. Is input. The selector MUX is supplied with the scan enable SEN as shown as a representative of the selector MUX corresponding to the signal CEN. If the write-through mode is instructed in the write mode, the data-in D0 to Dn taken into the FF is written into the selected memory cell of the memory cell array and amplified through the sense amplifier as described above. The data out Q0 to Qn are output as they are.

  Although not particularly limited, the FF is connected to the FF in a serial manner when the output signal SO as shown in FIG. 2 is input to the selector MUX at the next stage via one input of the AND gate circuit G, and is scanned. Chained. The scan enable SEN is commonly supplied to the other inputs of these gate circuits G as a gate control signal. That is, when the scan enable SEN is at a high level (logic 1), each gate G opens the gate and signal transmission for the scan chain connection is performed. If it is only for the scan chain, the gate circuit G can be omitted. By providing the gate circuit G, during normal operation, the gate of the gate circuit G is closed by the scan enable signal SEN, and its output is fixed at a low level. For this reason, it is possible to suppress an increase in power consumption due to the change in the output signal of the FF being always transmitted to the input of the selector MUX during normal operation. Therefore, the gate circuit G is provided adjacent to the output part of each FF.

  The scan-out SI of the memory is connected to the scan-out of the preceding FF, and the scan-out SO of the memory is connected to the scan-in of the subsequent FF. In this way, a scan chain including the memory circuit is performed. The test signal is serially input through such a scan chain, and the test result is serially output by the test signal taken into the FF.

  FIG. 4 shows a block diagram of another embodiment of the memory circuit of FIG. In this embodiment, an OR gate circuit OR is provided so that the write-through mode can be used even by a user function. The test signal TST and the write through signal WT formed by the user logic are input to the write through mode 20 of the memory through the gate circuit OR. As a result, the user logic also writes the write signal input to the memory input 02 to the memory cell array 19 via the FF and passes it through to the output 03 as it is, as in the test operation. You can

  FIG. 5 is a block diagram showing still another embodiment of the memory circuit of FIG. In this embodiment, the test mode 21 is provided, the memory cell array 19 is bypassed, and the selector 24 outputs a signal that has passed through the same number of delay elements 23 as when passing through the memory cell array 19. That is, a selector 24 for switching between the output of the memory cell array 19 and the output of the delay element 23 is provided, and a test mode 21 in which the delay element 23 side is always selected during a scan test is input as a select signal.

  By adopting the configuration as in the above embodiment, both the input and output of the memory can be subjected to the scan test. As a result, it is possible to detect a delay fault at the boundary of the memory simultaneously with other logic units by a method similar to a normal scan test. In other words, the operation margin of the circuit formed in the semiconductor integrated circuit tends to become smaller as the circuit becomes finer and faster. Therefore, a semiconductor integrated circuit device having high reliability can be obtained by detecting such a delay fault at the memory boundary.

  6 and 7 are main part block diagrams of an embodiment of the system LSI according to the present invention. Although FIG. 6 and FIG. 7 have the same configuration, the signal propagation path during the test operation is indicated by a solid line, and the signal propagation path not used in the test operation is indicated by a dotted line. That is, in FIG. 6, a delay fault between FF01, FF04 and FF11, FF12 corresponding to the logic 18 is detected, and in FIG. 7, a delay fault between the FF11, FF12 and the memory 17 is detected. is there.

  As shown in FIGS. 6 and 7, the system LSI is configured by chaining FF01 and 04 provided corresponding to the logic 18 in the same manner as described above, and FF13 and FF14 constituting the memory BIST circuit for the memory. ing. An input FF 11 and an output FF 12 are provided corresponding to the memory 17. A selector 05 is provided at the input section of the input FF, and a selector 25 is provided at the input section of the output FF. The selector 05 selects either the output of the FF01 corresponding to the logic 18 or the output corresponding to the FF13 of the memory BIST circuit. The selector 25 selects either the output 02 of the FF 11 or the output 03 of the memory cell array.

  6 and 7, the output of the FF 12 is shown to be selectively transmitted to either the FF 04 or the FF 14 as indicated by a solid line and a dotted line, but is fixed to one of them. It may be something that tells. However, in order to facilitate the understanding of the test mode of the invention, it is convenient to switch the signal transmission path as shown in the figure, and if the output signal is switched and transmitted as shown in the figure, the same selector as above May be provided. The FF11 and FF12 corresponding to the memory 17 are also scan chained.

  FIG. 6 shows a signal transmission path for detecting a delay fault between the FFs 11 and 12 that input and output signals to and from the memory 17 and the FF01 and FF04 corresponding to the logic 18. That is, the selector 05 selects the FF01 side, and the selector 25 selects the FF11 side. Then, the output of the FF 12 is transmitted to the FF 04 corresponding to the logic 18. With this configuration, a write operation is performed on the memory 17. By this write operation, the test signal scanned into FF01 is transmitted to FF11 by one cycle of the internal clock. The test signal scanned into the FF1 is transmitted to the FF12 through the selector 25 by one cycle of the internal clock. The test signal scanned into the FF 12 is transmitted to the FF 04 by one cycle of the internal clock. By such an operation, it becomes possible to detect a delay failure in the transfer from the user FF01 to the FF11 and a delay failure in the transfer from the FF12 to the user FF04.

  FIG. 7 shows a signal transmission path for detecting a delay fault between the FFs 11 and 12 and the memory 17. That is, the selector 05 selects the FF 13 side, and the selector 25 selects the memory output 03. The output of the FF 12 is transmitted to the FF 14 of the memory BIST circuit. With this configuration, writing and reading are performed from the memory BIST circuit to the memory 17 in synchronization with the internal clock. The write operation is performed to input a predetermined storage pattern into the memory cell array. Then, the stored information is sequentially read by a read operation. By performing the memory BIST operation with the actual speed clock in this way, detection of a delay failure in transfer from the FF 11 to the input 02 of the embedded memory 17 and a delay failure in transfer from the output 03 of the embedded memory 17 to the FF 12 are detected. Is possible. That is, it is possible to detect that the write signal is correctly written and read correctly in one cycle of the internal clock at the actual speed.

  By adopting the circuit configuration of this embodiment, the real-time memory BIST and the scan test are performed without changing the embedded memory 17 and the scan test method, so that a delay fault at the memory boundary can be prevented. Detection is possible.

  FIGS. 8 and 9 are main part block diagrams of another embodiment of the system LSI according to the present invention. Although FIG. 8 and FIG. 9 have the same configuration, the signal propagation path during the test operation is indicated by a solid line, and the signal propagation path that is not used in the test operation is indicated by a dotted line in the same manner as described above. That is, in FIG. 8, a delay failure of the read system path between the memory 17 and the FF 04 corresponding to the logic 18 is detected, and in FIG. 9, the delay of the write system path between the FF 01 corresponding to the logic 18 and the memory 17 is detected. Sexual failure is detected.

  As shown in FIG. 8 and FIG. 9, the system LSI is configured by chaining FF01, 04 provided corresponding to the logic 18 and FF13, FF14 constituting the memory BIST circuit for the memory as described above. ing. A selector 05 is provided corresponding to the memory input 02 of the memory 17, and a selector 06 is provided corresponding to the memory output 03 of the memory 17. The selector 05 selects either the output of the FF01 corresponding to the logic 18 or the output corresponding to the FF13 of the memory BIST circuit. The selector 06 selects a transmission path of the memory output 03 to either the FF 04 corresponding to the logic 18 or the FF 14 of the memory BIST circuit.

  8 and 9, the transmission path of the output 03 is switched by the selector 06, but a configuration in which the output 03 is transmitted to the FF 04 in a fixed manner may be employed. However, in order to facilitate understanding of the test mode of the invention, it is convenient to switch the signal transmission path as shown in the figure, and a selector 06 is provided for switching and transmitting the output signal as shown in the figure. . The embedded memory 17 has a forced read mode 26. When the forced read mode 26 is in an enabled state, the embedded memory 17 is always in a data reading state, and writing is not performed. The logic unit 18 is scanned.

  Detection of a delay fault at a memory boundary is divided into a read operation and a write operation of the memory 17. FIG. 8 shows a state during a memory read operation. In detecting a delay fault in the read operation of the memory 17, first, arbitrary data is written to all addresses of the embedded memory 17 using the memory BIST circuit 10. Next, an actual speed scan test is performed with the forced read mode 26 connected to the embedded memory 17 enabled. The test pattern used at this time is a pattern that takes into account the data written in the embedded memory 17 in the first operation. With the above operation, since the data output from the output 03 of the embedded memory 17 is input to the user FF 04, it is possible to detect a delay fault in the output system at the boundary of the memory, that is, in the read system path. Become.

  FIG. 9 shows a state during a memory write operation. First, an actual speed scan test is performed, and data is written into the embedded memory 17. Data to be finally written in the embedded memory 17 is obtained in advance. Next, using the memory BIST circuit 10, data is read from the embedded memory 17 and compared with data obtained in advance. For data comparison, for example, a compression method using MISR (Multiple-input signature register) can be considered. With the above operation, the data output from the user's FF01 during the scan test at the actual speed is written to the memory cell at the input 02 of the embedded memory 17, so that the memory boundary input, that is, the write system It becomes possible to detect a delay fault in the path. Also in this embodiment, the delay fault can be detected without changing the embedded memory 17 and the scan test technique, which is also useful as a method for detecting the delay fault.

  By adopting the configuration of the above-described embodiment, it is possible to detect a delay fault at the boundary of the memory by combining the memory BIST and the actual speed scan test without changing the design method of the embedded memory 17 and the logic unit 18. It will be possible.

  FIG. 10 is a block diagram showing an embodiment of an embedded memory mounted in the semiconductor integrated circuit device according to the present invention. The embedded memory 28 of this embodiment has a test mode 30. When the test mode 30 is enabled, the embedded memory 28 functions as a multi-bit FF. The embedded memory 28 is scanned in the same manner as the logic unit 18. That is, at the time of scanning, a selector 31 for selecting the input data 33 with the scan enable 32 is provided. The test mode 30 is always enabled, and the actual speed scan test is performed. That is, the storage information of the memory cell in which the data d0 is written every cycle of the internal clock is stored as the data d1 in the next cycle. Therefore, it is possible to detect a delay failure in the write system path and the read system path in the memory 28 in 0 to n cycles. By adopting such a configuration, it is possible to detect a delay fault at the boundary of the memory by performing an actual speed scan test.

  FIG. 11 is a block diagram showing an embodiment of an internally generated clock control circuit used in the semiconductor integrated circuit device according to the present invention. This internally generated clock control circuit is selected according to the shift clock SCLK supplied from the outside during the scan operation and the system clock (actual speed) CLK formed by the built-in PLL (clock generation circuit) during the scan test operation. Thus, the internal clock clk is formed. That is, in the scan operation, the test signal is scanned in corresponding to the slow-speed shift clock SCLK, and the circuit test including the delay fault detection as described above by the test signal corresponds to the high-speed system clock CLK. Scan test operation.

  The internally generated clock control circuit switches between the high-speed system clock CLK and the asynchronous shift clock SCLK. In the internally generated clock control circuit, when the scan test mode signal SCTM is at a high level (logic 1), the gate circuit G4 opens the gate, and the shift clock SCLK is transmitted as the internal clock clk through the OR gate circuit G5. Accordingly, the test signal is input in synchronization with the shift clock SCLK, and is transmitted to the flip-flop circuit FF through the scan chain.

  When the internal clock clk corresponding to the system clock CLK is formed, the scan test mode signal SCTM is set to a low level (logic 0), and the input of the shift clock SCLK is stopped. Then, the high level of the capture enable signal CPEN is captured in the opposite phase of the clock CLK, and the internally generated clock clk having the same cycle as the system clock is output for two cycles. That is, when two opposite phases of the internally generated clock CLK are input, the capture enable signal CPEN passes through the two FFs, and controls the gate circuit G1 to stop the internally generated clock.

  FIG. 12 is a block diagram showing an embodiment of a scan enable generation circuit used in the semiconductor integrated circuit device according to the present invention. In this embodiment, a high-speed single clock is enabled as a configuration in which scan enable control is switched between a single clock and a double clock. The internal clock clk is supplied to the clock terminal of the flip-flop circuit SFF. An OR gate circuit G6 is provided at the data input of the flip-flop circuit SFF. The chip scan enable signal CSEN is input to one input of the OR gate circuit G6. The output signal of the flip-flop circuit SFF is fed back to the other input of the gate circuit G6 through the inverter circuit NV3. The output of the flip-flop circuit SFF is supplied to the AND gate circuit G7. The AND gate circuit G7 is supplied with a switching signal S / W between a single clock mode and a double clock mode. The output signal of the gate circuit G7 and the chip scan enable signal CSEN are output as the scan enable signal SEN through the OR gate circuit G8.

  FIG. 13 is a waveform diagram for explaining the operation of the scan enable generation circuit of FIG. In the single clock mode, the signal S / W is set to the high level. As shown in FIG. 13A, even when the chip scan enable signal CSEN is set to the low level, the flip-flop circuit SFF outputs a high level (logic 1) until the first pulse of the clock clk arrives. . Therefore, the scan enable signal SEN that has passed through the gate circuits G6 and G8 is maintained at a high level. That is, the selector MUX provided in the input part of the scan flip-flop circuit FF in FIG. 2 selects the scan-in SI side. When the first clock clk arrives, the output of the flip-flop circuit SFF changes to low level, and the scan enable signal SEN is correspondingly changed to low level. When the second clock clk arrives, the low level output is inverted and fed back by the inverter circuit NV3, so that the output of the flip-flop circuit SFF changes to the high level again, and the scan enable signal SEN is also correspondingly High level.

  As a result, the final shift operation of the test signal is performed by the FF of the scan chain in synchronization with the first clock clk, and the test signal is transmitted to the logic stage, the memory, and the like. The signal transmitted through the logic stage, the memory, etc. is taken into the FF on the rear stage side in synchronization with the second clock clk. Since the scan enable signal SEN is set to the high level, the fetched downstream signal is serially output by supplying the shift clock SCLK to the low level again.

  In the single clock mode, the signal S / W is set to the low level. In this state, the gate of the gate circuit G7 is closed, and the scan enable signal SEN is set to low level by the chip scan enable signal CSEN being low level. The scan enable signal SEN is also set to high level by the high level of the chip scan enable signal CSEN. In this configuration, two pulses clk are output corresponding to the capture enable signal CPEN of FIG. In the double clock mode, the final shift operation of the test signal is also performed by the FF of the scan chain.

  In the double clock mode, the scan enable is set to the capture mode side before the first clock application, and then the test is performed by applying the clock twice. Since scan enable does not need to be switched in the test cycle, timing problems can be alleviated. However, in the double clock mode, since the clock is applied twice in the capture mode, it is handled as a two-stage sequential circuit in the test. For this reason, since it is not possible to directly recognize which of the two logic stages is a failure, the failure detection rate is less likely to be higher than in the single clock mode, and the test pattern is long.

  In this embodiment, by providing both the single clock mode and the double clock mode, the delay fault detection is performed in the single clock mode, and the auxiliary fault detection that cannot be performed in the single clock mode is performed in the double clock mode. By doing so, it is possible to detect a delayed failure with high reliability while preventing the test pattern from becoming long.

  FIG. 14 shows a waveform diagram of the test operation in the single clock mode. In the skin-in operation, a test signal is input from the outside of the semiconductor integrated circuit device at a low speed in synchronization with the shift clock SCLK. This skin-in operation is stopped immediately before the final shift by the low level of the chip scan enable signal CSEN. Then, by setting the capture enable signal CPEN to a high level, two pulses of a high-speed clock corresponding to the system clock CLK are output. In synchronization with the pulse clk, the scan enable signal SEN is formed as described above, and a delay fault test is performed at an actual speed corresponding to the system clock CLK.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. The scan test operation for detecting a delay fault at the boundary of the memory may be performed only in either the single clock mode or the double clock mode. However, since the delay failure in the logic stage and the delay failure in the single memory must be detected as described above, both the single clock mode and the double clock mode are provided, and the delay property in the single clock mode is provided. It is convenient to perform fault detection and to perform auxiliary fault detection in the double clock mode that cannot be performed. The present invention can be widely used as a semiconductor integrated circuit device such as a system LSI equipped with an embedded memory and a test method thereof.

1 is a principal block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. It is a block diagram which shows one Example of FF used as the scan chain of FIG. It is a block diagram which shows one Example of in-memory FF of FIG. FIG. 3 is a configuration diagram illustrating another embodiment of the memory circuit of FIG. 1. FIG. 6 is a configuration diagram showing still another embodiment of the memory circuit of FIG. 1. It is a principal part block diagram which shows one Example of the system LSI which concerns on this invention. It is a principal part block diagram which shows one Example of the system LSI which concerns on this invention. It is a principal part block diagram which shows another Example of the system LSI which concerns on this invention. It is a principal part block diagram which shows another Example of the system LSI which concerns on this invention. 1 is a configuration diagram showing an embodiment of an embedded memory mounted in a semiconductor integrated circuit device according to the present invention. 1 is a block diagram showing an embodiment of an internally generated clock control circuit used in a semiconductor integrated circuit device according to the present invention. 1 is a block diagram showing an embodiment of a scan enable generation circuit used in a semiconductor integrated circuit device according to the present invention. FIG. 13 is a waveform diagram for explaining the operation of the scan enable generation circuit of FIG. 12. It is a wave form diagram of the test operation in single clock mode. It is a block diagram of a system LSI equipped with an embedded memory studied prior to the present invention. It is a block diagram of a system LSI equipped with an embedded memory studied prior to the present invention.

Explanation of symbols

  01, 04, 13, 14, 22 ... FF (flip-flop circuit), 05, 06, 24, 31 ... selector, 17 ... memory, 18 ... logic, 19 ... memory cell array, 23 ... delay stage, MFF ... master flip-flop Circuit, SFF ... Slave flip-flop circuit, G1-G8 ... Gate circuit, NV1-NV3 ... Inverter circuit.

Claims (11)

Logic circuit;
A memory circuit in which memory access is performed by the logic circuit;
A test circuit including a scan chain for detecting a failure of the logic circuit and the memory circuit,
The scan chain includes first, second, third and fourth flip-flop circuits,
The first flip-flop circuit and the third flip-flop circuit respectively take in the first test signal and the third test signal for the memory circuit during the scan-in operation in the first test mode,
The second flip-flop circuit captures the second test signal for the memory circuit during the scan-in operation in the second test mode,
In the first test mode, the first test signal taken into the first flip-flop circuit is taken into the third flip-flop circuit through the first selector in synchronization with an internal clock, and the third flip-flop circuit The third test signal taken in is transmitted as an input signal for memory access to the memory circuit in synchronization with the internal clock,
In the second test mode, the second test signal taken into the second flip-flop circuit is taken into the third flip-flop circuit through the first selector in synchronization with the internal clock, and the third flip-flop circuit The signal held in the circuit is transmitted as an input signal for memory access to the memory circuit in synchronization with the internal clock,
The fourth flip-flop circuit captures an output signal from the memory circuit in synchronization with the internal clock in the first test mode and the second test mode,
The memory circuit is a test signal for transmitting the same signal as the write signal formed by the third flip-flop circuit to the fourth flip-flop circuit during a write operation in synchronization with the internal clock in the first test mode. A semiconductor integrated circuit device comprising a path. In claim 1,
2. The semiconductor integrated circuit device according to claim 1, wherein the test signal path is a read circuit that performs an operation of outputting a signal written in the memory cell when the test signal path is in an operation state in the first test mode. In claim 1,
The test signal path is
A delay circuit for transmitting a write signal formed by the third flip-flop circuit to the fourth flip-flop circuit in the first test mode with a delay time equivalent to a signal delay time in the memory cell array of the memory circuit. When,
A semiconductor integrated circuit device comprising: a second selector that switches between an output signal of the delay circuit and an output signal from the memory cell array according to an operation mode. In claim 1,
A PLL circuit;
The semiconductor integrated circuit device, wherein the internal clock is formed by the PLL circuit. Logic circuit;
A memory circuit in which memory access is performed by the logic circuit;
A test circuit including a scan chain for detecting a failure of the logic circuit and the memory circuit,
The scan chain includes first, second, third and fourth flip-flop circuits,
The first flip-flop circuit and the third flip-flop circuit respectively take in the first test signal and the third test signal for the memory circuit during the scan-in operation in the first test mode,
The second flip-flop circuit captures the second test signal for the memory circuit during the scan-in operation in the second test mode,
In the first test mode, the first test signal taken into the first flip-flop circuit is taken into the third flip-flop circuit through the first selector in synchronization with an internal clock, and the third flip-flop circuit The third test signal taken in is transmitted as an input signal for memory access to the memory circuit in synchronization with the internal clock,
In the second test mode, the second test signal taken into the second flip-flop circuit is taken into the third flip-flop circuit through the first selector in synchronization with the internal clock, and the third flip-flop circuit The signal held in the circuit is transmitted as an input signal for memory access to the memory circuit in synchronization with the internal clock,
The fourth flip-flop circuit captures an output signal of the third flip-flop circuit through the second selector in the first test mode in synchronization with the internal clock, and the second flip-flop circuit in the second test mode. A semiconductor integrated circuit device which takes in an output signal of the memory cell array through a selector. In claim 5,
A PLL circuit;
The semiconductor integrated circuit device, wherein the internal clock is formed by the PLL circuit. Logic circuit;
A memory circuit in which memory access is performed by the logic circuit;
A test circuit including a scan chain for detecting a failure of the logic circuit and the memory circuit,
The scan chain includes first and second flip-flop circuits,
The first flip-flop circuit captures the first test signal for the memory circuit during the scan-in operation in the first test mode,
The second flip-flop circuit captures the second test signal for the memory circuit during the scan-in operation in the second test mode,
The signal taken into the first flip-flop circuit is transmitted to the memory circuit through the first selector in synchronization with the internal clock in the first test mode,
The signal fetched by the second flip-flop circuit is transmitted to the memory circuit in synchronization with the internal clock through the first selector in the second test mode.
The semiconductor integrated circuit device, wherein the memory circuit transmits a read signal in the first test mode to the first or second flip-flop circuit. In claim 7,
The semiconductor integrated circuit device, wherein the first flip-flop circuit is also used in a test mode of the logic circuit. Logic circuit;
Memory access is performed by the logic circuit, and a memory circuit having a plurality of bits of a write node and a read signal node;
A test circuit including a scan chain for detecting a failure of the logic circuit and the memory circuit,
The scan chain sequentially transmits one of the outputs of the read node to one of the write nodes in the write test mode of the memory circuit, and transmits a signal from the logic circuit in a normal operation. Including selectors,
2. The semiconductor integrated circuit device according to claim 1, wherein the memory circuit includes an output operation for transmitting the same signal as the write signal to the read node in a test mode synchronized with the internal clock. Logic circuit;
A memory circuit in which memory access is performed by the logic circuit;
A test method for a semiconductor integrated circuit device comprising a test circuit having a scan chain including a first flip-flop circuit and a second flip-flop circuit for detecting a failure of the logic circuit and the memory circuit,
A first test signal for the memory circuit is input to the first flip-flop circuit by a first scan-in operation synchronized with a scan clock supplied from outside, and the first test signal is synchronized with the internal clock by the first test signal. The memory circuit performs writing and reading operations, performs a first test operation for transmitting an output signal of the reading operation to the first or second flip-flop circuit, and performs reading by a first scan-out operation synchronized with the scan clock. Compare with the expected value,
A second test signal for the memory circuit is input to the second flip-flop circuit by a second scan-in operation synchronized with the scan clock, and the memory circuit is synchronized with the internal clock by the second test signal. The second test operation is performed to transmit the output signal of the read operation to the first or second flip-flop circuit, and the read-out operation is synchronized with the scan clock and compared with the expected value. ,
A test method for a semiconductor integrated circuit device, comprising detecting a delay fault between the logic circuit and the memory circuit by a combination of the first test mode and the second test mode. In claim 10,
The semiconductor integrated circuit device includes a PLL circuit,
A test method for a semiconductor integrated circuit device, wherein the internal clock is formed by the built-in PLL circuit.

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