JP2001093300A - Synchronous memory device recording history of input signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record an address signal and a command signal inputted to a memory device or a memory module and to enable reading out them as necessary so that cause analysis of malfunction can be performed easily. SOLUTION: Relating to a synchronous memory device inputting an address and a command synchronizing with a clock and the prescribed strobe signal and a memory module 10 incorporating it, the device is characterized by that recording means 40, 80 recording address signals of the prescribed cycles and a command signal are provided in a memory device or on a memory module and these signals of the prescribed cycles are always recorded and held in a recording means. In such constitution, when malfunction is caused, a system incorporating a memory device is stopped once, the memory device and the memory module are switched to a diagnosis mode, and address signals of the prescribed cycles and a command signal directly before malfunction, can be read out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous memory device for inputting an address or a command in synchronization with a clock or a predetermined strobe signal and a memory module having the same, and more particularly to an input for facilitating failure analysis. The present invention relates to a memory device capable of recording a signal history and a memory module equipped with the same.

[0002]

2. Description of the Related Art A synchronous dynamic random access memory (DRAM) for inputting an address or a command in synchronization with a clock or a strobe signal is widely used as a semiconductor memory device capable of operating at high speed.
In recent years, such a memory device performs data input / output in synchronization with a clock or inputs an address or a command in synchronization with a clock or a predetermined strobe signal in response to a demand for higher speed.

[0003] As the width of the bus on the motherboard increases, a plurality of such memory devices are generally mounted on a module substrate and mounted on the motherboard as memory modules. In that case,
A register is provided on the module board to temporarily receive an address signal and a command signal supplied from a memory controller on the motherboard, and to supply the captured address signal and command signal to a plurality of memory devices mounted on the motherboard. Can be Thus, the register only needs to drive the address signal lines and the command signal lines on the module substrate which have a relatively small driving load, and can supply these signals to a plurality of memory devices at high timing.

Accordingly, in the memory module, a clock and a predetermined strobe signal supplied from the memory controller are once taken in, and the phase is adjusted and supplied to a plurality of memory devices in the module.

[0005]

However, in the case of such a memory module, a synchronous clock, a predetermined strobe signal, and an address signal and a command signal synchronized with the synchronous clock and the strobe signal are adjusted again in phase on the module, and then are transferred to a plurality of memory devices. Since they are supplied, the timing may be shifted in each memory device. If the timing shift occurs, an inappropriate address or command is input to the memory device at the timing of the synchronization signal, causing a malfunction.

FIG. 6 is a timing chart for explaining a conventional problem. FIG. 6A shows an example of a synchronous DRAM. The synchronous DRAM inputs an address signal and a command signal supplied from the memory controller in synchronization with a rising edge of a clock CLK which is a synchronization signal. For example, an address and a command supplied in synchronization with the rising edge t1 of the clock CLK are taken into the memory device.
This allows the memory controller to supply addresses and commands at a high speed according to the clock frequency.

However, in a memory module or the like, a module register for transferring the clock CLK and commands and addresses is provided on a module substrate. When these commands and addresses are supplied to a plurality of mounted memory devices in synchronization with the clock CLK via the module register, FIG.
As in the case of the edge t2 in (A), the timing of the rising edge of the clock CLK, which is the synchronization signal, may differ from the timing at which the address or command is supplied. In the example of FIG. 6A, the rising edge t2 of the clock CLK is shifted earlier. In this case, the memory device on the module substrate takes in inappropriate addresses and commands.

In such a case, a read operation or a write operation is performed on a memory cell corresponding to an inappropriate address, or a command decoder in a memory device cannot properly decode in response to an inappropriate command. ,
In some cases, the command may be incorrectly recognized as another command and an inappropriate operation may be performed.

FIG. 6B shows an example of a general-purpose DRAM. The general-purpose DRAM has a strobe signal RAS.
(Row Address Strobe) and CAS (Column Address Stro)
be) The corresponding address is fetched in synchronization with the falling edge of the signal. Again, the falling edge t
In the case of 1, there is no shift in timing and an appropriate address is taken in. However, in the falling edge t2, the timing is shifted and an appropriate address is not taken in. In this case, it also causes a malfunction.

[0010] Other factors may cause the memory device to malfunction for some reason. In either case, it is necessary to perform a failure analysis on such a memory device, but it is very difficult to analyze the cause of the defective operation from the use status and use state included in the user's complaint.

If improper data input is performed,
Since such data is usually recorded in a memory cell, the input write data can be read, and it can be analyzed whether or not the data has been properly written. When a signal is input and an erroneous operation occurs with it, it is difficult to find the cause.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device capable of relatively easily performing a failure analysis and a memory module having the same.

Still another object of the present invention is to provide a memory device capable of recording an input history of addresses and commands and a memory module equipped with the same.

[0014]

According to one aspect of the present invention, there is provided a synchronous memory device for inputting an address or a command in synchronization with a clock or a predetermined strobe signal, and a memory device having the same. In a memory module, a recording means for recording address signals and command signals for a predetermined cycle is provided in a memory device or on a memory module, and these signals for a predetermined cycle are always recorded and stored in the recording means. It is characterized by the following.

With this configuration, when a malfunction occurs, the system on which the memory device is mounted is temporarily stopped, the memory device or the memory module is switched to the diagnostic mode, and the address signals and the like for a predetermined cycle immediately before the malfunction are detected. Command signals can be read. Therefore, the cause of the malfunction can be relatively easily found using the read signals as clues.

According to another aspect of the present invention, there is provided a synchronous memory device for inputting an address and / or a command in synchronization with a predetermined synchronization signal.
In response to the input address and / or command, a memory core that performs a predetermined operation, an input recording unit that records the input address and / or command, and in response to a predetermined diagnostic mode signal, A diagnostic output circuit that outputs an address and / or a command recorded in the input recording unit.

According to the above invention, the latest history of the address signal and the command signal input to the memory device can be read out, which is convenient for analyzing the cause of the malfunction.

According to another aspect of the present invention, there is provided a memory module including a plurality of synchronous memory devices for inputting an address and / or a command in synchronization with a predetermined synchronization signal. The address and / or command supplied from outside is input in synchronization with the predetermined synchronization signal, and the input address and / or command is further stored in synchronization with the predetermined synchronization signal in the plurality of memories. A module register for supplying to the device, wherein the module register records the address and / or the command, and in response to a predetermined diagnostic mode signal, the address and / or recorded on the recording unit. A diagnostic output circuit for outputting a command.

According to the above invention, the latest history of address signals and command signals input to the memory module and supplied to the memory device can be read, which is convenient for analyzing a malfunction of the memory module.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.

FIG. 1 is a configuration diagram of a memory module according to the present embodiment. The memory module shown in FIG. 1 has eight memory devices on a module substrate 10.
Equipped with MD0 to MD7. The module substrate 10 includes a data input / output terminal DQ provided for each of the memory devices MD0 to MD7, an address and command input terminal A / C commonly provided for all the memory devices MD0 to MD7, and a And a clock input terminal CLK0 provided commonly. Further, on the module board 10, addresses and commands output from the module register are output from an address and command signal line 12 that supplies all memory modules MD 0 to MD 7 in parallel and a PLL (phase locked logic) 18. And a module clock wiring 13 for supplying the module clock to all the memory modules.

The clock, which is the synchronization signal supplied to the clock input terminal CLK0, is supplied to a PLL circuit 18, which generates a module clock CLK1 phase-synchronized with the input clock CLK0. It is supplied to all the memory devices at the same time, and is also supplied to the module register 16.

The module register 16 inputs an address signal and a command signal A / C supplied from a memory controller (not shown) in synchronization with the clock CLK1, and thereafter synchronizes with the input address signal and command in synchronization with the clock CLK1. Supply signal A / C to all memory devices.

A memory controller (not shown) is usually provided on a motherboard on which a memory module is mounted, and supplies an address signal and a command signal to the memory module via an address bus and a command bus on the motherboard. The address bus and the command bus on the motherboard have a relatively large driving load, and the timing of the command signal and the address signal propagating on the bus may be shifted with respect to the clock CLK0.

On the other hand, the address and command signal lines 12 on the module substrate 10 have a smaller driving load than the bus on the motherboard, and
Clock CLK1 between 6 and memory devices MD0-MD7
There is little possibility that the timing will shift. Therefore,
Module register 16 on module substrate 10
By providing the address signal and the command signal A / C to a plurality of memory devices on the module after adjusting the timing with the clock CLK1 which is the synchronization signal, the strobe signal is higher than the clock CLK1. The address signal and the command signal A / C can be supplied to the memory device at accurate timing.

However, as described above, the timing of the address signal or command signal actually supplied to the memory device for some reason may be shifted from the timing of the rising edge of the clock CLK1 which is the synchronization signal. In such a case, an inappropriate address signal or command signal is supplied to the memory device, causing a malfunction. Alternatively, for some other reason, an inappropriate address signal or command signal is supplied to the memory device,
In some cases, a malfunction may occur. For example, it cannot be said that there is no cause such as an inappropriate address or command being supplied by the memory controller.

In any case, it is convenient to analyze the cause of the malfunction of the memory module if it is possible to investigate the history of the input address or the input command immediately before the malfunction.

FIG. 2 is a configuration diagram of a memory device according to the present embodiment. The clock CLK1 in the module is input to the clock buffer 21 to generate the clock clk1 in the memory device. The clock clk1 is an input buffer and latch circuit 22 for inputting an address and a command A / C as an address and a command fetch clock.
23 and 25. The input buffer and latch circuits 22, 23, and 25 input and latch the address signal and the command signal A / C supplied from the module register 16 in synchronization with the clock clk1.

The memory device MD has an address latch circuit 30 and a decoder 32 as a configuration of a normal memory core.
And a cell array and sense amplifier group 34. In the cell array 34, a plurality of memory cells including, for example, one transistor and one capacitor are arranged at intersections of word lines and bit lines (not shown).

If the memory device MD is, for example, a synchronous D
In the case of a RAM, a command decoder 26 for decoding an input command, a mode register 27 for recording predetermined mode data in response to a mode set signal from the command decoder 26, and a decoding result signal ( For example, the control circuit 28 generates an internal control signal in response to read, write, active, refresh, and the like.

Data DATA from the cell array and sense amplifier group 34 is output from an output circuit 36 to an input / output terminal DQ via a switch 46 described later. Alternatively, write data is supplied from the input / output terminal DQ to the cell array and the sense amplifier group 34 via an input circuit (not shown).

The memory device MD shown in FIG. 2 records and holds an input address signal or command signal A / C for a predetermined number of clock cycles (for example, 10 cycles or 20 cycles). Part 4
Has zero. The address / command recording unit 40 includes an address / command register 42 for recording an address signal or a command signal in response to a timing signal S48, and a parallel / serial conversion for converting a parallel output from the address / command register 42 to a serial output. Circuit 44
And a frequency divider 49.

The above-mentioned parallel / serial conversion circuit 44
Is necessary when the number of bits of the input address and the command signal is larger than the number of output terminals DQ. The example of the parallel-serial conversion circuit 44 here is an example in which N address or command signals are output from one output terminal DQ.

In the address / command recording section 40, the address signal and the command signal A / C input in synchronization with the clock clk1 are synchronized with the timing signal S48 formed from the clock clk1, and the command register A is output every clock cycle. 42. At this time, the diagnostic mode signal TEST
Is in the L-level normal mode. Therefore, the output switch 46 is connected to the cell array and the sense amplifier 3.
A which connects the data bus DATA from No. 4 to the output circuit 36
Connected to the side. One input of the AND gate 47 is an inverted signal of the diagnostic mode signal TEST and is at the H level.
The signal passes through a gate 47 and an OR gate 48 and is supplied as a timing signal S48.

The address / command register 42 is provided with, for example, a plurality of cycles of flip-flops corresponding to a plurality of bits of the address signal and the number of bits of the command signal. Then, the input address signal and command signal are recorded every clock cycle in synchronization with the capture clock clk1. Therefore, the address / command register 42 can hold an address signal and a command signal for a plurality of cycles. If the recording capacity of the address / command register 42 is exceeded, the old address signal and the command signal are erased, and the address signal and the command signal for the latest plural cycles are held. In this embodiment, for example, the latest address signal and command signal for 20 cycles are stored in the address / command register 42.
Is held.

In the normal mode, an internal operation according to the input command is performed. For example, in the read mode, the input address is decoded by the decoder 32, the data of the selected memory cell is read by the sense amplifier, and the output terminal DQ is output from the output circuit 36 via the data bus DATA and the output switch 46. Is output to The output circuit 36 outputs the output data DATA to the output terminal DQ in synchronization with the data output clock clk2.

As described above, in the normal mode, the address
The command recording unit 40 records the latest history of the input address signal and command signal. Therefore, when a malfunction occurs for some reason, a failure analysis is performed by analyzing the latest recorded history.

In the diagnostic mode, the diagnostic mode signal TEST is high.
Level, the output changeover switch 47 is connected to the B side, and the address / command recording unit 40
Connected to. The diagnostic mode signal TEST can be supplied from the memory controller by providing a dedicated external terminal to the memory device MD. In that case, as shown in FIG.
It is necessary to provide a diagnostic mode signal terminal TEST and its signal line. Otherwise, the diagnostic mode signal TEST may be set in the mode register 27 in response to a command signal supplied from the memory controller. In that case, the diagnostic mode signal TEST is generated inside the memory device.

When the diagnostic mode signal TEST becomes H level,
The AND gate 47 is closed, the AND gate 50 is activated, and the data output clock clk2 is supplied to the frequency divider 49 and the parallel-to-serial converter 44 via the AND gate 50 as the clock S50. The parallel-to-serial converter 44 converts an N-bit recorded signal into 1-bit serial data. Then, the frequency divider 49 divides the frequency of the data output clock clk2 by 1 / N, and outputs the timing signal S49 in one cycle for every N clocks. Accordingly, in response to the timing signal S48 generated once every N data output clocks clk2, the address / command register 42 records the internally stored address and command signals in the parallel / serial conversion unit 44. Transfer to

The parallel / serial conversion unit 44
Outputs N recorded input signals serially in synchronization with a timing signal S50 synchronized with the data output clock clk2. The history of the address signal and the command signal is output from the output circuit 36 to the output terminal DQ in synchronization with the data output clock clk2.

As described above, by setting the diagnostic mode signal TEST to the H level, the history of the latest address signal and command signal recorded in the address / command recording unit 40 can be read from the output terminal DQ. Therefore, it is possible to relatively easily perform the failure analysis of the malfunction based on the history.

FIG. 3 is a configuration diagram of a memory device according to a modification of the embodiment of FIG. In this example, the number of signals recorded by the address / command recording unit 40 is the output terminal
Applicable if the number is less than or equal to the number of DQs Therefore, the address / command recording unit 40 is not provided with a serial / parallel conversion circuit. Instead, the output of the address / command register 42 is directly connected to the switch 46
0, 461, 46m, output circuits 360, 36
Output to 1,36m. Other configurations are the same.

Therefore, in the memory device of FIG. 3, in the normal mode, the address / command fetch clock clk1
An address signal and a command signal A / C are inputted in synchronism with the above, and are recorded in the address / command register 42. Then, in the diagnostic mode, the diagnostic mode signal TEST becomes H level, and in synchronization with the data output clock clk2,
The history of the latest address signal and command signal recorded in the address / command register 42 is stored in the switch 4.
60, 461, 46m, output circuits 360, 361, 36
m to output terminals DQ0 to DQm.

FIG. 4 is a configuration diagram of a memory module according to the second embodiment. In the second embodiment, the history of the address signal and the command signal A / C supplied from the memory controller are recorded in the module register 16 mounted on the module substrate 10 and read as needed. The eight memory devices MD0 to MD7 mounted on the module board 10 include the memory devices shown in FIGS.
A recording unit for recording the address signal and the command signal as shown in FIG.

The memory module in the embodiment shown in FIG. 4 has an input / output terminal DQ of each memory device and an address / command signal terminal A / C connected to the module register 16 on the module substrate 10 as in FIG. And a clock input terminal CLK0. Further, the memory module of FIG. 4 includes, on the module substrate, a diagnostic mode signal terminal TEST for reading the history of address signals and command signals recorded in the register 16 and a recording signal output terminal Tout for outputting those signals. Is provided. Further, the module substrate 10 is provided with a PLL circuit 18 which receives the clock CLK0 supplied from the memory controller and generates a module clock CLK1 synchronized with the clock CLK0. When each memory device has a recording unit as shown in FIGS. 2 and 3, a diagnostic mode signal terminal for the memory device also needs to be provided on the module substrate 10.

FIG. 5 is a configuration diagram of the module register 16 of FIG. As described above, the register 16 provided on the module substrate 10 stores an address signal and a command signal A / C supplied from a memory controller (not shown),
Once input in synchronization with clock CLK1, the next clock CLK1
The address signal and the command signal A / C held in the memory device MD on the module substrate are supplied in synchronization with. As a result, it becomes possible to supply an address signal and a command signal A / C synchronized with the clock CLK1 to a plurality of memory devices in the memory module at a highly accurate timing.

Therefore, the module register 16 includes an input buffer and latch circuits 61, 62 to 6n for inputting and latching the input address signal and the command signals A / C1 to A / Cn in synchronization with the clock CLK1. A register section 52 having output buffers 71, 72 to 7n for outputting them to each memory device at a clock CLK1 at the next timing.
Having.

Further, the module register 16 stores address signals and command signals A / C supplied to each memory device.
Is recorded in the address / command recording unit 80. The configuration of the address / command recording unit 80 is substantially the same as the configuration of the address / command recording unit 40 in the memory device shown in FIG. However, the module register 16
Is not provided with a data output circuit such as a memory device. Therefore, the address / command recording unit 80
Has a dedicated output circuit 86 from which a dedicated address / command recording signal output terminal Tout is output.
Output the signal recorded in If the number of the address / command recording signal output terminals Tout is one or the number of the address signal and the command signal is smaller than the number, the parallel-serial conversion unit 84 is provided.

When the diagnostic mode signal TEST supplied to the module register 16 is in the normal state of L level, the address signal and the command signal A / C input from the register section 52 and supplied to each memory device are converted into the timing signal S90. Is recorded in the address / command register 82 in synchronization with. The timing signal S90 is set to AN by the clock CLK1.
It is formed via a D gate 87 and a NOR gate 90. The address / command register 82 can hold, for example, an address signal and a command signal for 20 cycles.

When the diagnostic mode signal TEST changes to the H level and the diagnostic mode is set, the clock CLK1 is supplied via the AND gate to the frequency divider 89, the parallel conversion circuit 84 and the output circuit 86.
Supplied to The frequency divider 89 divides the clock S88 by 1 / N
The frequency signal is divided and the timing signal S90 is generated once every N clock cycles, and the history recorded in the address / command register 82 is converted into a parallel / serial converter 84.
Output to Then, in synchronization with the clock CLK1, the address signal and the command signal A / C that have been subjected to the parallel / serial conversion are output from the output circuit 86.

With the above configuration, the memory module
The history of the address signal and command signal supplied from the memory controller before the malfunction and supplied to each memory device can be retained. When the malfunction is diagnosed, the history data can be read and used for analyzing the cause of the malfunction. .

If the same history of the address signal and the command signal can be recorded and read out on the memory device side, the history in the module register 16 is compared with the history in the memory device to further analyze the malfunction. Can be used for

In the above-described embodiment, the history of the address signal and the command signal recorded in the analysis of the malfunction of the memory module and the memory device is used. It can also be used to investigate the ability of input timing control of command input signals. For example, by shifting the timing of a clock which is a synchronization signal, it is also possible to check how much the address or command signal is correctly input and to use it for measurement of a setup time or a hold time.

In the above-described embodiment, a clock has been described as an example of a synchronization signal. However, a strobe signal such as a RAS signal or a CAS signal can be similarly used. Further, any one of the address signal and the command signal may be recorded. However, by recording the histories of both signals, it becomes easier to analyze a malfunction.

As described above, the protection scope of the present invention is not limited to the above-described embodiment, but extends to the inventions described in the claims and their equivalents.

[0056]

As described above, according to the present invention, it is possible to easily analyze a failure of a memory device or a memory module generated in a system.

Further, the present invention can be used not only for defect inspection but also for investigating the ability of the memory device or the memory module for the timing accuracy of input signal fetching.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory module in the present embodiment.

FIG. 2 is a configuration diagram of a memory device according to the embodiment.

FIG. 3 is a configuration diagram of a memory device according to a modification of the embodiment of FIG. 2;

FIG. 4 is a configuration diagram of a memory module according to a second embodiment.

FIG. 5 is a configuration diagram of a module register 16 of FIG. 4;

FIG. 6 is a timing chart for explaining a conventional problem.

[Explanation of symbols]

 10 Module board 16 Module register MD0-7 Memory device 40, 80 Address / command recording section 46 Output switching output 36, 86 Output circuit A / C address signal, command signal TEST Diagnostic mode signal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B018 GA03 HA32 KA01 MA32 NA02 PA03 QA13 RA11 RA13 5B024 AA15 BA21 BA29 CA07 CA16 EA06 5L106 AA01 DD12 GG05 GG07

Claims (8)

[Claims] 1. An address and / or synchronizing with a predetermined synchronizing signal.
Or a synchronous memory device that inputs a command, a memory core that performs a predetermined operation in response to the input address and / or command, and an input recording unit that records the input address and / or command. And a diagnostic output circuit for outputting an address and / or a command recorded in the input recording unit in response to a predetermined diagnostic mode signal. 2. The memory device according to claim 1, wherein the input recording unit holds the input address and / or command for a plurality of cycles. 3. The data output circuit according to claim 1, wherein a data output circuit connected to the memory core and outputting data is also used as the diagnostic output circuit, and the output circuit is in the normal mode. Wherein the output circuit operates as the diagnostic output circuit in a diagnostic mode corresponding to the diagnostic mode signal. 4. The diagnostic output circuit according to claim 1, wherein the address and / or command is composed of a plurality of bits, and the recording unit converts the recorded address and / or command from parallel to serial to the diagnostic output circuit. A memory device having a conversion circuit for transferring. 5. A memory module having a plurality of memory devices according to claim 1, wherein the externally supplied address and / or command is input in synchronization with the predetermined synchronization signal. Further, in synchronization with the predetermined synchronization signal, the input address and / or
Or a memory module having a module register for supplying a command to the plurality of memory devices. 6. An address and / or synchronizing with a predetermined synchronizing signal.
Or a memory module equipped with a plurality of synchronous memory devices for inputting commands, wherein the address and / or command supplied from outside are input in synchronization with the predetermined synchronization signal, and the predetermined synchronization signal In synchronization with the input address and / or
Or a module register that supplies a command to the plurality of memory devices, wherein the module register records the address and / or the command, and records the address and / or the command in the recording unit in response to a predetermined diagnostic mode signal. And a diagnostic output circuit for outputting the address and / or command. 7. The memory module according to claim 6, wherein the recording unit holds the input address and / or command for a plurality of cycles. 8. The diagnostic output circuit according to claim 6, wherein the address and / or the command is constituted by a plurality of bits, and the recording unit converts the recorded address and / or the command from parallel to serial to the diagnostic output circuit. A memory module having a conversion circuit for transferring.