JP3176144B2 - Synchronous static memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous static memory, and more particularly, to a synchronous static memory having a function of taking in an address, write data and a control signal at the edge of a clock and automatically generating a write pulse signal internally. Regarding memory.

[0002]

2. Description of the Related Art Recent advances in LIS technology have greatly improved system performance. Accordingly, semiconductor memories that can be accessed at higher speeds are also required. Generally, asynchronous static memories are used as these ultra-high-speed semiconductor memories.

[0003] Asynchronous static memory (hereinafter referred to as SRAM)
) Can read and write data at the corresponding address by inputting an address, and does not require complicated timing control unlike a dynamic memory. However, as the performance of the system improves, timing skew occurs due to variations in the wiring impedance on the system board or the external drive capability of the output buffer inside the LSI, and the speed requirements for the conventional asynchronous SRAM become more severe. Has become. Further, it is difficult to secure the pulse width of the write pulse generated by the write pulse generating circuit on the system board.

[0004] From the above background, a synchronous SRAM called "Self Timed RAM" has appeared (hereinafter referred to as STRAM). The configuration and operation of this STRAM will be described with reference to the block diagram of FIG. 6 and the timing chart of FIG.

[0005] An address ADD, write data Din, a chip select signal (CS) (Negative logic is usually represented by an upper bar of a sign, but in the present specification and drawings, this is indicated by surrounding the sign with ()) and Write control signal (W
E) is the storage register 1 at the rise of the clock signal CLK.
2

The memory array 13 is accessed based on the information stored in the storage register 12, and the read information is transmitted from the memory array 13 to the storage register 14 in a read cycle. The read information Dout transmitted to the storage register 14 is output to the output terminal at the rising edge of the next cycle of the clock CLK. On the other hand, if it is a write cycle, the write pulse generation circuit 15 automatically generates a write pulse, and write data is written to the memory array 13.

As shown in FIG. 7, the address, chip select signal (CS) and write control signal (WE) need only satisfy the setup time ts and the hold time tH with respect to the rising edge of the clock CLK. Is very simple. For example, even if these input signals have timing skew on the system board,
It is relatively easy to set the timing so as to satisfy the setup time ts and the hall degree time tH,
Since the write pulse is automatically generated internally, there is no need to worry about the write pulse width outside the memory. Therefore,
The use of STRAM greatly facilitates system design.

As the majority of recent microprocessors occupy 32 bits, the STRAM is also required to have a large bit width. Therefore, if the data input terminal and the output terminal are separated from each other as in the related art, the number of pins increases when the multi-bit configuration is used, and the package also has multiple terminals. Therefore, a method of connecting a data input terminal and an output terminal and putting them together as an I / O terminal is generally used in a multi-bit STRAM. As an example, FIG. 8 shows a pin arrangement of a 128K × 8-bit STRAM proposed by JEDEC which is an international device specification determining organization. Since this 128K × 8-bit STRAM has an I / O terminal configuration, it requires only a 36-pin package. However, if eight I / O terminals are separated into a data input terminal and an output terminal, a 44-pin package is required. Is required.

An STRAM having this I / O terminal configuration generally has a configuration shown in FIG. In FIG. 9, 16 is a storage register for taking in an address, 17 is a memory array, 18
Is a write driver, 19 is a storage register for capturing write data, 20 is a storage register for capturing read data, 21 is a three-state output buffer for transmitting output data to an I / O terminal, 22 is a chip select signal (CS),
A group of storage registers for capturing an output control signal (OE) and a write control signal (WE), 23 is a write pulse generation circuit, 24 is a storage register for capturing output control information, 25
Is an AND circuit that outputs output control information in response to a chip select signal (CS) and a write control signal (WE).

Next, the read operation will be described with reference to FIG.

In response to the rising edge of the clock CLK,
The address ADD is taken into the storage register 16, and the chip select signal (CS), the output control signal (OE) at a low level, and the write control signal signal (WE) at a high level
Is stored in the storage register 22. Storage register 16
The data is read from the memory array 17 in response to the address ADD held in the storage register 20 and supplied to the storage register 20. In response to the rise of the clock CLK in the next cycle, the read data is latched in the storage register 20, and the data “1” from the AND circuit 25 is latched in the storage register 24. In response to the data "1" from the storage register 24, the output buffer 21 opens, and the read data Dout is output to the I / O terminal after a predetermined delay time TAA from the rise of the clock CLK.

Next, a write operation will be described with reference to FIG.

In response to the rising edge of the clock CLK,
The write address ADD is latched in the storage register 16, and the low-level chip select signal (CS), the write control signal (WE), and the high-level output control signal (OE) are captured in the storage register 22. The write data Din supplied to the I / O terminal is also stored in the storage register 19.
It is taken in. The write pulse generating circuit 23 generates a write pulse in the same cycle in response to the chip select signal (CS) and the write control signal (WE), and the write driver 18 writes the data Din at the position specified by the address ADD. .

Referring to FIG. 12, a read operation after a write operation will be described.

In response to the rising edge of the clock CLK,
Read address ADD, chip select signal (C
S), output control signal (OE), write control signal (W
E) is taken into the storage registers 16 and 22, and in that cycle, data is written to the memory array 17.
In response to the rising edge of the next cycle of the clock CLK, the read address ADD and the chip select signal (C
S), output control signal (OE), write control signal (W
E) is taken into the storage registers 16 and 22, and the read data Dout is output to the I / O terminal after the rise of the clock CLK in the next cycle.

Finally, the write operation after the read operation will be described with reference to FIG.

Assuming that the (Q-1) th data is read out in the T1 cycle, a high-level output control signal (OE) is fetched into the storage register 22 in this cycle. The low-level output of 25 is taken into the storage register 24, and the output buffer 21 is set to a high impedance state. Thereafter, the write data Din is fetched into the storage register 19 in the cycle T3.

[0018]

As described above,
STRAM with I / O common terminal, after read operation,
At the time of transition to the write operation, an idle cycle for setting the output buffer to the high impedance state is required, and there is a disadvantage that the performance of the system is reduced.

The present invention has been made in view of the above problems, and has as its object to provide an STRAM which can operate at high speed without increasing the number of terminals.

[0020]

According to the present invention, there is provided an address terminal for supplying one of upper and lower bits of an address, and the other bit of the address and write data supplied in a time-division manner within one cycle. A common terminal, a data output terminal for outputting read data, a control terminal for supplying a control signal, a clock terminal for supplying a clock signal, and a memory array for storing data.
Addressing the memory array from the common terminal and the address terminal in response to a first edge of the clock signal, the address being connected to the common terminal, the address terminal, the clock terminal, and the memory array; Means for reading data from the control signal.
When instructing, the position specified by the addressing means
Data from the device and output it to the data output terminal.
Reading means, which is connected to the common terminal, the clock terminal, and the memory array, fetches the write data from the common terminal in response to a second edge of the clock signal, and reads the write data from the addressing means of the memory array. Means for writing the write data at a designated position.

[0021]

In the present invention, the clock signal from the outside
1 to provide an address on the second edge of the clock signal.
Write data supplied at the edge is specified by the address.
In the memory cell array area within one cycle
No. As a result, the present invention reduces the number of external terminals.
In addition to being able to
When switching to the write operation, set the output buffer to high impedance.
-Requires idle cycle to set to dance state
And high-speed operation becomes possible.

[0022]

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a synchronous SRAM of this embodiment. The configuration shown in this block diagram is a configuration in a case where address data is n bits, write data and output data are both m bits, and n ≧ m.

In FIG. 1, ADDk / Dink terminals (k
.Ltoreq.m), the lower m bits and m bits of the n-bit address ADD are supplied in a time-division manner.
External terminals. The ADDk terminals (m <k ≦ n) are (nm) external terminals to which upper (nm) bits of the address ADD are supplied. Doutk terminal (k ≦
m) are m external terminals for outputting read data.

Reference numeral 1 denotes a storage register for taking in the address ADD supplied to the ADDk / Dink terminal in a time-sharing manner at the rising edge of the clock CLK, and reference numeral 2 denotes ADDk / Dink.
A storage register for taking in the write data Din transmitted to the terminals in a time-division manner at the rising edge of the clock (CLK) (falling edge of the clock CLK), 3 is a decoder for decoding addresses, 4 is a memory array for storing data, 5
Is a sense amplifier group for amplifying information read from the memory array 4, 6 is a storage register for capturing the output data of the sense amplifier group 5, 7 is a storage register for capturing the address ADD supplied to the ADDk terminal, and 8 is a write driver. , 9 are write pulse generating circuits for generating write pulses, and 10 and 11 are chip select signals (CS), respectively.
And a storage register for receiving a write control signal (WE).

Next, the operation of the STRAM of this embodiment will be described with reference to the timing charts of FIGS.

(I) In the case of a read operation, ADDk /
Supply the lower m bits of the address ADD to the Dink terminal,
The upper (nm) bits of the address ADD are supplied to the ADDk terminal, and a low level (selection level) chip select signal (CS) and a high level (read level) write control signal (WE) are written to the chip select terminal. Supply to control terminal.

As shown in FIG. 2, in response to the rise of the clock CLK, the storage registers 1 and 7 store the address AD.
D, and the storage registers 10 and 11 receive the chip select signal (CS) and the write control signal (WE). The decoder 3 decodes the address ADD stored in the storage registers 1 and 7 and selects a corresponding memory cell of the memory array 4. The small signal read from the selected memory cell is amplified by the sense amplifier unit 5 and stored in the storage register 6 at the rising edge of the next cycle of the clock CLK.
The output data Dout is output from the Doutk terminal after a delay time TAA from the rise of the clock CLK.

(Ii) In the case of a write operation, ADDk
/ Dink terminal, the lower m bits of address ADD and m bits of write data Dink are supplied to the ADDk terminal in a time-division manner, and the low-level chip select signal (C
S) and a low level (write level) write control signal (WE) are supplied to the chip select terminal and the write control terminal.

As shown in FIG. 3, in response to the rise of the clock CLK, the storage registers 1 and 7 store the address AD.
D, and the storage registers 10 and 11 receive the chip select signal (CS) and the write control signal (WE).

The decoder 3 decodes the address ADD stored in the storage registers 1 and 7, and selects a corresponding memory cell of the memory array 4.

In response to the rising edge of the clock (CLK), the storage register 2 takes in the write data Din supplied to the ADDk / Dink terminal in a time-sharing manner and transmits it to the write driver 8.

The write pulse generating circuit 9 outputs a write pulse in response to the control signal taken into the storage registers 10 and 11. In response to this write pulse,
The write driver 8 writes the write data Din to the selected memory cell.

The differences between the above-structured STRAM and the conventional I / O common type STRAM are as follows. (1) Conventionally, the address and the write data are supplied to different terminals, but in this embodiment, (a part of) the address ADD and the write data Din are supplied to the same terminal in a time-division manner. (2) Conventionally, since the address and the write data were supplied to different terminals, both the address and the write data were taken into the storage register at the rising edge of the clock CLK. In this embodiment, however, the address ADD is applied to the clock CLK. At the rising edge of the clock CLK, and the write data Din is captured at the falling edge of the clock CLK.

As described above, in this embodiment, the address AD
D and write data Din are connected to the same terminal by the clock signal 1
Unlike the conventional I / O common type synchronous SRAM, a redundant idle cycle is not required between a read operation and a write operation because a configuration in which supply is performed in a time-division manner in a cycle is employed. Performance is improved. In this embodiment, since the address ADD and the write data Din are multiplexed, a multi-bit I / O separate type synchronous SRAM can be constructed without increasing the number of terminals.

In the above embodiment, the storage register 11
Captures the write control signal (WE) in response to the rising edge of the clock CLK, but supplies the inverted clock (CLK) to the storage register 11 and changes the write control signal (WE) to the clock as shown in FIGS. It may be captured at the falling edge of CLK. The write data Din supplied to the ADDk / Dink terminal in a time sharing manner is stored in the storage register 2.
Is taken at the falling edge of the clock CLK, there is no problem if the write control signal (WE) is taken in at the falling edge of the clock CLK.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, the logic of each signal shown in the above embodiment may be changed. For example, at the rising edge of the clock CLK, the write data is fetched and the clock C
The address may be fetched at the fall of LK. In the above embodiment, the upper (n)
-M) supply the bit to the address terminal, and
Are supplied to the ADDk / Dink terminal,
The method of supplying the address is not limited to this. For example,
The lower (nm) bits of the address ADD are supplied to the address terminal ADDk, and the upper m bits of the address ADD are set to A.
It may be supplied to the DDk / Dink terminal. In the above embodiment, the number of bits n of the address ADD is equal to the data D.
The case where the number of bits of in and Dout is larger than m has been described.
When n and m are the same, the address dedicated terminal ADDk and the storage register 7 need not be arranged. The present invention is also applicable to an STRAM in which the number n of bits of the address ADD is smaller than the number m of bits of data. In this case, a write data terminal is provided in addition to the common terminal.

[0038]

As described above, according to the present invention, the synchronous S
Since the RAM is configured to supply the address and the write data to the same terminal in a time-sharing manner, the data width can be widened without increasing the number of pins. Also, I
There is no need for an idle cycle to avoid collision between the write data Din and the output data Dout as in the case of the / O common type synchronous SRAM, and the system performance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronous SRAM according to one embodiment of the present invention.

FIG. 2 is a timing chart showing an operation at the time of reading of the synchronous SRAM shown in FIG. 1;

FIG. 3 is a timing chart showing an operation at the time of writing in the synchronous SRAM shown in FIG. 1;

FIG. 4 is a timing chart showing an operation at the time of reading in a modification of the synchronous SRAM shown in FIG. 1;

FIG. 5 is a timing chart showing an operation at the time of writing in a modification of the synchronous SRAM shown in FIG. 4;

FIG. 6 is a block diagram of a conventional I / O separate type STRAM.

FIG. 7 is an operation timing chart of a conventional I / O separate type STRAM.

FIG. 8 is a diagram showing an example of a pin arrangement of a 128-k × 8-bit STRAM;

FIG. 9 is a block diagram of a conventional I / O separate type STRAM.

10 is a timing chart showing an operation at the time of reading of the synchronous SRAM shown in FIG. 9;

11 is a timing chart showing an operation at the time of writing in the synchronous SRAM shown in FIG. 9;

12 is a timing chart showing a read operation after writing in the synchronous SRAM shown in FIG. 9;

13 is a timing chart showing a write operation after reading of the synchronous SRAM shown in FIG. 9;

[Explanation of symbols]

1, 2, 6, 7, 10, 12, 14, 16, 19, 2
0, 22, 24: Storage register 3: Decoder 4, 13, 17: Memory array 5: Sense amplifier 8, 18: Write driver 9, 15, 23: Write pulse generation circuit 21: 3-state buffer 25: AND gate

Continuation of front page (56) References JP-A-2-44828 (JP, A) JP-A-3-124398 (JP, A) JP-A-54-134934 (JP, A) JP-A-53-32634 (JP) JP-A-59-14192 (JP, A) JP-A-54-128226 (JP, A)

Claims (2)

(57) [Claims] 1. An upper address or a lower address of an address
An address terminal for supplying the bit, the other bit of the address and the write data
A common terminal supplied in a time-division manner within the vehicle, a data output terminal for outputting read data, a control terminal for supplying a control signal, a clock terminal for supplying a clock signal, and a memory array for storing data. The common terminal, the address terminal, the clock terminal, and the memo
And a first edge of the clock signal.
The common terminal and the address terminal in response to the
Fetch the address and address the memory array
Means to sing,When the control signal indicates data reading,
Read data from the position specified by the addressing means.
Reading means for outputting the data to the data output terminal;  Connect to the common terminal, clock terminal and the memory array
And in response to a second edge of the clock signal,
Capture the write data from the common terminal and
Specified by the addressing means of Morialay
Means for writing the write data to a location, the synchronous static memory comprising: 2. A first edge of the clock signal rises.
Rising or falling, and the second
The feature is that the edge of the falling or rising edge
The synchronous static memory according to claim 1, wherein