JPS60150294A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve actual mounting density as a whole by receiving specific signals, generating the first and second selective signals inside the chip, and reducing the number of memory pins to miniaturize package. CONSTITUTION:The device is equipped with a delay circuit 12 which receives a line strobe signal RAS formed outside the IC inside an IC20 and uses this output as a row strobe signal CAS. This means that the device performs line selection when the signal RAS is at a VOL level and performs row selection when the signal CAs is at a low level by using as the signal CAS the signal delayed only for a period of t0 of this RAS signal, thus enabling omission of CAS signal input pins as compared with the conventional circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing system, and is mainly directed to a semiconductor memory device (hereinafter referred to as MO8I'C memory or simply memory) that is a semiconductor integrated circuit device.

The number of terminals in a semiconductor integrated circuit (IC) is limited by the size of the IC package, and conversely, the limitation on the number of terminals also limits the type and number of circuits that can be constructed within the package. In order to increase the packaging density of MO8IC memory,
Adopts an address multiplex method (a method that allows the number of address signal pins to be halved by processing address signals in a time-sharing manner), which allows the number of pins (terminals) on the package to be reduced. An outline of this method is shown and explained in FIG.

In the drawing, a portion 20 surrounded by a dashed line is a portion formed inside the IC. IC has pin P, ~
P1a is provided. Seven address signals A are provided to pins P1 to P7. -A, are applied respectively. Pin P1
The address signal applied to ~P7 is sent to the ICi section via the address signal line (ADDRESSBUS > txt), and one side is connected to the row address storage circuit 1 (COLUMN LAT
CH), and the other is column address storage circuit 2 (ROW LA
TCH) respectively.

3 in the figure is a row selection decoder (COLUMN DECODE).
R), which receives the address signal from the row address storage circuit 1 and outputs the output from the sense amplifier 7 (5ENSE'AM).
PS Ilo GATING). In the figure, reference numeral 4 denotes a column selection decoder (ROW DECODER) which receives the output of the column address storage circuit 2. This column selection decoder 4 and the sense amplifier 7 are connected to a memory cell array 8 (ST
ORAGE ARREY). The output of the row selection decoder 3 is sent to the memory cell 8 via the sense amplifier 7.
is applied to select a predetermined row. Further, a predetermined address of the memory cell 8 is selected by the output of the column selection decoder 4. Furthermore, writing to or reading from the memory cell 8 is performed via the sense amplifier 7 . 5 in the figure is a row circuit control clock generator (CAS).
CLOCK GENERATOR) and pin P1.
It is driven by an external drive signal CAS. A signal (ENABLE) generated from this clock generator 5 causes the row address storage circuit 1, the row selection decoder 3, and the output circuit 9 (OUT PUTLATcHA to be described later) to be activated.
ND BUFFER) is also activated.

Note that the disable signal (DISABLE) applied from the clock generator 5 to the output circuit 9 is for stopping the operation of the output circuit during writing. In addition, 6 in the figure is a column circuit control clock generator (RAS CLOCKGENERA).
TOR) and the external drive signal RA of pin P14.
Driven by S. A signal (ENABLE) generated from this clock generator 6 activates the column address storage circuit 2 and the column selection decoder 4. 11 in the figure is readout,
This is a write control circuit and is driven by an external drive signal WE.

When writing, the input circuit (DATA IN LATCH) is driven by setting WE to low level, and the pin P
, the data DIN from the outside is sent to the sense amplifier 7, and when reading, the operation of the input circuit 10 is stopped by setting WE- to high level, and the signal of the sense amplifier 7 is applied to the output circuit 9, and the pin P, . Karari. This is to read it as UT. Note that pin PIG has a negative power supply vBB + PH has a positive power supply vDD, p,...
A TTL (h transistor transistor logic) level power supply is connected to CC*, and a GND potential is connected to Pts.

The operation of the memory with the above configuration is as usual.

FIG. 2 is a timing chart for explaining the general operation of the above circuit.

First, the falling low level (
(2) With oL), the column selection clock generator 6 starts and drives the 1st column address storage circuit 2 and the column selection decoder 4. Therefore, one of the columns in the memory cell 8 is selected depending on the signal state of the address signal sections 0 to A (during periods t and xt).

Next, the row strobe signal CAS is generated sufficiently delayed from the column strobe signal RAS. When set to L level, the row circuit control clock generator 5 starts and the row address memory 19
Drives row selection decoder 3.

Therefore, the address signal A. - Any row in memory 7 flares and ray 8 is selected depending on the state of A6 (during period t to t3). This determines the address within the memory cell array. Therefore, when the signal WE applied to the 5th control circuit 11 is set to a low level, the input circuit 10 operates and input data D□i is applied to the determined address via the sense amplifier 7 to perform a write operation. is possible, and also reverse KW
When E is set to a high level, the operation of the input circuit IO stops,
The memory contents of the determined address are applied to the sense amplifier 7,
The stored contents can be read out from the output circuit 9 as OUT. Note that Ai (hereinafter referred to as address signals A0 to A0) in the timing chart shown in FIG.
6 will be collectively referred to as Ai. ) Do not mark ■ in the signal section.
Indicates a care portion (a portion that may be in any signal state).

The circuit shown in FIG. 1 is used, for example, as a circuit having a 16-bit memory capacity, but the number of pins required in such a case is 16, as is clear from the figure.

However, for larger-capacity memories, the number of pins will further increase, so it is desirable to share the pins that can be shared and reduce the number of pins as much as possible from the perspective of improving packaging density.

Therefore, an object of the present invention is to reduce the number of pins of a large-capacity memory, downsize the package, and improve the overall packaging density.

The gist of the present invention for achieving the above object is to transmit the start or determination of an address input signal to a memory device, in which a first selection signal selects a first address signal group, and the first A signal processing method that selects a second address signal group using a second selection signal delayed from a selection signal of It is characterized in that the signal is generated inside the chip.

The present invention will be specifically described below using examples and with reference to the drawings.

FIGS. 3A and 3B are a block diagram and timing chart showing an embodiment of the present invention.

According to one embodiment of the present invention, as shown in FIG. 3A, an IC
A delay circuit 12 for receiving an externally generated column strobe signal RAS is provided within the IC 20, and its output is used as the row strobe signal CAS. That is, the third
As shown in the timing chart shown in Figure B, column selection is performed when column strobe signals RA and S are at VoL level, and this R
t than the AS signal. A signal delayed by the period of CAS is used to select a row when the signal is at a low level.

According to such an embodiment, the input pin for the CAS signal (bin pH+ in FIG. 1) can be omitted compared to the conventional circuit.

4A and 4B are a circuit diagram and a timing chart thereof showing another embodiment of the present invention, which is an improvement of the above-mentioned FIGS. 3A and 3B. In other words, in order to use the mesori at the highest speed, it is desirable that the row address group come as quickly as possible after the column address group, and in such a case, as shown in FIGS. 3A and 3B above, Although it may be constant from the positive τ input to CAS (internally generated pulse) (period t in FIG. 3B), if a situation arises in which the row address group must be delayed for some reason, the above first embodiment is inconvenient. It is.

Therefore, the block diagram of FIG.
Column address strobe RAS, from ! A row address strobe CAS generation circuit 1 that uses two people to generate the bin P to which the near) response signal AO is applied and the special signal obtained.
3 is provided inside the IC to obtain a strobe signal CAS suitable for the above requirements. What is required at this time is that the above special signal is the address signal A. - It is necessary to use any one of 80 and have a level different from the address signal level.

In this way, as shown in the timing chart of FIG. 4B, for example, the address signal group A. By pre-installing a special signal (the part marked A51 in the figure) in the first address 80 of A6, the RAS signal can be changed to ■. L
Row selection is performed at the level (during the period t.-1), and then when the section A51 arrives after a predetermined period of delay, the row strobe signal CAS is generated by the CAS generation circuit 13.
can be generated and row selection can be performed (period t, ~t
.

). Therefore, by setting the arrival time of a special signal part (the part in the figure) piggybacked on any one of ○ to A6 (for example, A) to the above address signal group to an appropriate length, the row selection for a predetermined period is performed. Actions can be delayed.

This period can be freely set outside the IC. Therefore, according to this embodiment, in addition to the effects of those shown in FIGS. 3A and 3B, there is also the effect of increasing the degree of freedom in design.

Here, an example of the above-mentioned special signal and its detection circuit will be explained.

Figure 4C shows an example of a special signal, and Figure 4D
Figure 4 and Figure 4B show an example of a detection circuit for that signal.

FIG. 4C shows -VOL or VOR to V. V over 0
Positive pulse A rising to DD level, i1(+) and VOL
Or a negative pulse A, 12 (÷) that goes below the GND level and falls to the VBB level from VOH, and a signal A, 1 in a high impedance state.
3 (103 states are shown. In addition, the X and Y parts other than the part marked in the figure represent a group of address signals.

When determining the above-mentioned special signal, the following points must be kept in mind.

That is, since the address input Ai usually has many TTL (transistor, transistor, logic) levels, considering this case, the TTL output is at a high level (2). H and low level ■. L exists between V8s (GND-Ov) and VCC (approximately 5 V), and in addition to these, power supplies at VDD level (approximately 12 V) and VBB level (approximately -5 V) are used in the memory.

Therefore, the relationship between the above-mentioned respective potentials is as shown in the following equation (1).

vBB<vBB<vOL<vOl(<vCC<vDD
-(t) This is coupled with the fact that the level of the special signal needs to be distinguished from the normal address signal.

A signal that rises to the VDD level (Asix), or ■
It must be a signal that falls to the BB level (Asiz(1)) or a high impedance signal.

An example of a circuit for detecting such a special signal is shown in FIG. 4D or 4E.

Figure 4D shows a circuit that can detect special signals of A, i, or As12, and connects a resistor R and an insulated gate field effect transistor (hereinafter referred to as FET) between the VDD power supply and the BB power supply. )Q, are connected in series. In addition,
The signal applied to this input terminal is also applied to the address storage circuit 17. Then, add A5 to this circuit in Fig. 4C.
1. When a signal is applied, FETQ may be a P-channel FET, and when AB12 is applied, it may be an N-channel FET. According to this configuration, ASi
When a positive pulse of l is applied, FETQl turns off,
The output a51 becomes the DD level. Also ASl 2
The same applies when a negative pulse of is applied. This output a
51 (VDD level), one row strobe signal C'
The AS generating circuit can be driven.

FIG. 4E shows a circuit that can detect the state of As13, in which a resistor R6 and a FETQ are connected in series between the VDD power supply and the VBB power supply, and the FETQ
A resistor R8 is connected between the gate of y and the power supply VB2. According to this circuit, when the As iB flaw signal shown in FIG.
The voltage is raised to near B, FETQ is turned off, and its output a51 becomes the VDD level. Therefore, predetermined detection can be performed.

FIGS. 5A and 5B show still another example of the present invention.

FIG. 5A shows a further improvement of the circuit shown in FIG.
si is applied to the RAS and CAS generation circuit 14 provided inside the IC via one address pin (for example, address AO pin). This generation circuit 14 includes a negative pulse detection circuit as shown in FIG. 4D above,
A delay circuit is provided.

FIG. 5B is a timing chart for explaining the operation of the above circuit. As shown in the figure, when a negative pulse (for example, VBB level) of the signal As 4 applied to one address pin arrives, the RAS generation circuit 14 is driven to generate the column strobe signal RAS (period 1+). Next, a delay circuit provided in the signal generating circuit 14 generates a row strobe signal CAS delayed from the column strobe signal RAS (period 11). As a result, one period t1 to 1. If the column selection is between, and the period t
, ~t, row selection can be made. In this way, compared to the conventional method, two bins, RAS and positive τ1, can be omitted.

According to the embodiment shown in FIGS. 5A and 5B, the period from the occurrence of the column strobe RAS to the occurrence of the row strobe CAS (between t and t in FIG. 5B) is constant based on the design value of the delay circuit. becomes. Therefore, it is inconvenient when a situation arises in which the row address group must be delayed for some reason. The embodiments shown in FIGS. 6A and 6B are improved in this respect.

That is, FIG. 6A shows address signal A. and special signals (
+) is applied to the column strobe RAS via the bin P1 to which 0 is applied to the address signal, for example.
In addition to applying f to the generation circuit 15, other address signals A
, and a special signal (+), the second signal ABi'
the other address signal A.

It is assumed that the voltage is applied to the row strobe CAS generation circuit 16 via the bin P of . Then, the signal A5 i +
The special signals included in As i' utilize the positive pulse, negative pulse, or high impedance state shown in FIG. 4C, and RAS.

The CAS generating circuit is provided with means for detecting the above signal (for example, a circuit as shown in FIGS. 4D and 4E).

FIG. 6B is a timing chart for explaining the operation of the above circuit. In addition, in the following operation explanation, kB i *
A case will be described in which a negative pulse is used as a special signal of kB i'.

First, when the first signal kBi becomes a negative pulse, the RAS generation circuit to which this negative pulse is applied operates.

Generate column strobe RAS. A predetermined column selection is performed by this RAS (during period t to 1).

Next, when a negative pulse of the second signal Asi' is applied, CA
The S generation circuit operates and generates a row strobe CAS. A predetermined row selection is made by this CAS (period t, ~t
, between). According to an embodiment with such a configuration, the above-mentioned Nos. 5A and B
In addition to the effects of the embodiment shown in the figure, the second signal ABi'
By changing the arrival period of the negative pulse, the period from the generation of the column strobe RAS to the generation of the row strobe CAS can be arbitrarily delayed, which also has the effect of increasing the degree of freedom in design.

FIG. 7 is a circuit diagram showing a specific example in which the signal processing method shown in FIGS. 6A and 6B is applied to an actual memory.

In the figure, a portion 20 surrounded by a dashed line is the inside of the IC, and P1 to PI4 existing on the boundary thereof are external pins. Address signal A is applied to pins P1 to P7. In this embodiment, a signal k which is a combination of an address signal Ao and a RAS generation special signal is applied to pin P1.
Bi is applied to the pin P, and a signal ABi' which is a combination of an address signal A and a CAS occurrence special signal is applied to the pin P. The above signals A and i are connected to the RAS detection generation circuit 15 (RAS DETECTIO
N CIRCUIT), and its output RAS is applied to the column circuit control clock generator 6 (RAS CLOCK G
ENERATOR). On the other hand, the above signal As
i' is connected to the CAS detection generation circuit 16 (
CAS DETECTION CIRCUIT) and its output CAS is applied to the row circuit control clock generator 5 (
CAS CLOCK GENERA-TOR). Also, address signal A. ~A6 are applied to the row address storage circuit 1 (COLUMN LATCH) and the column address storage circuit 2 (ROW LATCH) via the address signal line (ADDRES8 BUS), respectively. The column address storage circuit 1 is driven by Tagata of the column circuit control clock generator 5, and
The output is sent to row selection decoder 3 (COLUMN DECODE
R) is applied.

The column address storage circuit 2 includes a column circuit control clock generator 6.
The row select decoder 4 (ROW DECODER) is driven by the output of the row select decoder 4 (ROW DECODER). Reference numeral 8 denotes a memory cell array (5TORAGEARRAY), from which memory cells at predetermined addresses are selected by the column selection decoder 4 and row selection decoder 3. moreover,
11 is a read/write control circuit, and a control signal W
A predetermined signal is generated based on E and the output of the column circuit control clock generator 5. 10 is a write circuit (DATAIN
LATCH), and the sense amplifier 7 (SE
This is to write data to a predetermined memory cell in the memory cell array 8 via the NSE AMPS Ilo GATING). 9 is the output circuit (OUTPUTLAT
HAND BUFFER) is driven by the output of the row circuit control clock generator 5, and is driven by the sense amplifier 7.
The data stored in a predetermined memory cell is output via the . U.T.
It can be read as . In the above configuration, the write operation is performed by setting the control signal WE to a low level to give a start signal (STROBE) from the control circuit 11 to the input circuit, and inputting the input data DIN to the memory cell array 8 through the sense amplifier 7. This is done by applying the voltage to the determined address (at this time, the output circuit 9
is the disable signal (DISABLE) from the clock generator 5
The read operation is performed by setting the control signal WE to a high level and extracting the information stored in the memory cell to the output DOUT via the sense amplifier 7 and the output circuit 9. At this time,
The input circuit 10 is not operated by a signal from the control circuit 11. In addition, the pin PI (l has a negative power supply ■B
B, positive 11 source ■DD for pin pH, TT for pin P1□
L level power supply■. 0. GND is applied to each pin PUS.

FIG. 8 is a timing chart for explaining the operation of the memory. The operation will be explained below with reference to the same figure. In addition,
The following description of the operation deals with the case of a negative pulse as a special signal combined with address signals Ao and A1.

First, address signal A. When the signal A81 applied to the application pin P becomes a negative pulse, the RAS detection and generation circuit 15 becomes operational and generates the column strobe signal RAS (period 1+) (period tz). This RAS causes the clock generator 6 to operate, thereby activating the column address storage circuit 2 and column selection decoder 4, and selecting a predetermined column in the memory cell array 8 (during periods t to t). Next, address signal A
, when the signal Asi' applied to the application pin P becomes a negative pulse', the CA8 detection generation circuit 16 does not operate for a period t,
), generates a row strobe signal CAS (period it).

This CAS operates the clock generator 5, which activates the row address storage circuit 1 and the row selection decoder 3, and selects a memory cell in a predetermined row in the memory cell array 8 (during the period t4 to t). ). Therefore, an address within the memory cell array is specified. Furthermore, if the write control signal WE is set to a low level, the input circuit 10 operates and the input signal DIN<'+1 jl or "o
"> can be written to the determined address via the sense amplifier 7 (during the period 14 to t). Furthermore, if the control signal WE is kept at a high level, the output circuit 9 will operate. , the data at the designated address obtained via the sense amplifier 7 can be read out (periods t, ~t7).
).

As described above, according to the present invention, the number of external pins of an IC can be reduced (
This makes it possible to reduce the size of the package and improve the packaging density even for large-capacity memories.

The present invention is applicable not only to memories but also to ICs having multiple external pins.
widely available.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional IC memory,
FIG. 2 is a timing chart thereof, FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A are block diagrams showing one embodiment of the present invention, and FIG. 3B. Figures 4B, 5B, and 6B are timing charts of the above embodiment, Figure 4C is a waveform diagram showing an example of a special signal used in the present invention, and Figures 4D and 4E are for detecting the above signal. FIG. 7 is a block diagram showing an example of the application of the present invention, and FIG. 8 is a timing chart thereof. 1.2... Address storage circuit, 3.4... Decoder, 5.6... Clock generator, 7... Sense amplifier, 8... Memory cell array, 9... Output circuit, 10
...Input circuit, 11...Control circuit, 12...Delay circuit, 13...CAS generation circuit, 14-16...Strobe signal detection generation circuit, 17...Address buffer, 20...・Inside the IC, Q, , Q2...FET,
R, ~R8...Resistance. Agent Patent Attorney - Akio Takahashi, Figure 1 Figure 2 Figure M 1 / Figure 7 M 670- Figure 8

Claims (1)

[Scope of Claims] 1. A first address signal group and a second address signal group are supplied multiple times, and are selected from a memory cell group according to the first address signal group, and the first address signal group and the second address signal group are 2
In a semiconductor memory device in which data is written to or read from a memory cell selected according to a group of address signals, a timing signal that defines the timing for reading the first group of address signals, and a second nutless signal The internal timing signal required in the operation of selecting a memory cell according to a second group of address signals from the group of memory cells is formed upon a change in at least one address signal of the group. Characteristic semiconductor memory device.