JP2019106056A - Memory system and memory device - Google Patents

Abstract

To shorten an analysis operation time in abnormality occurrence.SOLUTION: A memory system includes a host device 3, and a memory device 2 including a memory 11 and a control circuit 12 and having first and second control modes. When receiving a writing request or a reading request, the control circuit 12 responds to the received writing request or reading request in the first control mode, and does not respond to the received writing request or reading request in the second control mode, when receiving an internal information storage request or internal information acquisition request, the control circuit shifts from the first control mode to the second control mode, executes a storage operation or acquisition operation of the internal information, and shifts from the second control mode to the first control mode without re-starting the memory device 2 after the end of the storage operation or acquisition operation.SELECTED DRAWING: Figure 10

Description

  Embodiments of the present invention relate to memory systems and memory devices.

  A memory system conforming to the universal flash storage (UFS) standard is known as a memory system consisting of a host device and a memory device based on a client server model.

JP, 2011-65313, A Patent No. 5300496 gazette Patent No. 5458568 gazette

  Provided are a memory system and a memory device capable of shortening an analysis operation period when an abnormality occurs.

  A memory system according to an embodiment includes: a host device capable of transmitting an internal information storage request and an internal information acquisition request; a memory connected to the host device and including a memory cell array including a plurality of memory cells; And a memory device having a first control mode and a second control mode. When the control circuit receives a write request or read request from the host device, the control circuit responds to the received write request or read request in the first control mode, and receives the received write request in the second control mode. When the internal information storage request or the internal information acquisition request is received from the host device without responding to the read request, the control mode is shifted from the first control mode to the second control mode and the internal information storage operation or acquisition operation is executed. After the storage operation or the acquisition operation is finished, the second control mode is shifted to the first control mode without restarting the memory device.

FIG. 1 is a block diagram of a memory system according to the first embodiment. FIG. 2 is a block diagram of a memory provided in the memory system according to the first embodiment. FIG. 3 is a block diagram of a memory cell array provided in the memory system according to the first embodiment. FIG. 4 is a circuit diagram of a memory cell array provided in the memory system according to the first embodiment. FIG. 5 is a cross-sectional view of a memory cell array provided in the memory system according to the first embodiment. FIG. 6 is a diagram showing a state in which a memory device provided in the memory system according to the first embodiment is mounted. FIG. 7 is a flowchart of the normal operation of the host device included in the memory system according to the first embodiment. FIG. 8 is a flowchart of the write operation in the memory system according to the first embodiment. FIG. 9 is a flowchart of the read operation in the memory system according to the first embodiment. FIG. 10 is a flowchart of the internal information storing operation and the internal information acquiring operation in the memory system according to the first embodiment. FIG. 11 is a flowchart showing a specific example of access between a host device and a memory device in the memory system according to the first embodiment. FIG. 12 is a flowchart showing a specific example of access between a host device and a memory device in the memory system according to the first embodiment. FIG. 13 is a diagram showing an example of a memory system conforming to the embedded multi media card (e-MMC) standard. FIG. 14 is a diagram showing an example of a memory system compliant with the UFS standard. FIG. 15 is a flowchart showing a specific example of access between a host device and a memory device in the memory system according to the second embodiment. FIG. 16 is a flowchart showing a specific example of access between a host device and a memory device in a memory system according to the second embodiment. FIG. 17 is a flowchart illustrating a specific example of access between a host device and a memory device in a memory system according to the second embodiment. FIG. 18 is a block diagram of a memory system according to the third embodiment.

  Embodiments will be described below with reference to the drawings. In the description, components having substantially the same function and configuration are denoted by the same reference numerals. Further, each embodiment shown below is an example of an apparatus and a method for embodying the technical idea of this embodiment, and the technical idea of the embodiment includes the material, shape, and structure of the component. , Arrangement, etc. are not specified to the following. The technical ideas of the embodiments can be variously modified within the scope of the claims.

1. First Embodiment A memory system according to the first embodiment will be described. Hereinafter, a memory system including a host device and a memory device conforming to the UFS standard will be described.

1.1 Configuration 1.1.1 Overall Configuration of Memory System First, the overall configuration of the memory system will be described with reference to FIG. FIG. 1 shows the hardware configuration of a memory device. In FIG. 1, a part of the connection between the blocks is indicated by an arrow, but the connection between the blocks is not limited to this.

  As shown in FIG. 1, the memory system 1 includes a memory device 2 and a host device 3. The memory device 2 is configured to communicate with the host device 3 based on the client server model. The memory device 2 operates as a target, and the host device 3 operates as an initiator. As a more specific example, the memory device 2 is a UFS memory device, and the host device 3 is a host device that supports the UFS memory device. The host device 3 is, for example, a SoC (system on chip) device, and may be a device mounted on a smartphone, a digital camera, or the like.

  The memory device 2 includes a non-volatile semiconductor memory 11 (hereinafter referred to as “memory”) and a controller 12 for controlling the memory 11.

  The memory 11 performs the write operation and the read operation of data in a specific write unit composed of a plurality of bits. Furthermore, the memory 11 erases data in an erase unit composed of a plurality of write units. For example, the memory 11 is composed of one or more NAND flash memories. When the memory 11 is a NAND flash memory, the memory 11 performs a write operation and a read operation in page units. The following describes the case where the memory 11 is a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked above a semiconductor substrate. The memory is not limited to the three-dimensional stacked NAND flash memory, but may be a planar NAND flash memory in which memory cell transistors are two-dimensionally arranged on a semiconductor substrate, and other non-volatile memories Also good. Details of the memory 11 will be described later.

  The memory device 2 includes an I / O 21, a core logic unit 22, and an I / O 23. The I / O 21 includes a hardware configuration for connecting the memory device 2 to the host device 3. The memory device 2 is connected to the host device 3 via the host bus. When the memory system 1 conforms to the UFS standard, the host bus corresponds to the serial interface. Signals transmitted and received between the memory device 2 and the host device 3 include RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c. RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c are communicated between the host device 3 and the I / O 21 via the host bus. RESET is a hardware reset signal. REF_CLK is a reference clock signal. DOUT and DOUT_c form a differential signal pair and are signals transmitted from the host device 3 to the memory device 2. DIN and DIN_c form a differential signal pair and are signals transmitted from the memory device 2 to the host device 3.

  The core logic unit 22 is a main part of the controller 12 excluding the I / O 21 and the I / O 23. The I / O 23 includes a hardware configuration for the controller 12 to connect to the memory 11.

  The core logic unit 22 includes a host interface 31, a buffer 32, a data bus 33, a memory interface 34, a buffer 35, an ECC circuit 36, a control bus 41, a CPU (central processing unit) 42, a ROM (read only memory) 43, and a RAM ( random access memory 44 and a register 45 are included.

  The I / O 21 is connected to the host interface 31. The host interface 31 performs processing necessary for the memory device 2 and the host device 3 to communicate. More specifically, the host interface 31 is responsible for communication between the memory device 2 and the host device 3 in accordance with the communication protocol with which the memory device 2 and the host device 3 are both compliant. When the memory device 2 is a UFS memory device, for example, the host interface 31 is a UFS interface. The UFS interface conforms to the M-PHY standard for the physical layer and the UniPro standard for the link layer.

  The host interface 31 is connected to the buffer 32. The buffer 32 receives data transmitted from the host device 3 to the memory device 2 via the host interface 31 and temporarily holds the data. The buffer 32 also temporarily holds data transmitted from the memory device 2 to the host device 3 via the host interface 31. The buffer 32 is connected to the data bus 33.

  The I / O 23 is connected to the memory interface 34. Memory interface 34 performs the processing necessary for controller 12 to communicate with memory 11. More specifically, the memory interface 34 transmits an instruction (control signal) from the core logic unit 22 in such a form that the memory 11 can recognize. Furthermore, the memory interface 34 transmits and receives the signal DQ to and from the memory 11, and receives the ready / busy signal R / Bn from the memory 11. The signal DQ includes, for example, data, an address, and a command. The signal R / Bn is a signal indicating that the memory 11 is in a busy state. When the memory 11 is a NAND flash memory, the memory interface 34 is a NAND flash interface.

  The memory interface 34 is connected to the buffer 35. The buffer 35 receives data transmitted from the memory 11 to the controller 12 via the memory interface 34 and temporarily holds the data. The buffer 35 also temporarily holds data to be transmitted from the controller 12 to the memory 11 via the memory interface 34. The buffer 35 is connected to the data bus 33. The buffers 32 and 35 may be one buffer. The memory interface 34 and the buffer 35 are connected to an ECC (error correcting code) circuit 36. The ECC circuit 36 receives the write data from the host device 3 through the data bus 33, adds an error correction code (hereinafter referred to as "parity") to the write data, and buffers the write data to which parity is added. Supply to 35 Further, the ECC circuit 36 receives the data supplied from the memory 11 through the buffer 35, performs error correction using the parity given to the data, and supplies the data bus 33 with the error-corrected data. .

  The CPU 42, the ROM 43, the RAM 44, and the register 45 are connected to the control bus 41. The CPU 42, the ROM 43, the RAM 44, and the register 45 communicate with each other via the control bus 41.

  The CPU 42 manages the entire operation of the memory device 2. The CPU 42 executes predetermined processing (write operation, read operation, erase operation, etc.) in accordance with a control program (instruction) stored in the ROM 43. The CPU 42 executes, for example, predetermined processing on the memory 11 in accordance with a command received from the host device 3.

  When the CPU 42 receives a read request (instruction) including a command and a logical address from the host device 3, data stored in the memory 11 in which the logical address and the physical address are associated (hereinafter referred to as “logical object conversion data” And the logical-physical conversion data corresponding to the logical address to be read out are read out, and the logical address is converted to a physical address. The physical address identifies a portion of the memory space of the memory 11. When the CPU 42 receives a write request including a command, write data, and a logical address from the host device 3, the CPU 42 newly allocates a physical address corresponding to the logical address.

  The ROM 43 stores control programs and the like executed by the CPU 42.

  The RAM 44 is used as a work area for the CPU 42, and temporarily stores variables and the like necessary for the work of the CPU 42.

  The register 45 holds various values necessary for the operation of the memory device 2. Also, the register 45 holds various values necessary for the host device 3 to control the memory device 2.

  Further, a host interface 31, a buffer 32, a memory interface 34, and a buffer 35 are connected to the control bus 41. The CPU 42 controls the host interface 31, the buffer 32, the memory interface 34, and the buffer 35 based on an instruction from the control program and the host device 3. Furthermore, the controller 12 may be provided with an analog circuit 51.

1.1.2 Configuration of Memory Next, the configuration of the memory 11 will be described with reference to FIG. In FIG. 2, a part of the connection between the blocks is indicated by an arrow, but the connection between the blocks is not limited to this.

  As shown in FIG. 2, the memory 11 includes an input / output circuit 100, a logic control circuit 101, a status register 102, an address register 103, a command register 104, a sequencer 105, a ready / busy circuit 106, a voltage generation circuit 107, and a memory cell array 108. , A row decoder 109, a sense amplifier 110, a data register 111, and a column decoder 112.

  The input / output circuit 100 controls the input / output of the signal DQ with the controller 12. More specifically, input / output circuit 100 transmits data DAT (write data) received from controller 12 to data register 111, transmits address ADD to address register 103, and transmits command CMD to command register 104. Do. In addition, the input / output circuit 100 transmits the status information STS received from the status register 102, the data DAT (read data) received from the data register 111, and the address ADD received from the address register 103 to the controller 12.

  The logic control circuit 101 receives various control signals from the controller 12. Then, the logic control circuit 101 controls the input / output circuit 100 and the sequencer 105 in accordance with the received control signal.

  The status register 102 temporarily holds status information STS in, for example, a write operation, a read operation, and an erase operation, and notifies the controller 12 whether the operation has ended normally.

  The address register 103 temporarily holds the address ADD received from the controller 12 via the input / output circuit 100. Then, the address register 103 transfers the row address RA to the row decoder 109 and transfers the column address CA to the column decoder 112.

  The command register 104 temporarily stores the command CMD received from the controller 12 via the input / output circuit 100 and transfers it to the sequencer 105.

  The sequencer 105 controls the overall operation of the memory 11. More specifically, the sequencer 105 responds to the command CMD held by the command register 104, for example, the status register 102, the ready / busy circuit 106, the voltage generation circuit 107, the row decoder 109, the sense amplifier 110, the data register 111, And controls the column decoder 112 and the like to execute a write operation, a read operation, an erase operation, and the like.

    The ready / busy circuit 106 transmits a ready / busy signal R / Bn to the controller 12 in accordance with the operation status of the sequencer 105.

  The voltage generation circuit 107 generates voltages necessary for the write operation, the read operation, and the erase operation according to the control of the sequencer 105, and generates the generated voltages as, for example, the memory cell array 108, the row decoder 109, the sense amplifier 110, and the like. Supply to The row decoder 109 and the sense amplifier 110 apply the voltage supplied from the voltage generation circuit 107 to the memory cell transistors in the memory cell array 108.

  Memory cell array 108 includes a plurality of non-volatile memory cell transistors (hereinafter also referred to as “memory cells”) associated with rows and columns. Memory cell array 108 roughly includes a user area 130 and a system area 131 as a space area of memory.

  The user area 130 is an area used for writing and reading data received from the host device 3.

  The system area 131 is, for example, information related to the basis of the memory device 2 such as a control program in the memory 11, logical-physical conversion data, or various setting parameters such as an applied voltage in a write operation (hereinafter referred to as "system information") Is the area to be saved. The system area 131 is an area to which the host device 3 can not access in a write operation and a read operation of data received from the host device 3. The system area 131 includes a plurality of memory groups MG. The sequencer 105 normally selects one memory group MG and stores system information. When updating of one memory group MG proceeds to a certain extent, the sequencer 105 copies system information to another memory group MG and erases the system information of the original memory group MG in order to prevent destruction due to exhaustion.

  In addition, in the memory group MG in which system information is not stored, when there is a request from the host device 3, information indicating the internal state of the memory device 2 (hereinafter referred to as "internal information") is stored. As internal information, for example, an error log when an abnormality occurs in the memory device 2, information of each register (102, 103, 104, and 111) and the sequencer 105, or which address data is valid (for example, writing) In operation, information necessary for failure analysis, such as information indicating how far writing is completed, is included. The error log includes, for example, an abnormality occurrence factor, an abnormality occurrence location, time information at the time of abnormality occurrence, and the like.

  The row decoder 109 decodes the row address RA. The row decoder 109 applies a necessary voltage to the memory cell array 108 based on the decoding result.

  The sense amplifier 110 senses the data read from the memory cell array 108 in the read operation. Then, the sense amplifier 110 transmits the read data to the data register 111. Further, the sense amplifier 110 transmits write data to the memory cell array 108 in the write operation.

  The data register 111 includes a plurality of latch circuits. The latch circuit temporarily holds write data or read data. For example, in a write operation, the data register 111 temporarily holds write data received from the input / output circuit 100 and transmits the write data to the sense amplifier 110. Further, for example, in the read operation, the data register 111 temporarily holds read data received from the sense amplifier 110 and transmits the read data to the input / output circuit 100.

  The column decoder 112 decodes the column address CA, for example, in a write operation, a read operation, and an erase operation, and selects a latch circuit in the data register 111 according to the decoding result.

1.1.3 Configuration of Memory Cell Array Next, the configuration of the memory cell array 108 will be described using FIGS. 3 and 4. FIG.

  FIG. 3 is a block diagram of the memory cell array 108. As shown in FIG. As shown in FIG. 3, the memory cell array 108 includes a plurality of blocks BLK (BLK0, BLK1,...) Including memory cell transistors. Each block BLK includes a plurality of string units SU (SU0, SU1, SU2, SU3,...). Each string unit SU includes a plurality of NAND strings SR. The number of blocks BLK in the memory cell array 108 and the number of string units SU in each block BLK are arbitrary.

  Assignment of each block BLK and each string unit SU to the user area 130 and the system area 131 is arbitrary. For example, any block BLK may be allocated to the user area 130 and another block BLK may be allocated to the system area 131. Also, for example, an arbitrary string unit SU of each block BLK may be assigned to each memory group MG of the system area 131.

  Next, the circuit configuration of the memory cell array 108 will be described. The example of FIG. 4 shows the block BLK0, but the configuration of the other blocks BLK is the same.

  As shown in FIG. 4, the block BLK0 includes, for example, four string units SU (SU0 to SU3). Each string unit SU includes a plurality of NAND strings SR. Each of the NAND strings SR includes, for example, eight memory cell transistors MT0 to MT7, and select transistors ST1 and ST2. Hereinafter, when the memory cell transistors MT0 to MT7 are not limited, they are referred to as memory cell transistors MT. The memory cell transistor MT includes a control gate and a charge storage layer, and holds data in a non-volatile manner. The memory cell transistor MT changes its threshold voltage in accordance with the number of electrons stored in the charge storage layer, and stores information according to the difference in threshold voltage. The memory cell transistor MT may be a MONOS type using an insulating film as a charge storage layer, or may be an FG type using a conductive layer as a charge storage layer. Hereinafter, in the present embodiment, the MONOS type will be described as an example. Also, the number of memory cell transistors MT is not limited to eight, and may be 16, 32, 64, 128, etc., and the number is not limited. Furthermore, the number of select transistors ST1 and ST2 is arbitrary, and may be one or more.

  The memory cell transistor MT is connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. More specifically, the memory cell transistors MT0 to MT7 have their current paths connected in series. The drain of the memory cell transistor MT7 is connected to the source of the select transistor ST1, and the source of the memory cell transistor MT0 is connected to the drain of the select transistor ST2.

  The gates of the select transistors ST1 in each of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. Similarly, the gates of the select transistors ST2 in each of the string units SU0 to SU3 are connected to select gate lines SGS0 to SGS3, respectively. Hereinafter, when the selection gate lines SGD0 to SGD3 are not limited, they are referred to as a selection gate line SGD. When the selection gate lines SGS0 to SGS3 are not limited, they are referred to as a selection gate line SGS. The select gate lines SGS0 to SGS3 of each string unit SU may be connected in common.

  Control gates of the memory cell transistors MT0 to MT7 in the block BLK are commonly connected to word lines WL0 to WL7, respectively. Hereinafter, when the word lines WL0 to WL7 are not limited, they are referred to as word lines WL.

  The drains of the select transistors ST1 of the NAND strings SR in the string unit SU are connected to different bit lines BL0 to BL (N-1) (N is an integer of 2 or more). Hereinafter, when not limiting the bit lines BL0 to BL (N-1), they are referred to as the bit line BL. Each bit line BL commonly connects one NAND string SR in each string unit SU among a plurality of blocks BLK. Furthermore, the sources of the plurality of select transistors ST2 are commonly connected to the source line SL. That is, the string unit SU is a group of NAND strings SR connected to different bit lines BL and connected to the same select gate line SGD and SGS. The block BLK is a set of a plurality of string units SU sharing the word line WL. The memory cell array 18 is an aggregate of a plurality of blocks BLK sharing the bit line BL.

  The write operation and the read operation are collectively performed on the memory cell transistors MT connected to any word line WL in any string unit SU, and a collection of data at this time is called a "page". .

  When the memory 11 is a NAND flash memory, the memory cell transistor MT can take different states of two or more threshold voltages, that is, the memory 11 so that one memory cell transistor MT can store multiple values (multiple bits). May be configured. In the case of such a memory cell transistor MT capable of storing multiple values, a plurality of pages are assigned to one word line WL.

1.1.4 Cross-sectional configuration of memory cell array
Next, the cross-sectional configuration of the memory cell array 108 will be described with reference to FIG. The example of FIG. 5 shows the cross sections of the string units SU0 and SU1, and the configurations of the string units SU2 and SU3 are similar. In FIG. 5, the interlayer insulating film is omitted.

  As shown in FIG. 5, a plurality of source line contacts LI extending in a second direction D2 parallel to the semiconductor substrate 200 and perpendicular to the first direction D1 are provided along the first direction D1 parallel to the semiconductor substrate 200. There is. One string unit SU is disposed between the two source line contacts LI. The source line contact LI connects the semiconductor substrate 200 and a source line SL (not shown) provided above the NAND string SR. The arrangement of source line contact LI and NAND string SR can be set arbitrarily. For example, a plurality of string units SU may be provided between two source line contacts LI. Furthermore, in the example of FIG. 5, the case where a plurality of NAND strings SR are arranged in one column along the second direction D2 in one string unit SU is shown to simplify the description. The arrangement of NAND strings SR in one string unit SU can be arbitrarily set. For example, two rows may be arranged in parallel along the second direction D2, or may be arranged in a four-row staggered arrangement.

In each string unit SU, the NAND string SR is formed along a third direction D3 perpendicular to the semiconductor substrate 200. More specifically, an n-type well 201 is provided in the surface region of the semiconductor substrate 200. In the surface region of the n-type well 201, a p-type well 202 is provided. In addition, an n ⁺ -type diffusion layer 203 is provided in part of the surface region of the p-type well 202. The select gate line SGS, the word lines WL0 to WL7 connected to the memory cell transistors MT0 to MT7, and the ten wiring layers 204 functioning as the select gate line SGD are illustrated above the p-type well 202, respectively. It is sequentially laminated via an interlayer insulating film.

  Then, a pillar-shaped semiconductor layer 205 which penetrates the ten wiring layers 204 and reaches the p-type well 202 is formed. A tunnel insulating film 206, a charge storage layer 207, and a block insulating film 208 are sequentially formed on the side surface of the semiconductor layer 205. For example, polycrystalline silicon is used for the semiconductor layer 205. For example, a silicon oxide film is used for the tunnel insulating film 206 and the block insulating film 208. For example, a silicon nitride film is used for the charge storage layer 207. The semiconductor layer 205 functions as a current path of the NAND string SR, and is a region where the channel of each transistor is formed. The upper end of the semiconductor layer 205 is connected to the wiring layer 210 extending in the first direction D1 via the contact plug 209. The wiring layer 210 functions as a bit line BL. In the example of FIG. 5, one wiring layer 204 functioning as the selection gate lines SGD and SGS is provided, but a plurality of wiring layers may be provided.

The source line contact LI has a line shape along the second direction D2. For example, polycrystalline silicon is used for the source line contact LI. The bottom surface of the source line contact LI is connected to the n ⁺ -type diffusion layer 203, and the top surface is connected to a wiring layer (not shown) functioning as a source line SL.

1.1.5 Memory Device Mounting Form Next, a memory device mounting form will be described with reference to FIG. The memory device 2 may be, for example, an embedded type mounted on a printed circuit board by solder, or may be a removable type removable from a card slot provided in the host device 3. FIG. 5 shows an example of the memory device 2 in sealed form.

  As shown in FIG. 6, a plurality of chip-like memories 11 are stacked on a printed circuit board 301. Each memory 11 is connected to a wiring pattern (not shown) on the printed circuit board 301 by a wire 302. The chip controller 12 is also placed on the printed circuit board 301 and connected to the wiring pattern by the wires 302. An external terminal (for example, a BGA (ball grid array)) (not shown) is provided on the back surface of the printed circuit board 301. Signals (RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c shown in FIG. 1 are assigned to the external terminals, and signals are communicated between the memory device 2 and the host device 3 through the external terminals. The printed circuit board 301, the memory 11, the controller 12, and the wire 302 are sealed by, for example, a resin package 303.

1.2 Access of Host Device and Memory Device Next, access between the host device 3 and the memory device 2 will be described.

1.2.1 Flow of Normal Operation Request in Host Device First, a flow of a case where the host device 3 requests the memory device 2 for a write operation or a read operation (hereinafter referred to as “normal operation request”), This will be described using 7. The host device 3 in the present embodiment transmits a request to the memory device 2 and has a retry function capable of repeatedly transmitting the same request multiple times if there is no response to the request from the memory device 2.

  As shown in FIG. 7, first, the host device 3 transmits a normal operation request to the memory device 2 (step S1). More specifically, in the case of the write request, the host device 3 transmits the normal operation request to the memory device 2. Send a write command (write command), a logical address, and write data. In the case of a read request, the host device 3 transmits a read command (write command) and a logical address to the memory device 2.

  The host device 3 ends the normal operation request when the memory device 2 responds to the normal operation request within the preset time (step S2_Yes). That is, the process associated with the normal operation request is completed.

  On the other hand, when there is no response within the set time (step S2_No), the host device 3 confirms whether the number of times of making a normal operation request to the memory device 2 has reached a preset number (step S3).

  If the number of requests has not reached the set number (step S3_No), the host device 3 retransmits the request for the same operation to the memory device 2 (step S4).

  On the other hand, when the number of requests has reached the set number, the host device 3 determines that a timeout has occurred (step S5), and ends the normal operation request.

1.2.2 Overall Flow at the Time of Write Request Next, the overall flow at the time of write request will be described using FIG.

  As shown in FIG. 8, first, the host device 3 transmits a write request to the controller 12 of the memory device 2 (step S10).

  The controller 12 transmits a write command to the memory 11 based on the write request (step S11). More specifically, the CPU 42 assigns the logical address received from the host device 3 to an unused page in the user area 130 of the memory 11, that is, the physical address of a page to which new data is not written after data is erased. The CPU 42 also issues a write command that can be recognized by the memory 11. The ECC circuit 36 applies parity to the write data received from the host device 3. Then, the write data to which the write command, the physical address, and the parity are given is sent to the memory 11 as a write command.

  When the memory 11 receives the write command, the memory 11 executes the write operation (step S12). At this time, data is written to the user area 130.

  When the write operation is completed, the memory 11 transmits, to the controller 12, status information STS indicating that the write operation is normally completed (step S13). More specifically, for example, after confirming that the write operation has been completed and the signal R / Bn has returned from the busy state to the ready state, the controller 12 transmits a status information read command to the memory 11, The status information STS may be read from

  When the controller 12 receives the status information STS indicating that the write operation has ended normally from the memory 11, the controller 12 transmits a response to the write request (hereinafter referred to as "write response") to the host device 3 (step S14).

  When the host device 3 confirms the write response from the controller 12, it ends the write request (step S15). When the write response can not be confirmed, the host device 3 transmits the write request again as described with reference to FIG.

1.2.3 Overall Flow for Read Request Next, the overall flow for read request will be described using FIG.

  As shown in FIG. 9, first, the host device 3 sends a read request to the controller 12 of the memory device 2 (step S20).

  The controller 12 transmits a read command to the memory 11 based on the read request (step S21). More specifically, the CPU 42 converts the logical address received from the host device 3 into a physical address based on the logical-physical conversion data. The CPU 42 also issues a read command that can be recognized by the memory 11. Then, the read command and the physical address are transmitted to the memory 11 as a read command.

  When the memory 11 receives the read command, the memory 11 executes the read operation (step S22). At this time, data is read from the user area 130.

  When the read operation is completed, the memory 11 transmits read data to the controller 12 (step S23).

  After performing ECC processing of the read data received from the memory 11, the controller 12 transmits the error-corrected read data to the host device 3 as a response to the read request (hereinafter, referred to as "read response") (step S24).

  When the host device 3 acquires the read data from the controller 12, the host device 3 ends the read request (step S25). When the host device 3 can not confirm the read response, the host device 3 transmits the read request again as described with reference to FIG.

1.2.4 Control Mode of Memory Device Next, a control mode of the memory device 2 will be described. The memory device 2 of the present embodiment has two control modes of a normal mode and an analysis mode as a control mode of the memory device 2. The control mode of the memory device 2 is managed by the controller 12.

  The normal mode is a control mode selected when an operation (a write operation, a read operation, an erase operation, etc.) for accessing the user area 130 of the memory cell array 108 is performed. For example, when the host device 3 makes a normal operation request in the normal mode, the memory device 2 accesses the user area 130 and performs an operation according to the request.

  The analysis mode is a mode selected when performing an operation of accessing the system area 131 of the memory cell array 108. While in the analysis mode, the memory device 2 does not perform an operation corresponding to the request even when receiving the request from the host device 3, and does not respond to the host device 3.

  For example, when an abnormality such as a timeout occurs in the memory system 1, the host device 3 requests the memory device 2 to save and acquire internal information at the time of abnormality occurrence in order to analyze the cause. When the memory device 2 receives a request for storage or acquisition of internal information from the host device 3, the memory device 2 shifts to the analysis mode and accesses the system area 131 of the memory 11. Then, after the operation of accessing the system area 131 is completed, the memory device 2 returns to the normal mode without requiring the restart process and the initialization process.

1.2.5 Overall Flow at the Time of Internal Information Storage Request and Internal Information Acquisition Request Next, the overall flow at the time of internal information storage request and internal information acquisition request will be described using FIG.

  First, the entire flow in the case where there is an internal information storage request from the host device 3 will be described. As shown in FIG. 10, the host device 3 transmits an internal information storage request to the controller 12 (step S30). For example, the internal information storage request includes a storage instruction (storage command) and a logical address, but does not include data.

  The controller 12 shifts the control mode of the memory device 2 from the normal mode to the analysis mode, and does not respond to the normal operation request from the host device 3 (step S31).

  The controller 12 transmits an internal information storage instruction to the memory 11 (step S32). More specifically, the CPU 42 sets the logical address received from the host device 3 to an unused memory group MG of the system area 131, that is, a physical address of any one of a plurality of memory groups MG in which system information is not stored. assign. Further, the CPU 42 issues a save command that can be recognized by the memory 11. Then, the CPU 42 transmits the storage command and the physical address to the memory 11 as an internal information storage instruction via the memory interface 34. At this time, the controller 12 may also transmit, for example, the information in the register 45 and store the information in the memory 11 as internal information.

  When the memory 11 receives the internal information storage instruction, the memory 11 executes an internal information storage operation (writing operation) (step S33). At this time, internal information is written to the unused memory group MG of the system area 131 corresponding to the received physical address.

  When the storage of the internal information is completed, the memory 11 transmits, to the controller 12, status information STS notifying that the storage of the internal information has ended normally (step S34).

  When the controller 12 receives the status information STS indicating that the storage of the internal information has ended normally from the memory 11, the controller 12 transmits to the host device 3 a response to the internal information storage request (hereinafter referred to as "internal information storage response"). (Step S35), the normal mode is restored (Step S36).

  The host device 3 confirms the internal information storage response from the controller 12 (step S37). Thus, the process associated with the internal information storage request is completed.

  Subsequently, the entire flow when there is an internal information acquisition request from the host device 3 will be described.

  After confirming the internal information storage response, the host device 3 transmits an internal information acquisition request to the controller 12 (step S38). For example, the internal information acquisition request includes an acquisition instruction (acquisition command) and a logical address.

  The controller 12 shifts to the analysis mode and does not respond to the normal operation request from the host device 3 (step S39).

  The controller 12 transmits an internal information acquisition command to the memory 11 (step S40). More specifically, the CPU 42 converts the logical address received from the host device 3 into a physical address based on the logical-physical conversion data. Further, the CPU 42 issues an acquisition command that can be recognized by the memory 11. Then, the CPU 42 transmits the acquisition command and the physical address to the memory 11 as an internal information acquisition instruction via the memory interface 34.

  When receiving the internal information acquisition command, the memory 11 executes an internal information acquisition operation (read operation) (step S41). At this time, internal information is read from the memory group MG in the system area 131.

  The memory 11 transmits the internal information to the controller 12 (step S42).

  The controller 12 transmits the internal information received from the memory 11 to the host device 3 as a response to the internal information acquisition request (hereinafter referred to as "internal information acquisition response") (step S43), and returns to the normal mode (step S43) S44).

  The host device 3 acquires internal information from the controller 12 (step S45). Thus, the process associated with the internal information acquisition request is completed.

  In the flow of FIG. 10, the return to the normal mode of step S36 and the transition to the analysis mode of step S39 may be eliminated. In this case, even in the analysis mode, the memory device 2 may respond to the internal information acquisition request from the host device 3. Furthermore, the host device 3 may transmit storage and acquisition of internal information to the memory device 2 as one request.

1.3 Specific Example of Access of Host and Memory Device Next, a specific example of access of the host device 3 and the memory device 2 will be described with reference to FIGS. 11 and 12. 11 and 12, steps S101 to S109 show the case where an abnormality (timeout) occurs in the normal operation (write operation and read operation) in the memory system 1, and steps S110 to S124 indicate analysis operations (internal Information storage and acquisition) are shown, and steps S125 to S130 show the normal operation after the analysis operation. The host device 3 can transmit the normal operation request to the memory device 2 also during the analysis operation in the memory system 1.

  As shown in FIG. 11, for example, the host device 3 transmits a read request to the memory device 2 (step S101). After executing the read operation (step S102), the memory device 2 transmits a read response (read data) to the host device 3 (step S103). The host device 3 acquires the read data, and the process associated with the read request ends.

  Also, for example, the host device 3 transmits a write request to the memory device 2 (step S104). After executing the write operation (step S105), the memory device 2 transmits a write response to the host device 3 (step S106). The host device 3 confirms the write response, and the process associated with the write request ends.

  The host device 3 transmits a write request different from step S104 to the memory device 2 (step S107). At this time, for example, when an abnormality occurs in the memory device 2 (step S108), the host device 3 can not respond even if it retransmits the request multiple times, resulting in timeout (step S109).

  When a timeout occurs, the host device 3 shifts the memory system 1 to an analysis operation. More specifically, the host device 3 transmits an internal information storage request to the memory device 2 (step S110). The memory device 2 shifts to the analysis mode (step S111), and stores the internal information (step S112).

  Even while the memory device 2 stores internal information in the memory system 1, the host device 3 may access the memory device 2 and transmit a read request, for example (step S 113). However, since the memory device 2 is in the analysis mode, it does not respond to the read request (step S114).

  When the storage of the internal information is completed, the memory device 2 transmits a storage response of the internal information to the host device 3 (step S115), and returns to the normal mode (step S116). The host device 3 confirms the storage response of the internal information, and the processing associated with the internal information storage request ends.

  As shown in FIG. 12, when the internal information storage request is completed, the host device 3 transmits an internal information acquisition request to the memory device 2 (step S117). The memory device 2 shifts to the analysis mode (step S118), and acquires internal information (step S119).

  Even while the memory device 2 acquires the internal information, the host device 3 may access the memory device 2 and transmit a write request, for example (step S120). However, since the memory device 2 is in the analysis mode, it does not respond to the write request (step S121).

  When the acquisition of the internal information is completed, the memory device 2 transmits an acquisition response of the internal information to the host device 3 (step S122), and returns to the normal mode (step S123). The host device 3 acquires the internal information (step S124), and the process associated with the internal information acquisition request ends. Thus, the host device 3 shifts the memory system 1 to the normal operation.

  The host device 3 retransmits, for example, the read request in step S113 for which the memory device 2 did not receive a response to the memory device 2 (step S125). After executing the read operation (step S126), the memory device 2 transmits a read response (read data) to the host device 3 (step S127). The host device 3 acquires the read data, and the process associated with the read request in step S113 ends.

  The host device 3 retransmits, to the memory device 2, the write request of step S 120 for which no response has been obtained from the memory device 2 (step S 128). After executing the write operation (step S129), the memory device 2 transmits a write response to the host device 3 (step S130). The host device 3 confirms the write response, and the process associated with the write request in step S120 ends.

1.4 Effects of the Present Embodiment With the configuration of the present embodiment, it is possible to shorten the analysis operation period when an abnormality occurs in the memory system. Hereinafter, this effect will be described.

  First, the problem of the protocol analysis at the time of abnormality occurrence in the memory system based on the UFS standard will be described with reference to FIG. 13 and FIG. FIG. 13 shows an example of a memory system compliant with the e-MMC standard, and FIG. 14 shows an example of a memory system compliant with the UFS standard.

  As shown in FIG. 13, for example, in a memory system, a parallel interface compliant with an embedded multi media card (e-MMC) standard may be used to transmit and receive data between a host device and the memory device. In this case, since it is sufficient to secure a communication speed conforming to the e-MMC standard, a certain distance can be secured in the communication path between the host device and the memory device, and for example, a test pad may be provided in the communication path. it can. Therefore, when an abnormality such as timeout occurs in the memory system, a protocol analysis device can be connected to this test pad to analyze the cause of the abnormal state.

  On the other hand, as shown in FIG. 14, in the memory system, a high-speed serial interface conforming to the UFS standard, which has a higher communication speed than the e-MMC standard, is used to transmit and receive data between the host device and the memory device. There is a case. In this case, in order to perform high-speed communication, the communication path is designed to be short, and it may be difficult to secure a space for providing a test pad. In addition, there is a concern that the signal quality may be degraded by providing a test pad. Therefore, it becomes difficult to provide a test pad, and protocol analysis between devices becomes difficult.

  For example, a dedicated test substrate and equipment may be prepared, and the memory device may be transferred from the mounting substrate to the test substrate to perform protocol analysis. In this case, the period of the reproduction experiment for reproducing the abnormal state is required, and the analysis period becomes long. Also, by transferring the memory device, the abnormal state may not be reproduced, or the accuracy of the protocol acquisition may be reduced (data may be lost).

  Also, for example, the protocol may be acquired with the memory device mounted. In this case, after reproducing the abnormal state by reproducing experiment, the host device transmits the internal information storage request and the internal information acquisition request to the memory device, and extracts the internal information from the memory device. At this time, in the memory device, it is necessary to prevent the system information from being destroyed during the storage operation and the acquisition operation of the internal information. Therefore, the host device corrects the control program of the memory device at the time of the internal information storage request and the internal information acquisition request, and the memory device does not receive access from the host device for normal operation (write operation or read operation). Let's do it. After storing the internal information and after acquiring the internal information, restart processing and initialization processing of the memory system are performed, and the memory device returns to a state where access from the host device can be accepted.

  When acquiring internal information with the memory device mounted as described above, there are, for example, five problems as described below.

  First of all, the period for reproducing the abnormal state is required. Then, when the internal information storage request and the internal information acquisition request are made, the memory system restart processing and initialization processing are required. Therefore, the analysis period is relatively long.

  Second, the software modification of the memory device may change the timing of access until the occurrence of an abnormality, and the abnormal state may not be reproduced.

  Third, by performing the restart process and the initialization process, access is interrupted between the host device and the memory device, resulting in an inaccessible period. Therefore, for example, due to the occurrence of one abnormality, a long-term operation test in the memory system can not be continued.

  Fourth, for example, in the case where a plurality of abnormalities occur successively, if restart processing and initialization processing are performed after storage and acquisition of internal information with respect to the first abnormality occurrence, subsequent abnormality occurrence I can not save the internal information at the time. Therefore, internal information about continuous occurrence of abnormality can not be stored.

  Fifth, when a memory system error occurs, the host device can not arbitrarily save and acquire internal information of the memory device. Therefore, it takes a relatively long time to analyze whether the memory device is the cause of the abnormal state.

  On the other hand, in the memory system according to the present embodiment, the host device 3 has a retry function of retransmitting a request when there is no response from the memory device 2 to the request. The memory device 2 has two operation modes, a normal mode and an analysis mode. When the memory device 2 receives the internal information storage request and the internal information acquisition request from the host device 3, the memory device 2 shifts to the analysis mode during the storage operation and the acquisition operation of the internal information, and responds to the request from the host device 3. , Will not respond. Even if there is no response from the memory device 2 while in the analysis mode, the host device 3 can repeatedly transmit the same request multiple times, thereby avoiding a memory system abnormality due to the absence of a response. As a result, there is no need to rewrite the control program of the memory device 2 in accordance with the internal information storage request and the internal information acquisition request, and the restart processing and the initialization processing can be eliminated. Therefore, the period of internal information storage and acquisition in the memory system 1 can be shortened. Therefore, the analysis operation period when an abnormality occurs in the memory system 1 can be shortened.

  Furthermore, the memory device 2 can store internal information in a memory group MG that includes a plurality of memory groups MG in the system area 131 of the memory 11 and does not store system information. This can reduce the possibility of system information being destroyed. Therefore, when an abnormality occurs, the reproduction experiment can be omitted by storing the internal information at that time in the memory group MG in which the system information is not stored.

  Furthermore, since the software correction of the memory device is not required, the timing of access until the occurrence of an abnormality changes, and the possibility that the abnormal state will not be reproduced can be reduced.

  Furthermore, since the restart process and the initialization process are not required, access can be continued between the host device and the memory device. For this reason, for example, a long operation test in the memory system can be continued.

  Furthermore, even when a plurality of abnormalities occur, for example, the restart process and the initialization process become unnecessary, so internal information at the time of the subsequent abnormality occurrence can also be saved. Therefore, internal information on continuous abnormal conditions can be stored.

  Furthermore, in the event of a memory system failure, the host device can optionally save and acquire internal information of the memory device.

2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, a specific example of access between the host device 3 and the memory device 2 when a plurality of abnormalities occur will be described.

2.1 About Specific Example of Access of Host and Memory Device A specific example of access of the host device 3 and the memory device 2 will be described with reference to FIGS. In FIG. 15 to FIG. 17, steps S201 and S202 show the case where the host device 3 detects an abnormality of the system in the normal operation in the memory system 1, and steps S203 to S209 and steps S218 to S237 analyze operations. Steps S210 to S217 and steps S239 to S244 show the normal operation after the analysis operation.

  As shown in FIG. 15, the host device 3 transmits a write request to the memory device 2 (step S201). After transmitting the write request, the host device 3 detects any abnormality in the memory system 1 (step S202). In this case, the abnormality of the memory system 1 may be a timeout due to the memory device 2 or another abnormality.

  When detecting an abnormality, the host device 3 shifts the memory system 1 to the analysis operation. More specifically, the host device 3 transmits a storage request for the internal information 1 corresponding to the abnormality detection in step S202 to the memory device 2 (step S203). The memory device 2 shifts to the analysis mode (step S204), and stores the internal information 1 (step S205).

  Even while the memory device 2 stores the internal information 1, the host device 3 may access the memory device 2 and transmit, for example, a write request (step S206). However, since the memory device 2 is in the analysis mode, it does not respond to the write request (step S207).

  When the storage of the internal information 1 is completed, the memory device 2 transmits a storage response of the internal information 1 to the host device 3 (step S208), and returns to the normal mode (step S209). The host device 3 confirms the storage response of the internal information 1, and the processing associated with the storage request of the internal information 1 ends. Thus, the host device 3 shifts the memory system 1 to the normal operation.

  The host device 3 re-sends, for example, the memory device 2 to the write request of step S206 for which the memory device 2 did not receive a response (step S210). After executing the write operation (step S211), the memory device 2 transmits a write response to the host device 3 (step S212). The host device 3 confirms the write response, and the process associated with the write request in step S206 ends.

  Subsequently, the host device 3 transmits a read request to the memory device 2 (step S212). After executing the read operation (step S213), the memory device 2 transmits a read response (read data) to the host device 3 (step S214). The host device 3 acquires the read data, and the process associated with the read request ends.

  As illustrated in FIG. 16, the host device 3 transmits, to the memory device 2, a read request different from step S <b> 212 (step S <b> 215). At this time, for example, when an abnormality occurs in the memory device 2 (step S216), a timeout occurs (step S217).

  When a timeout occurs, the host device 3 shifts the memory system 1 to the analysis operation. More specifically, the host device 3 transmits, to the memory device 2, a request for storing the internal information 2 corresponding to the time-out in step S217 (step S218). The memory device 2 shifts to the analysis mode (step S219), and stores the internal information 2 (step S220). At this time, internal information 2 is stored in a memory group MG different from memory group MG in which system information is stored and memory group MG in which internal information 1 is stored.

  Even while the memory device 2 stores the internal information 2, the host device 3 may access the memory device 2 and transmit a read request, for example (step S221). However, since the memory device 2 is in the analysis mode, it does not respond to the read request (step S222).

  When the storage of the internal information 2 is completed, the memory device 2 transmits a storage response of the internal information 2 to the host device 3 (step S225), and returns to the normal mode (step S224). The host device 3 confirms the storage response of the internal information 2, and the process associated with the storage request of the internal information 2 ends.

  When the storage request for the internal information 2 is completed, the host device 3 transmits an acquisition request for the internal information 1 to the memory device 2 (step S225). The memory device 2 shifts to the analysis mode (step S226), and acquires the internal information 1 (step S227).

  Even while the memory device 2 acquires the internal information 1, the host device 3 may access the memory device 2 and transmit, for example, a write request (step S228). However, since the memory device 2 is in the analysis mode, it does not respond to the write request (step S229).

  When the acquisition of the internal information 1 is completed, the memory device 2 transmits an acquisition response of the internal information 1 to the host device 3 (step S230), and returns to the normal mode (step S231). The host device 3 acquires the internal information 1 (step S232), and the process associated with the acquisition request of the internal information 1 ends.

  As illustrated in FIG. 17, when the acquisition request for the internal information 1 ends, the host device 3 transmits, for example, the acquisition request for the internal information 2 to the memory device 2 (step S233). The memory device 2 shifts to the analysis mode (step S234), and acquires the internal information 2 (step S235).

  When the acquisition of the internal information 2 is completed, the memory device 2 transmits an acquisition response of the internal information 2 to the host device 3 (step S236), and returns to the normal mode (step S237). The host device 3 acquires the internal information 2 (step S238), and the process associated with the acquisition request for the internal information 2 ends. Thus, the host device 3 shifts the memory system 1 to the normal operation.

  The host device 3 retransmits, to the memory device 2, for example, the read request of step S221 for which no response has been obtained from the memory device 2 (step S239). After executing the read operation (step S240), the memory device 2 transmits a read response (read data) to the host device 3 (step S241). The host device 3 acquires the read data, and the process associated with the read request in step S221 ends.

  Also, the host device 3 retransmits, to the memory device 2, for example, the write request of step S 228 for which a response was not obtained from the memory device 2 (step S 242). After executing the write operation (step S243), the memory device 2 transmits a write response to the host device 3 (step S244). The host device 3 confirms the write response, and the process associated with the write request in step S244 ends.

2.2 Effects of the Present Embodiment With the configuration according to the present embodiment, the same effects as those of the first embodiment can be obtained.

  Furthermore, with the configuration according to the present embodiment, a plurality of pieces of internal information can be stored in different memory groups MG. For example, when a plurality of abnormalities occur during a long-term operation test of the memory system 1, the internal information is stored and the test is continued each time an abnormality occurs, and the plurality of internal information is It can be acquired collectively. As a result, even when an abnormality occurs, the test can be continued, and internal information on continuous abnormality occurrence can be acquired.

3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a case where the memory system 1 includes a plurality of memory devices 2 will be described.

3.1 Overall Configuration of Memory System The overall configuration of the memory system 1 will be described with reference to FIG. Although the details of the memory devices 2-0 and 2-1 are omitted in the example of FIG. 18 to simplify the description, the configuration of the memory devices 2-0 and 2-1 is the same as that of the first embodiment. It is the same as FIG. 1 and FIG.

  As shown in FIG. 18, the memory system 1 includes a host device 3 and two memory devices 2 (2-0 and 2-1). The number of memory devices 2 included in the memory system 1 may be three or more. The host device 3 and two memory devices 2 (2-0 and 2-1) are respectively connected via a host bus. The signals transmitted and received between the memory device 2 and the host device 3 via the host bus include RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c, as in the first embodiment. Each signal may be separately assigned to memory devices 2-0 and 2-1 (e.g. RESET0 is sent to memory device 2-0 and RESET1 is sent to memory device 2-1), common It may be

  The memory device 2-0 includes a controller 12-0 and a memory 11-0. The configurations of the controller 12-0 and the memory 11-0 are the same as in the first embodiment. Similarly, the memory device 2-1 includes a controller 12-1 and a memory 11-1.

3.2 Effects of the Present Embodiment With the configuration of the present embodiment, the same effects as in the first and second embodiments can be obtained.

4. Modified Example Etc. The memory system according to the above embodiment is connected to a host device capable of transmitting an internal information storage request and an internal information acquisition request, and a host device (3), and includes a memory cell array (a plurality of memory cells (MT)) 108) and a control circuit (12) for controlling the memory, and includes a memory device (2) having a first control mode (normal mode) and a second control mode (analysis mode) . When the control circuit receives a write request or read request from the host device, the control circuit responds to the received write request or read request in the first control mode, and receives the received write request in the second control mode. When the internal information storage request or the internal information acquisition request is received from the host device without responding to the read request, the control mode is shifted from the first control mode to the second control mode and the internal information storage operation or acquisition operation is executed. After the storage operation or the acquisition operation is finished, the second control mode is shifted to the first control mode without restarting the memory device.

  The embodiment is not limited to the above-described embodiment, and various modifications are possible.

  For example, in the above embodiment, the memory system may conform to the e-MMC standard, or may conform to another communication protocol. The present invention can be applied to a memory system in which a host device has a retry function.

  Furthermore, the “connection” in the above embodiment also includes a state of being indirectly connected with another something, such as a transistor or a resistor, interposed therebetween.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

DESCRIPTION OF SYMBOLS 1 ... Memory system, 2 ... Memory device, 3 ... Host device, 11 ... Memory, 12 ... Controller, 18 ... Memory cell array, 22 ... Core logic part, 31 ... Host interface, 32, 35 ... Buffer, 33 ... Data bus, 34: Memory interface, 36: ECC circuit, 41: Control bus, 42: CPU, 43: ROM, 44: RAM, 45: Register, 51: Analog circuit, 100: I / O circuit, 101: Logic control circuit, 102: Status register, 103: address register, 104: command register, 105: sequencer, 106: ready / busy circuit, 107: voltage generation circuit, 108: memory cell array, 109: row decoder, 110: sense amplifier, 111: data register, 112: Column decoder, 30 ... user area, 131 ... system area, 200 ... semiconductor substrate, 201 ... n-type well, 202 ... p-type well, 203 ... ^{n +} -type diffusion layer, 204, 210 ... wiring layer, 205 ... semiconductor layer, 206, 208 ... Insulating film, 207 ... charge storage layer, 209 ... contact plug, 301 ... printed circuit board, 302 ... wire, 303 ... package.

Claims (7)

A host device capable of transmitting an internal information storage request and an internal information acquisition request;
A memory device connected to the host device and including a memory cell array including a plurality of memory cells, and a control circuit for controlling the memory, the memory device having a first control mode and a second control mode;
The control circuit comprises
When a write request or a read request is received from the host device, it responds to the received write request or the read request in the case of the first control mode, and receives the received in the case of the second control mode. Do not respond to a write request or the read request,
When the internal information storage request or the internal information acquisition request is received from the host device, the control mode is switched from the first control mode to the second control mode to execute the internal information storage operation or acquisition operation, and the storage operation Or, after the acquisition operation is finished, transitioning from the second control mode to the first control mode without restarting the memory device.
Memory system. The memory cell array is
A first memory area corresponding to the write request and the read request received from the host device;
A plurality of memory groups, system information and a second memory area capable of storing the internal information, the system information is stored in any one of the plurality of memory groups, and the internal information is the system The information is stored in any of the plurality of memory groups where the information is not stored,
The memory system according to claim 1. The host device is configured to re-send the write request or the read request to the memory device when there is no response from the memory device to the write request or the read request.
The memory system according to claim 1. The internal information includes an error log of an abnormality that has occurred in the memory device.
The memory system according to any one of claims 1 to 3. The memory device communicates with the host device in accordance with the universal flash storage (UFS) standard.
The memory system according to any one of claims 1 to 4. Comprising a plurality of said memory devices,
The memory system according to any one of claims 1 to 5. Connectable with host device,
Has a first control mode and a second control mode,
A memory including a memory cell array including a plurality of memory cells;
A control circuit for controlling the memory, the control circuit comprising:
When a write request or a read request is received from the host device, it responds to the received write request or the read request in the case of the first control mode, and receives the received in the case of the second control mode. Do not respond to a write request or the read request,
When an internal information storage request or an internal information acquisition request is received from the host device, the control mode is shifted from the first control mode to the second control mode to execute an internal information storage operation or an internal information acquisition operation. After the end of the storage operation or the acquisition operation, the second control mode is shifted to the first control mode without being restarted.
Memory device.