CN116798490A

CN116798490A - Memory system

Info

Publication number: CN116798490A
Application number: CN202210696772.8A
Authority: CN
Inventors: 柴崎健太; 进藤佳彦; 平嶋康伯; 菅原昭雄; 长坂繁辉; 中村大; 萩原洋介
Original assignee: Kioxia Corp
Current assignee: Kioxia Corp
Priority date: 2022-03-16
Filing date: 2022-06-20
Publication date: 2023-09-22
Also published as: US20230297239A1; JP2023136000A; TW202338834A

Abstract

Embodiments increase the processing power of a memory system. According to an embodiment, a memory system includes a memory chip (11) including a memory cell array (111), and a memory controller (20) controlling the memory chip. In the memory cell array, the 1 st data (chip start-up data) used in the 1 st action (POR) performed at the time of the memory chip start-up is stored. The memory chip does not read out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is received from the memory controller, and reads out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is not received from the memory controller.

Description

Memory system

[ associated application ]

The present application enjoys priority over Japanese patent application No. 2022-41389 (application date: 16. 3. Of 2022). The present application includes the entire contents of the basic application by reference to the basic application.

Technical Field

Embodiments of the application relate to a memory system.

Background

As a memory system, an SSD (Solid State Drive ) mounted with a nonvolatile memory device such as a NAND flash memory is known.

Disclosure of Invention

In one embodiment of the present invention, a memory system is provided that can increase processing power.

The memory system of an embodiment includes a memory chip including a memory cell array, and a memory controller controlling the memory chip. The memory cell array stores 1 st data used in 1 st operation performed at the time of starting up the memory chip. The memory chip does not read out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is received from the memory controller, and reads out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is not received from the memory controller.

Drawings

Fig. 1 is a block diagram showing an example of the overall configuration of a data processing apparatus including the memory system according to embodiment 1.

Fig. 2 is a block diagram showing a basic configuration of a memory chip included in the memory system according to embodiment 1.

Fig. 3 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory system according to embodiment 1.

Fig. 4 is a block diagram of a data register and a sense amplifier included in the memory system of embodiment 1.

Fig. 5 is a flowchart showing a power-on read operation corresponding to the low power consumption mode in the memory system of embodiment 1.

Fig. 6 is a flowchart showing a stop operation of a memory chip corresponding to the low power consumption mode in the memory system according to embodiment 1.

Fig. 7 is a diagram showing a command sequence and a consumption current of a full-sequence operation in the memory system according to embodiment 1.

Fig. 8 is a diagram showing instruction sequences and consumption currents of a cell read operation and a cache read operation in the memory system according to embodiment 1.

Fig. 9 is a diagram showing an instruction sequence and a consumption current of a cache write operation and a set operation in the memory system according to embodiment 1.

Fig. 10 is a cross-sectional view showing an example of a memory device in which memory chips 11_0 to 11_7 included in the memory system according to embodiment 1 are stacked.

Fig. 11 is a diagram showing the current consumption in the case where the memory chips 11_0 to 11_7 included in the memory system according to embodiment 1 perform the full-sequence operation.

Fig. 12 is a diagram showing the current consumption in the case where the memory chips 11_0 to 11_7 included in the memory system according to embodiment 1 perform the set operation.

Fig. 13 is another diagram showing the current consumption in the case where the memory chips 11_0 to 11_7 included in the memory system according to embodiment 1 perform the set operation.

Fig. 14 is a block diagram showing an example of the overall configuration of a data processing apparatus including the memory system of example 1 of embodiment 2.

Fig. 15 is a block diagram showing a basic configuration of a memory chip included in the memory system of example 1 of embodiment 2.

Fig. 16 is a diagram showing an example of on/off control of a memory chip in the memory system of example 1 according to embodiment 2.

Fig. 17 is a block diagram showing a basic configuration of a memory chip included in the memory system of example 2 of embodiment 2.

Fig. 18 is a block diagram showing a basic configuration of a memory chip included in the memory system according to example 3 of embodiment 2.

Fig. 19 is a diagram showing an instruction sequence of a cache write operation and a set operation in the memory system of example 1 according to embodiment 3.

Fig. 20 is a diagram showing an instruction sequence of a cache write operation and a set operation in the memory system of example 2 according to embodiment 3.

Fig. 21 is a flowchart showing a power-on read operation corresponding to the low power consumption mode in the memory system of example 1 according to embodiment 4.

Fig. 22 is a flowchart showing a power-on read operation corresponding to the low power consumption mode in the memory system of example 2 according to embodiment 4.

Fig. 23 is a block diagram showing a basic configuration of a NOR flash memory included in the memory system according to embodiment 5.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. The drawing is a schematic diagram. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. Numerals after characters constituting the reference numerals are referred to by the reference numerals including the same characters, and are used to distinguish elements having the same constitution from each other. Where elements represented by reference numerals including the same letter do not need to be distinguished from each other, the elements may be referenced by reference numerals including only the same letter.

The memory system according to the embodiment will be described below.

1 constitution of

1.1 construction of information processing apparatus

1.1.1 construction of data processing apparatus

First, an example of the structure of the data processing apparatus 1 including a memory system will be described with reference to fig. 1. Fig. 1 is a block diagram showing an example of the overall configuration of the data processing apparatus 1.

As shown in fig. 1, the data processing apparatus 1 includes a host device 2 and a memory system 3. The data processing apparatus 1 may comprise a plurality of host devices 2 or a plurality of memory systems 3. In the case where the data processing apparatus 1 includes a plurality of host devices 2 and a plurality of memory systems 3, the plurality of memory systems 3 may be connected to 1 host device 2. Further, a plurality of host devices 2 may be connected to 1 memory system 3.

The host device 2 is an information processing apparatus (computing device) that accesses the memory system 3. The host device 2 controls the memory system 3. More specifically, for example, the host device 2 requests (commands) a writing operation or a reading operation of data (hereinafter, referred to as "user data") to the memory system 3.

The memory system 3 is, for example, SSD (Solid State Drive). The memory system 3 is connected to the host device 2 via a host bus HB.

1.1.2 construction of memory systems

Next, an example of the structure of the memory system 3 will be described.

As shown in fig. 1, the memory system 3 includes a memory device 10 and a memory controller 20.

The memory device 10 is a nonvolatile storage medium (semiconductor storage device). Memory device 10 non-volatile stores data received from memory controller 20. Hereinafter, a case where the memory device 10 is a NAND type flash memory will be described. The memory device 10 may be a nonvolatile memory medium other than a NAND flash memory.

The memory controller 20 is, for example, a SoC (System On a Chip). The memory controller 20 commands the memory device 10 with a read operation, a write operation, an erase operation, and the like in response to a request (command) from the host device 2. In addition, the memory controller 20 manages the storage space of the memory device 10.

Next, an example of the internal configuration of the memory device 10 will be described. The memory device 10 may include a plurality of memory chips 11 (also abbreviated as "chips"). The plurality of memory chips 11 can be operated independently. The number of memory chips 11 included in the memory device 10 may be arbitrary.

The memory chip 11 is, for example, a semiconductor chip on which a NAND flash memory is mounted. The memory chip 11 stores data nonvolatile. The memory chip 11 is connected to the memory controller 20 via a NAND bus NB. In addition, the memory chip 11 may be other nonvolatile memories.

Next, an example of the internal configuration of the memory controller 20 will be described. The Memory controller 20 includes a host interface circuit (host I/F) 21, a CPU (Center Processing Unit, central processing unit) 22, a ROM (Read Only Memory) 23, a RAM (Random Access Memory ) 24, a buffer Memory 25, an ECC (Error Checking and Correcting ) circuit 26, and a Memory interface circuit (Memory I/F) 27. These circuits are connected to each other, for example, through an internal bus of the memory controller 20. The functions of the host interface circuit 21, the ECC circuit 26, and the memory interface circuit 27 may be realized by dedicated circuits or by the CPU22 executing firmware.

The host interface circuit 21 is an interface circuit connected to the host device 2. The host interface circuit 21 controls communication between the host device 2 and the memory controller 20. The host interface circuit 21 transmits the request and user data received from the host device 2 to the CPU22 and the buffer memory 25, respectively. Further, the host interface circuit 21 transmits the user data in the buffer memory 25 to the host device 2 according to the control of the CPU 22.

The CPU22 is a processor. The CPU22 controls the operation of the entire memory controller 20. For example, the CPU22 commands a write operation, a read operation, and an erase operation to the memory device 10 (memory chip 11) according to the request of the host device 2.

The CPU22 controls the memory device 10. For example, the CPU22 may control switching between on-state and off-state of the memory chip 11 (hereinafter, referred to as "on/off control") according to the operation condition of the memory chip 11. More specifically, the CPU22 supplies a power supply voltage to the memory chip 11 that performs operations such as a read operation, a write operation, and an erase operation (hereinafter, also referred to as "normal operation"), and turns on the memory chip 11 (hereinafter, also referred to as "turning on the power supply of the memory chip 11"). On the other hand, the CPU22 stops the supply of the power supply voltage to the memory chip 11 in the standby state, and turns off the memory chip 11 (hereinafter, also referred to as "turning off the power supply to the memory chip 11"). The CPU22 controls an increase in power consumption in the memory system 3 by turning off the memory chip 11 in the standby state. Hereinafter, a mode in which the CPU22 performs on/off control of the memory chip 11 is referred to as a "low power consumption mode". In the low power consumption mode, the CPU22 (memory controller 20) repeatedly performs on/off control of the memory chip 11 while maintaining the on state. In the case of executing the low power consumption mode, the CPU22 may execute on/off control for each memory chip 11, or may set a plurality of memory chips 11 to 1 group to execute on/off control. For example, the unit of on/off control may be a channel CH unit described later, or may be a unit of the memory chip 11 that is uniformly enabled by a chip enable signal CEn described later.

In the following description, when the CPU22 performs various operations associated with the on/off control of the memory chip 11 in accordance with the low power consumption mode, the operation corresponding to the low power consumption mode will be described as "operation corresponding to the low power consumption mode". Before the memory chip 11 is turned off in response to the low power consumption mode, the CPU22 reads out chip start data (also referred to as "start data") from the memory chip 11. The chip start-up data is data used in a Power On Read (POR) operation, which is one of the start-up operations (start-up operations) of the memory chip 11. The memory chip 11 performs various settings based on the chip start data, management of a memory element capable of normal operation, and the like. For example, the CPU22 causes the RAM24 to store chip start-up data. If the memory chip 11 as the object is in the on state, the CPU22 may perform the read-out operation of the chip start data at an arbitrary timing.

The CPU22 controls the memory chip 11 to perform a different power-on read operation in response to the presence or absence of the read operation of the chip start data. The power-on read operation includes an operation of reading out chip start-up data from the memory cell array of the target memory chip 11 (hereinafter, referred to as "cell read operation"), and an operation of transferring (storing) the read-out chip start-up data to a corresponding register in the memory chip 11 (hereinafter, referred to as "set operation"). The CPU22 controls the unit read operation and the setting operation to be performed during the power-on read operation without performing the read operation of the chip start data. On the other hand, when the read operation of the chip start data is executed, the CPU22 controls the power-on read operation so that the cell read operation is omitted.

More specifically, for example, in the first start-up operation of the memory chip 11 after the memory controller 20 is turned on, the CPU22 does not execute the read-out operation of the chip start-up data until the start-up operation of the memory chip 11. In this case, the CPU22 executes the cell reading operation and the setting operation in the power-on reading operation. That is, the CPU22 performs the setting operation using the chip start data read out by the unit reading operation.

On the other hand, for example, in the on/off control of the memory chip 11 corresponding to the low power consumption mode, the CPU22 reads out the chip start data from the memory chip 11 in advance before turning the memory chip 11 into the off state. In this case, the CPU22 transmits the chip start data to the memory chip 11. Then, the CPU22 controls the memory chip 11 to perform a power-on read operation using the chip start data received from the memory controller 20. In this way, in the case of the power-on read operation corresponding to the low power consumption mode, the cell read operation is omitted.

For example, the chip start data includes parameter information, bad block information, and bad column information. This information is different in each memory chip 11. Accordingly, the CPU22 performs a read-out operation of the chip start data for each memory chip 11.

The parameter information is set value information of the memory chip 11. For example, the parameter information may include information such as voltage and voltage application time of each wiring in writing operation, reading operation, erasing operation, and the like.

The bad block information is information of blocks which cannot be used in the memory cell array of the memory chip 11. For example, a block is a unit of a memory area in which erasing data is unified in the memory chip 11. For example, the bad block information includes information of blocks determined to be unusable by shipment inspection or the like of the memory chip 11.

The bad column information is information of a column which cannot be used in the memory cell array of the memory chip 11, that is, information of a bit line which cannot be used. For example, the bad column information includes information of a column determined to be unusable by shipment inspection or the like of the memory chip 11.

The ROM23 is a nonvolatile memory. ROM23 is, for example, EEPROM ^TM (Electrically Erasable Programmable Read-Only Memory), electrically erasable programmable read Only Memory). The ROM23 is a non-transitory storage medium storing firmware, programs, and the like. For example, the CPU22 expands the firmware loaded from the ROM23 in the RAM 24.

RAM24 is volatile memory. RAM24 is DRAM (Dynamic Random Access Memory ) or SRAM (Static Random Access Memory, static random access memory), or the like. The RAM24 can be used as a work area of the CPU 22. For example, the RAM24 stores firmware for managing the memory device 10, various management tables.

The RAM24 of the present embodiment stores chip start data of each memory chip 11. In addition, the chip start data may be stored in a memory area other than the RAM 24.

The buffer memory 25 is a volatile memory. The buffer memory 25 is a DRAM, an SRAM, or the like. The buffer memory 25 temporarily holds user data read out from the memory device 10 by the memory controller 20, user data received from the host device 2, and the like.

The ECC circuit 26 is a circuit that performs ECC processing. The ECC processing includes encoding processing and decoding processing of data. For example, the ECC circuit 26 performs data encoding processing during a data writing operation to generate an error correction code (parity check). Then, the ECC circuit 26 gives parity to the data. The ECC circuit 26 performs decoding processing during a data reading operation. That is, the ECC circuit 26 performs error correction processing of data using parity.

Memory interface circuitry 27 controls communication between memory controller 20 and memory device 10. More specifically, the memory interface circuit 27 transmits instructions corresponding to a write operation, a read operation, an erase operation, and the like to the memory chip 11. The memory interface circuit 27 receives read data from the memory chip 11 during a read operation. The memory interface circuit 27 may have a plurality of channels CH (CH 0, CH1, …). A plurality of memory chips 11 may be connected to each channel CH via a NAND bus NB.

1.1.3 formation of memory chips

Next, an example of the structure of the memory chip 11 will be described with reference to fig. 2. Fig. 2 is a block diagram showing a basic configuration of the memory chip 11. In the example shown in fig. 2, part of the connection between the constituent elements is indicated by an arrow line. However, the connection between the components is not limited to this.

As shown in fig. 2, the memory chip 11 transmits and receives signals DQ and DQs to and from the memory controller 20 (more specifically, the memory interface circuit 27) via the NAND bus NB. The signal DQ is, for example, data DAT, address ADD, command CMD. The timing signals DQS and DQSn are timing signals used when the data DAT is input and output. The timing signal DQSn is an inversion signal of the timing signal DQS.

Further, the memory chip 11 receives, for example, a chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the memory controller 20 via the NAND bus NB. Further, the memory chip 11 transmits a ready/busy signal RBn to the memory controller 20 via the NAND bus NB.

The chip enable signal CEn is a signal for enabling the memory chip 11. The signal CEn is asserted, for example, at a low ("L") level.

The instruction latch enable signal CLE is a signal indicating that the signal DQ is an instruction. The signal CLE is asserted, for example, at a high ("H") level.

The address latch enable signal ALE is a signal indicating that the signal DQ is an address. The signal ALE is asserted, for example, at an "H" level.

The write enable signal Wen is a signal for taking in the signal DQ when the signal DQ is the command CMD or the address ADD. The signal WEn takes in the command CMD or the address ADD at the timing of the memory chip 11, for example, takes effect at the "L" level. Thus, each time the signal WEn is triggered, the command CMD or the address ADD is fetched into the memory chip 11.

The read enable signal REn is a signal to read out data from the memory chip 11 by the memory controller 20. The signal REn is asserted, for example, at the "L" level. For example, the memory chip 11 generates the signals DQS and DQSn based on the signal REn at the time of data output.

The ready/busy signal RBn is a signal indicating a state in which the memory chip 11 can or cannot receive the command CMD from the memory controller 20. The ready state is a state in which the memory chip 11 can receive a command CMD from the memory controller 20. The busy state is a state in which the memory chip 11 cannot receive the command CMD from the memory controller 20. For example, the ready/busy signal RBn is set to "L" level when the memory chip 11 is in a busy state.

Next, the internal configuration of the memory chip 11 will be described. The memory chip 11 includes an input-output circuit 101, a logic control circuit 102, an address register 103, an instruction register 104, a sequencer 105, a ready/busy circuit 106, a parameter information register 107, a bad block information register 108, a bad column information register 109, a voltage generating circuit 110, a memory cell array 111, a row decoder 112, a sense amplifier 113, a data register 114, and a column decoder 115.

The input/output circuit 101 is a circuit for inputting and outputting a signal DQ. The input/output circuit 101 is connected to the memory controller 20 via the NAND bus NB. The input/output circuit 101 is connected to the logic control circuit 102, the address register 103, the instruction register 104, and the data register 114.

The input/output circuit 101 transmits the address ADD to the address register 103 when the input signal DQ is the address ADD. When the input signal DQ is a command CMD, the input/output circuit 101 sends the command CMD to the command register 104.

The input/output circuit 101 receives the input signal DQ based on the timing signals DQs and DQSn when the input signal DQ is data DAT. The input/output circuit 101 transmits data DAT to the data register 114. The input/output circuit 101 outputs the data DAT to the memory controller 20 together with the timing signals DQS and DQSn.

The logic control circuit 102 is a circuit that performs logic control of the memory chip 11. The logic control circuit 102 is connected to the memory controller 20 via the NAND bus NB. The logic control circuit 102 is connected to the input/output circuit 101 and the sequencer 105. The logic control circuit 102 receives various control signals such as the signal CEn, CLE, ALE, WEn and REn from the memory controller 20. The logic control circuit 102 controls the input/output circuit 101 and the sequencer 105 according to the received control signal.

The address register 103 is a register that temporarily stores an address ADD. The address register 103 is connected to the input/output circuit 101, the row decoder 112, and the column decoder 115. Address ADD includes a row address RA and a column address CA. The address register 103 sends the row address RA to the row decoder 112. Further, the address register 103 sends a column address CA to the column decoder 115.

The instruction register 104 is a register that temporarily stores the instruction CMD. The instruction register 104 is connected to the input/output circuit 101 and the sequencer 105. The instruction register 104 sends a command CMD to the sequencer 105.

The sequencer 105 is a circuit that performs control of the memory chip 11. The sequencer 105 controls the operation of the entire memory chip 11. More specifically, for example, the sequencer 105 is connected to the logic control circuit 102, the instruction register 104, the ready/busy circuit 106, the parameter information register 107, the bad block information register 108, the bad column information register 109, the voltage generating circuit 110, the row decoder 112, the sense amplifier 113, and the data register 114. Also, for example, sequencer 105 controls ready/busy circuit 106, parameter information register 107, bad block information register 108, bad column information register 109, row decoder 112, and sense amplifier 113.

The sequencer 105 executes a write operation, a read operation, an erase operation, and the like in accordance with the command CMD. Sequencer 105 may receive chip enable data from data registers 114. The sequencer 105 transmits and receives parameter information to and from the parameter information register 107. The sequencer 105 transmits and receives bad block information to and from the bad block information register 108. The sequencer 105 transmits and receives bad column information to and from the bad column information register 109.

Ready/busy circuit 106 is a circuit that sends ready/busy signal RBn. Ready/busy circuit 106 sends ready/busy signal RBn to memory controller 20 based on the action status of sequencer 105.

The parameter information register 107 is a register that temporarily stores parameter information.

Bad block information register 108 is a register that temporarily stores bad block information.

The bad column information register 109 is a register that temporarily stores bad column information.

The voltage generating circuit 110 generates voltages used in writing operation, reading operation, and erasing operation. The voltage generating circuit 110 is connected to a row decoder 112, a sense amplifier 113, and the like. For example, the voltage generation circuit 110 supplies a voltage to the row decoder 112 and the sense amplifier 113.

The memory cell array 111 is a set of a plurality of memory cell transistors arranged in a two-dimensional or three-dimensional matrix. The memory cell array 111 includes a user region and a ROM (Read Only Memory) fuse region as memory regions. The user area is an area storing user data. The ROM fuse area is an area in which various system data including chip start data is stored. The ROM fuse area is an area that is inaccessible to the host device 2. The memory cell array 111 includes, for example, n blocks BLK0 to BLKn and 1 block blk_rom. For example, a block BLK is a set of memory cell transistors that collectively erases data. That is, the block BLK is an erase unit of data. For example, blocks BLK0 to BLKn are allocated to the user area. The block BLK_ROM is assigned to the ROM fuse area. In addition, a plurality of blocks blk_rom may be provided. The detailed construction of the block BLK is described below.

The row decoder 112 is a decoding circuit of the row address RA. The row decoder 112 selects any block BLK within the memory cell array 111 according to the decoding result. The row decoder 112 applies a voltage to the wirings (word lines and select gate lines described later) in the row direction of the selected block BLK.

The sense amplifier 113 is a circuit for writing and reading data DAT. The sense amplifier 113 is connected to the memory cell array 111 and the data register 114. The sense amplifier 113 reads out data DAT from the memory cell array 111 during a read operation. In addition, the sense amplifier 113 supplies a voltage based on the write data DAT to the memory cell array 111 during the write operation.

The data register 114 is a register that temporarily stores data DAT. The data register 114 is connected to the sense amplifier 113 and the column decoder 115. The data register 114 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

The column decoder 115 is a circuit that decodes a column address CA. The column decoder 115 receives a column address CA from the address register 103. The column decoder 115 selects a latch circuit in the data register 114 according to the decoding result of the column address CA.

1.1.4 Circuit configuration of memory cell array

Next, an example of the circuit configuration of the memory cell array 111 will be described with reference to fig. 3. Fig. 3 is a circuit diagram showing an example of the circuit configuration of 1 block BLK. The blocks BLK0 to BLKn and BLK_ROM have the same structure.

The block BLK includes a plurality of strings SU. In the example shown in fig. 3, the block BLK includes 4 strings SU0 to SU3. In addition, the number of strings SU included in the block BLK may be arbitrary. String group SU is, for example, a set of a plurality of NAND strings NS that are collectively selected in a write operation or a read operation.

Next, the internal configuration of the string SU will be described. String set SU includes a plurality of NAND strings NS. NAND string NS is a collection of multiple memory cell transistors connected in series. The plurality of NAND strings NS in the string group SU are connected to any one of the bit lines BL0 to BLi (i is an integer of 1 or more).

Next, the internal configuration of the NAND string NS will be described. Each NAND string NS includes a plurality of memory cell transistors MC, and select transistors ST1 and ST2. In the example shown in FIG. 3, NAND string NS includes 8 memory cell transistors MC 0-MC 7.

The memory cell transistor MC is a memory element that stores data nonvolatile. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be of a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type.

The selection transistors ST1 and ST2 are switching elements. The selection transistors ST1 and ST2 are used for selecting the string group SU at various operations.

The current paths of the select transistor ST2, the memory cell transistors MC0 to MC7, and the select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to the bit line BL. The source of the selection transistor ST2 is connected to the source line SL.

The control gates of the memory cell transistors MC0 to MC7 of the same block BLK are commonly connected to word lines WL0 to WL7, respectively. More specifically, for example, the block BLK includes 4 strings SU0 to SU3. Each string SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to 1 word line WL0. The same applies to the memory cell transistors MC1 to MC 7.

The gates of the plurality of select transistors ST1 in the string SU are commonly connected to 1 select gate line SGD. More specifically, the gates of the plurality of select transistors ST1 in the string group SU0 are commonly connected to the select gate line SGD0. The gates of the plurality of select transistors ST1 in the string group SU1 are commonly connected to the select gate line SGD1. The gates of the plurality of select transistors ST1 in the string SU2 are commonly connected to the select gate line SGD2. The gates of the plurality of select transistors ST1 in the string SU3 are commonly connected to the select gate line SGD3.

The gates of the plurality of select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. In addition, like the select gate lines SGD, the select gate lines SGS may be provided for each string group SU.

Word lines WL0 to WL7, select gate lines SGD0 to SGD3, and select gate line SGS are connected to row decoder 112, respectively.

The bit line BL is commonly connected to any one of the NAND strings NS in each string group SU of each block BLK. Each bit line BL is connected to a sense amplifier 113. For example, the same column address CA is assigned to the NAND string NS connected to the same bit line BL.

The source line SL is shared among a plurality of blocks BLK, for example.

A set of a plurality of memory cell transistors MC connected to a common word line WL within 1 string SU is denoted as a "cell group CU", for example. In other words, the cell group CU is a set of a plurality of memory cell transistors MC that are collectively selected in the writing operation or the reading operation. A page is a unit of data uniformly written into (uniformly read out from) the unit group CU. In addition, the cell group CU may have a storage capacity of 2 pages or more of data according to the number of bits of data stored in the memory cell transistor MC. For example, in the case where the memory cell transistor MC is an SLC (Single Level Cell, single-layer cell) that stores 1-bit data, the memory capacity of the cell group CU is 1 page. Further, for example, in the case where the memory cell transistor MC is TLC (Triple Level Cell, three-layer cell) storing 3-bit data, the memory capacity of the cell group CU is 3 pages. In addition, the number of bits of data that the memory cell transistors MC can store may also be different in each block BLK. For example, the memory cell transistors MC in the user area (blocks BLK 0-BLKn) may also be TLC. The memory cell transistor MC of the ROM fuse area (block BLK_ROM) may also be SLC.

1.1.5 data register and sense Amplifier configuration

Next, an example of the configuration of the data register 114 and the sense amplifier 113 will be described with reference to fig. 4. Fig. 4 is a block diagram of the data register 114 and the sense amplifier 113.

As shown in fig. 4, the sense amplifier 113 includes a plurality of sense amplifier groups SAU provided for each bit line BL. Also, the data register 114 includes a plurality of latch circuits XDL provided for each sense amplifier group SAU. The addresses CA are arranged for the latch circuits XDL.

The sense amplifier set SAU includes, for example, a sense circuit SA, a latch circuit SDL, ADL, BDL, CDL, and a TDL. The sense circuit SA, the latch circuits SDL, ADL, BDL, CDL, and TDL are commonly connected to the corresponding latch circuit XDL via the bus LBUS. In other words, the latch circuit XDL, the sense circuit SA, and the latch circuits SDL, ADL, BDL, CDL and TDL are connected to each other so as to be able to transmit and receive data to and from each other via the bus LBUS.

The sense circuit SA senses data read out to the corresponding bit line BL during a read operation, and determines whether the read data is "0" data or "1" data. In addition, the sense circuit SA applies a voltage to the bit line BL according to the write data during the write operation.

The latch circuit SDL, ADL, BDL, CDL and the TDL temporarily store read data and write data. For example, during a read operation, data may be transferred from the sense circuit SA to any of the latch circuits SDL, ADL, BDL, CDL and TDL. In addition, during the write operation, data can be transferred from the latch circuit XDL to either one of the latch circuits SDL, ADL, BDL, CDL and TDL.

The latch circuit XDL temporarily stores read data and write data. The latch circuit XDL is used for inputting and outputting data between the sense amplifier group SAU and the input-output circuit 101.

The configuration of the sense amplifier unit SAU is not limited to this, and various modifications are possible. For example, the number of latch circuits included in the sense amplifier group SAU can be designed based on the number of bits of data held by 1 memory cell transistor MC.

1.2 Power-on readout action

Next, a power-on read operation will be described. The power-on read operation includes a cell read operation and a set operation. The memory chip 11 can individually perform each of the cell reading operation and the setting operation. In the case of continuously executing the cell reading operation and the setting operation, the operation is also referred to as "normal power-on reading operation" or "full-sequence operation". In the power-on read operation corresponding to the low power consumption mode, the cell read operation is omitted.

The cell read operation is an operation of reading out chip start-up data from the memory cell transistor MC of the block blk_rom and transferring (storing) the read-out chip start-up data to the data register 114 (latch circuit XDL). For example, the sequencer 105 may execute a unit readout action at a timing different from that of the start action according to the control of the CPU 22. In this case, the chip enable data stored in the data register 114 is read out to the memory controller 20. For example, when the memory chip 11 performs a power-on read operation corresponding to the low power consumption mode, the CPU22 transmits chip start data to the memory chip 11. Sequencer 105 causes the chip enable data received from memory controller 20 to be stored in data register 114. Therefore, in the power-on read operation corresponding to the low power consumption mode, the cell read operation is omitted.

The setting operation includes an operation of causing the parameter information register 107, the bad block information register 108, and the bad column information register 109 to store parameter information, bad block information, and bad column information, respectively. More specifically, for example, first, the sequencer 105 resets the parameter information register 107, the bad block information register 108, and the bad column information register 109. Next, the sequencer 105 reads out the chip enable data from the data register 114. Then, the sequencer 105 transfers (stores) the parameter information, the bad block information, and the bad column information to the parameter information register 107, the bad block information register 108, and the bad column information register 109, respectively. For example, when the memory chip 11 performs a power-on read operation corresponding to the low power consumption mode, the sequencer 105 performs a set operation using the chip start data received from the memory controller 20. On the other hand, in the case where the memory chip performs a normal power-on read operation, the set operation is performed using the chip start data read out from the memory cell array 111.

When the CPU22 does not read the chip start-up data, the full-sequence operation is, for example, a normal power-on read operation performed when the memory system 3 is started up.

1.2.1 flow of Power-on readout operation corresponding to Low Power consumption mode

Next, an example of a flow of the power-on readout operation corresponding to the low power consumption mode will be described with reference to fig. 5. Fig. 5 is a flowchart showing a power-on read operation corresponding to the low power consumption mode.

As shown in fig. 5, first, the CPU22 turns on the power of the memory chip 11 (S101). That is, the CPU22 turns on the memory chip 11. After turning on the memory chip 11, the CPU22 starts a start operation (power-on read operation) of the memory chip 11.

When the CPU22 finishes reading the chip start data (yes in S102), that is, when the power-on read operation corresponding to the low power consumption mode is performed, the CPU22 transmits the chip start data to the memory chip 11. Chip enable data received from the memory controller 20 is stored in the data register 114. That is, the CPU22 writes the chip enable data to the data register 114. Hereinafter, the operation of the CPU22 to write the chip enable data to the data register 114 will be referred to as "cache write operation". The cell read operation in the power-on read operation is omitted by the cache write operation.

On the other hand, when the CPU22 does not complete the read of the chip start data (S102_no), the sequencer 105 executes the full-sequence operation (normal power-on read operation). Thus, the sequencer 105 first performs a cell read action. The data register 114 stores the chip enable data read from the block blk_rom.

The sequencer 105 performs a setting action using the chip start data stored in the data register 114 (S105).

The sequencer 105 ends the power-on read operation (S106). After the start-up operation is completed, the memory chip 11 is in a state in which normal operation is possible. For example, sequencer 105 brings ready/busy signal RBn to an "H" level (ready state).

1.2.2 stop operation of memory chip corresponding to Low Power consumption mode

Next, an example of a flow of stopping operation of the memory chip 11 corresponding to the low power consumption mode will be described with reference to fig. 6. Fig. 6 is a flowchart showing a stop operation of the memory chip corresponding to the low power consumption mode.

As shown in fig. 6, first, the CPU22 selects the memory chip 11 to be set in the off state from among the memory chips 11 in the on state and in the standby state, for example (S111).

The CPU22 confirms whether or not the chip start data of the read target memory chip 11 has been completed (S112). For example, the CPU22 executes a read operation of the chip start data of the target memory chip 11 as a preparatory operation for turning the target memory chip 11 off. In other words, the stop operation of the memory chip 11 includes a read operation of the chip start data and an operation of turning off the memory chip 11. At this time, the CPU22 first confirms whether or not the readout of the chip start data has been completed. The timing at which the CPU22 performs the read operation of the chip start data is not limited to that before the memory chip 11 is turned off. The CPU22 can execute a read operation (an operation for confirming whether or not read is completed) of the chip start data at an arbitrary timing with respect to the memory chip 11 in which the ready/busy signal RBn is at the "H" level and the normal operation is not executed.

If the read of the chip start data is not completed (S112_no), the CPU22 causes the target memory chip 11 to execute the cell read operation (S113).

The CPU22 reads out the chip start data from the data register 114 of the target memory chip 11 (S114). Hereinafter, the operation of the CPU22 to read data from the data register 114 will be referred to as "cache read operation". For example, the CPU22 causes the chip start data read out by the cache read-out operation to be stored in the RAM 24.

When the reading of the chip start data is completed (yes in S112), the CPU22 omits S113 and S114.

After reading out the chip start data, the CPU22 turns off the target memory chip 11 (S115).

1.2.3 instruction sequence for full sequence actions

Next, an example of a command sequence of the full-sequence operation will be described with reference to fig. 7. Fig. 7 is a diagram showing a command sequence and a current consumption of the full-sequence operation. In the example shown in fig. 7, the signal DQ and the signal RBn are shown for simplicity of explanation, and the signal CEn, CLE, ALE, WEn and the signal REn are omitted. Hereinafter, for the signal DQ, an instruction is written in a circular frame, an address is written in a quadrangular frame, and data is written in a hexagonal frame. First, in the example shown in fig. 7, the current waveform of the consumption current ICC of the memory chip 11 is collectively shown.

As shown in fig. 7, the CPU22 transmits an instruction "FFh" to the memory chip 11. The instruction "FFh" is an instruction to instruct the execution of the power-on readout operation.

When receiving the command "FFh", the sequencer 105 sets the signal RBn to the "L" level, and executes a normal power-on read operation (full sequence operation). The full-sequence operation includes a standby period Idl, a dummy period Dmy, a reset period Rst, a read period Rd, and a set period St as states.

The standby period Idl is a standby period between the start and the end of the power-on read operation and until the start of the next operation.

The dummy period Dmy is a period set for adjusting the timing of executing the next operation. For example, when the plurality of memory chips 11 simultaneously perform the power-on read operation, the peak value of the consumption current ICC (also abbreviated as "current peak") of each memory chip 11 overlaps, and the maximum consumption current of the memory device 10 increases. In this case, the timing of the current peak can be shifted by changing the length of the dummy period of each memory chip 11. The dummy period Dmy may be omitted.

The reset period Rst is a period during which the reset operation of the parameter information register 107, the bad block information register 108, and the bad column information register 109 is performed. In general, 1 current peak occurs during the reset period Rst due to the reset operation.

The read period Rd is a period during which the cell read operation is performed. During the read period Rd, chip start data is read from the block BLK_ROM. The read-out chip enable data is then stored in the data register 114. In the example shown in fig. 7, 4 current peaks occur during the read period Rd. For example, 2 current peaks are 1 group, corresponding to 1 readout operation. Thus, 4 current peaks represent 2 sensing actions performed. For example, the read operation is performed 2 times by dividing the odd-numbered bit lines BL (hereinafter, referred to as "odd-numbered bit lines BL") and the even-numbered bit lines BL (hereinafter, referred to as "even-numbered bit lines BL"). As a result, the influence of the coupling noise received from the adjacent bit line BL is reduced, and the voltage convergence time of the bit line BL can be reduced. This can speed up the reading operation. For example, the 1 st and 3 rd current peaks are generated when the pump in the voltage generating circuit 110 is started to start applying the voltage to the word line WL. For example, the 2 nd and 4 th current peaks occur when voltages are applied to the word line WL and the bit line BL (odd bit line BL or even bit line BL) selected as the read operation target. The number and timing of the current peaks are arbitrary.

For example, when the read operation of the even bit lines BL and the read operation of the odd bit lines BL are sequentially performed, first, the read result of the even bit lines BL is stored in the latch circuit ADL. Next, the read result of the odd bit line BL is added to the data of the latch circuit ADL. Thereby, the read results (chip start data) of all the bit lines BL are stored in the latch circuit ADL. The data of the latch circuit ADL is transferred to the latch circuit XDL. For example, the latch circuits BDL, CDL, and TDL may be used in the same manner as the latch circuit ADL when the chip start data is 2 or more pages of data, when the chip start data is divided, or the like.

The setting period St is a period during which a setting action is performed. In the example shown in fig. 7, the current peak value is not generated during the set period St.

After the completion of the full-sequence operation, the sequencer 105 sets the signal RBn to the "H" level. Hereinafter, a period during which the sequencer 105 sets the signal RBn to the "L" level and executes the full-sequence operation is referred to as a "period tpro 1".

1.2.4 instruction sequence for Unit read action and cache read action

Next, an example of an instruction sequence of the unit read operation and the cache read operation will be described with reference to fig. 8. Fig. 8 is a diagram showing instruction sequences and consumption currents of the cell read operation and the cache read operation. In the example shown in fig. 8, the signal DQ and the signal RBn are shown for simplicity of explanation, and the signal CEn, CLE, ALE, WEn and the signal REn are omitted. In the example shown in fig. 8, the current waveform of the consumption current ICC of the memory chip 11 during the cell reading operation is also shown.

As shown in fig. 8, the CPU22 transmits instructions "XXh" and "FDh" to the memory chip 11. The instruction "XXh" is a prefix instruction that instructs the setup operation to be omitted (i.e., is limited to the cell readout operation) in the power-on readout operation. The instruction "FDh" is an instruction for instructing the execution of the power-on read operation manually (at a timing other than the start operation).

When receiving the instructions "XXh" and "FDh", the sequencer 105 sets the signal RBn to "L" level, and executes the cell read operation. The cell read operation includes a standby period Idl, a dummy period Dmy, and a read period Rd as states. The cell read operation is a flow of removing the reset period Rst and the set period St from the full-sequence operation described using fig. 7. In the same way as in the full-sequence operation, 4 current peaks occur in the read period Rd.

After the cell read operation is completed, the sequencer 105 sets the signal RBn to the "H" level. Hereinafter, a period in which the sequencer 105 sets the signal RBn to the "L" level and performs the cell read operation is referred to as a "period tpro 2". Since the reset operation and the set operation are omitted, the period tpro 2 is shorter than the period tpro 1.

When receiving the signal RBn of the "H" level, the CPU22 performs a cache read operation. More specifically, the CPU22 first transmits an instruction "05h" to the memory chip 11. Instruction "05h" is an instruction notifying the cache read operation. Next, the CPU22 transmits, for example, 5-cycle addresses ADD (2-cycle column addresses "C1" and "C2" and 3-cycle row addresses "R1", "R2", and "R3") to the memory chip 11. Next, the CPU22 sends an instruction "E0h" to the memory chip 11. Instruction "E0h" is an instruction that indicates execution of a cache read action. When receiving the instruction "E0H", the sequencer 105 transmits the chip enable data "DAT" stored in the data register 114 to the memory controller 20 in a state where the signal RBn is set to "H" level.

1.2.5 instruction sequence of the cache write action and set action

Next, an example of an instruction sequence of the cache write operation and the set operation will be described with reference to fig. 9. Fig. 9 is a diagram showing an instruction sequence and a consumption current of a cache write operation and a set operation. In the example shown in fig. 9, the signal DQ and the signal RBn are shown for simplicity of explanation, and the signal CEn, CLE, ALE, WEn and the signal REn are omitted. In the example shown in fig. 9, the current waveform of the consumption current ICC of the memory chip 11 during the set operation is also shown.

As shown in fig. 9, first, the CPU22 transmits an instruction "85h" to the memory chip 11. Instruction "85h" is an instruction for notifying the memory chip 11 of the execution of the cache write operation. Next, the CPU22 transmits the same address ADD as the cache read operation described using fig. 8. Next, the CPU22 transmits the chip start data "DAT" to the memory chip 11. Next, the CPU22 sends an instruction "15h" to the memory chip 11. Instruction "15h" refers to an instruction indicating execution of a cache write action. In addition, instruction "15h" is omitted.

When receiving the instruction "15H", the sequencer 105 performs a cache write operation in a state where the signal RBn is set to "H" level. Hereinafter, the period from when the sequencer 105 receives the instruction "85h" to when the sequencer 105 ends the cache write operation is referred to as "period tDIN".

Next, the CPU22 transmits instructions "YYh" and "FFh" to the memory chip 11 in order to execute the setting operation. The instruction "YYh" is a prefix instruction indicating omission of the unit reading operation (i.e., limited to the setting operation) in the power-on reading operation.

When receiving the instructions "YYh" and "FFh", the sequencer 105 sets the signal RBn to "L" level, and executes a setting operation. The setting operation includes the standby period Idl, the dummy period Dmy, the reset period Rst, and the setting period St as states. The set operation is a flow of removing the read period Rd from the full-sequence operation described with reference to fig. 7. Like the full sequence operation, rst generates 1 current peak during the reset period. In other words, in the power-on sensing operation corresponding to the low power consumption mode, 1 current peak is generated during the reset period Rst, and no current peak corresponding to the cell sensing operation is generated.

After the end of the set operation, the sequencer 105 sets the signal RBn to the "H" level. Hereinafter, a period in which the sequencer 105 sets the signal RBn to the "L" level and performs the setting operation (power-on read operation corresponding to the low power consumption mode) is referred to as a "period tpro 3". The period tpro 3 is shorter than the periods tpro 1 and tpro 2. The period tDIN is shorter than the read period Rd. Thus, the total period of the period tDIN and the period tpro 3 is shorter than the period tpro 1. That is, the total processing time of the cache write operation and the set operation is shorter than the processing time of the full-sequence operation. In other words, the processing time of the combination of the cache write operation and the power-on read operation corresponding to the low power consumption mode is shorter than the processing time of the normal power-on read operation.

1.3 specific examples of consumption Current for Power-on sense operations of multiple memory chips

Next, a specific example of the consumption current in the power-on/read operation of the plurality of memory chips 11 will be described with reference to fig. 10 to 13. FIG. 10 is a cross-sectional view of a memory device 10 in which memory chips 11_0 to 11_7 are stacked. In the example shown in fig. 10, components irrelevant to the supply of the power supply voltage VCC are omitted for simplicity of description. Fig. 11 is a diagram showing the current consumption in the case where the memory chips 11_0 to 11_7 perform the full-sequence operation. Fig. 12 and 13 are diagrams showing the consumption current in the case where the memory chips 11_0 to 11_7 perform the set operation. The lengths of the dummy periods Dmy in the examples shown in fig. 12 and 13 are different from each other.

First, an example of a cross-sectional structure of the memory device 10 will be described.

As shown in fig. 10, for example, 8 memory chips 11_0 to 11_7 are stacked in the memory device 10. For example, memory chips 11_0 to 11_7 are commonly connected to channel CH0. The power supply voltage VCC is commonly supplied to the memory chips 11_0 to 11_7. More specifically, each memory chip 11 includes, for example, a conductive TSV that electrically connects an electrode pad provided on the upper surface of the chip with an electrode pad provided on the lower surface. The conductive TSVs may be 1 via plug penetrating the memory chip 11, and may also include a plurality of via plugs and wiring layers. Bumps BP are provided between the memory chips 11. The bump BP is made of a conductive material. The conductive TSVs of the memory chips 11_0 to 11_7 are electrically connected via bumps BP. The power supply voltage VCC is applied from the memory chip 11_0 to the memory chip 11_7 to each of the conductive TSVs. That is, the power supply voltage VCC is supplied to each memory chip 11. In this configuration, the combined current of the consumption currents ICC of the memory chips 11 is referred to as a consumption current icc_total.

Next, the consumption current icc_total in the case where the memory chips 11_0 to 11_7 perform a normal power-on read operation (full-sequence operation) will be described.

As shown in fig. 11, when the memory chips 11_0 to 11_7 perform the full-sequence operation, the CPU22 changes the length of the dummy period Dmy of each memory chip 11. Thus, the CPU22 can shift the current peak value of each memory chip 11. However, in the case of the full-sequence operation, a plurality of current peaks are generated. For example, as described with reference to fig. 7, in the case of the full-sequence operation, 1 current peak is generated in the reset period Rst, and 4 current peaks are generated in the read period Rd. In the example shown in fig. 11, the length of the dummy period Dmy of each memory chip is adjusted so that the current peaks generated in the reset period Rst do not overlap. However, during the readout period Rd, the current peaks of the plurality of memory chips 11 overlap. In the case of the full-sequence operation, it is difficult to prevent the current peaks of the plurality of memory chips 11 from overlapping. Therefore, the maximum value of the consumption current icc_total is greatly increased compared to the consumption current ICC of 1 memory chip 11. When the maximum value of the consumption current icc_total must be equal to or less than a fixed value, the length of the dummy period Dmy of each memory chip is adjusted to be longer so that the current peaks of the plurality of memory chips 11 do not overlap, and the total sequence operation time becomes longer.

Next, the consumption current icc_total in the case where the memory chips 11_0 to 11_7 perform the power-on read operation (set operation) corresponding to the low power consumption mode will be described.

As shown in fig. 12, when the memory chips 11_0 to 11_7 perform the set operation as the power-on read operation corresponding to the low power consumption mode, 1 current peak occurs in each reset period Rst. Since the current peak value of each memory chip 11 is 1, it is easy to adjust the length of the dummy period Dmy of each memory chip 11 so that the current peak values of each memory chip 11 do not overlap. This suppresses an increase in the consumption current icc_total. In addition, in the case of the power-on read operation corresponding to the low power consumption mode, it is not necessary to consider the overlapping of the current peak generated in the reset period Rst and the current peak generated in the read period Rd described with reference to fig. 11. Therefore, as shown in fig. 13, the adjustment range of the dummy period Dmy can be made larger than the full-sequence operation to disperse the current peak value of the reset period Rst of each memory chip 11.

1.4 effects of the present embodiment

The configuration of the present embodiment can improve the processing capability of the memory system. This effect will be described in detail.

In the low power consumption mode, on/off control of the memory chip 11 is performed. In this case, the power-on read operation is performed in the memory chip 11 every time the memory chip 11 is put into the on state. In order to improve the processing capacity of the memory system, it is necessary to shorten the processing time for the power-on read operation.

In contrast, in the configuration of the present embodiment, when the memory chip 11 is in the on state, the CPU22 can read out the chip start data from the memory chip 11. In the case of performing the power-on read operation corresponding to the low power consumption mode, the CPU22 may transmit the chip start data read in advance to the memory chip 11. That is, the CPU22 may write the chip enable data into the data register 114 of the memory chip 11. The memory chip 11 may perform a setting action using the chip start data received from the memory controller 20. Thus, the memory chip 11 can omit the cell read operation of the chip start data. This shortens the processing time of the power-on read operation corresponding to the low power consumption mode. Thus, the processing capacity of the memory system can be improved.

Further, in the configuration of the present embodiment, it is possible to prevent the generation of a current peak caused by the cell reading operation in the power-on reading operation corresponding to the low power consumption mode. This suppresses an increase in current consumption during the power-on read operation.

Further, in the configuration of the present embodiment, when the power-on read operation corresponding to the low power consumption mode is performed in the plurality of memory chips 11, the timing of the current peak accompanying the reset operation is shifted, whereby an increase in the maximum consumption current can be suppressed.

Further, in the configuration of the present embodiment, the cell reading operation may be omitted in the power-on reading operation corresponding to the low power consumption mode. Therefore, the number of times of execution of the read operation in the memory cell array 111 can be reduced. Thus, the read disturb caused by the increase in the number of times of reading can be suppressed, and erroneous reading of the chip start data can be suppressed. Thus, the reliability of the memory system can be improved.

2. Embodiment 2

Next, embodiment 2 will be described. In embodiment 2, 3 examples of the configuration of the memory system 3 different from embodiment 1 are shown. Hereinafter, differences from embodiment 1 will be mainly described.

2.1 example 1

First, example 1 will be described.

2.1.1 construction of memory System

First, the configuration of the memory system 3 will be described with reference to fig. 14. Fig. 14 is a block diagram showing an example of the overall configuration of the data processing apparatus 1.

As shown in fig. 14, the point different from embodiment 1 is that the chip start data is not stored in the RAM 24. Other configurations of the memory controller 20 are the same as those of embodiment 1.

2.1.2 formation of memory chips

Next, the structure of the memory chip 11 will be described with reference to fig. 15. Fig. 15 is a block diagram showing a basic configuration of the memory chip 11. In the example shown in fig. 15, part of the connection between the constituent elements is shown by an arrow line. However, the connection between the components is not limited to this.

As shown in fig. 15, the point different from embodiment 1 is that the memory chip 11 includes a RAM120. Other configurations are the same as those of embodiment 1.

RAM120 is volatile memory. The RAM120 is DRAM, SRAM, or the like. The RAM120 of this example stores chip start data (hereinafter, referred to as "other chip start data") of the other memory chip 11.

2.1.3 example of on/off control of a memory chip in Low Power consumption mode

Next, an example of on/off control of the memory chip 11 in the low power consumption mode will be described with reference to fig. 16. Fig. 16 is a diagram showing an example of on/off control of the memory chip 11.

As shown in fig. 16, for example, the CPU22 performs on/off control of the memory chip 11 for each channel CH. In this case, the CPU22 reads out the chip start data of each memory chip 11 of the channel CH0 before turning off the power supply of the memory chip 11 of the channel CH 0. Further, the CPU22 causes the chip start data to be stored as other chip start data in the RAM120 of the memory chip 11 of the channel CH 1. Thereafter, the CPU22 turns off the power supply of the memory chip 11 of the channel CH 0.

When the power supply of the memory chip 11 of the channel CH0 is turned on, the CPU22 reads out other chip start data from the memory chip 11 of the channel CH 1. Next, the CPU22 transmits corresponding chip start data to the memory chip 11 of the channel CH 0. Thereafter, each memory chip 11 performs a power-on read operation corresponding to the low power consumption mode.

2.2 example 2

Next, example 2 will be described. In example 2, a structure of the memory chip 11 different from that in example 1 will be described with reference to fig. 17. Fig. 17 is a block diagram showing a basic configuration of the memory chip 11. In the example shown in fig. 17, part of the connection between the constituent elements is shown by an arrow line. However, the connection between the components is not limited to this.

As shown in fig. 17, a point different from example 1 is that other chip start data is stored in a block BLK of the user area instead of providing the RAM120 in the memory chip 11. In the example shown in fig. 17, other chip start-up data is stored in the block BLK0, but any of the blocks BLK0 to BLKn of the user area may be used to store other chip start-up data. In addition, in order to increase the speed of data reading and to improve the reliability, the memory cell transistor MC for storing the chip start-up data is preferably SLC.

Other constitution and operation are the same as those of example 1.

2.3 example 3

Next, example 3 will be described. In example 3, a case where the chip start data is encrypted will be described with reference to fig. 18. Fig. 18 is a block diagram showing a basic configuration of the memory chip 11. In the example shown in fig. 18, part of the connection between the constituent elements is shown by an arrow line. However, the connection between the components is not limited to this.

As shown in fig. 18, the memory chip 11 of this example includes an encryption circuit 130 and a decoding circuit 131. Other configurations are the same as those of embodiment 1.

The encryption circuit 130 performs encryption processing of the chip enable data stored in the data register 114. For example, in a cache read action of the chip enable data, sequencer 105 sends the encrypted chip enable data to memory controller 20.

The decoding circuit 131 decodes (decrypts) the encrypted chip enable data. For example, in a cache write action of the chip enable data, the memory chip 11 receives encrypted chip enable data from the memory controller 20. Sequencer 105 causes the chip enable data decoded by decoding circuit 131 to be stored in data register 114.

2.4 effects of the present embodiment

The same effects as those of embodiment 1 can be obtained by the configuration of this embodiment.

Further, in the configuration of example 1 or example 2 of the present embodiment, other chip start data may be stored in the memory chip 11. Thereby, the storage capacity of the RAM24 in the memory controller 20 can be reduced.

Further, in the configuration of example 3 of the present embodiment, the chip enable data may be encrypted. Thus, the user can be prevented from editing the chip start data. Thus, malfunction of the memory chip 11 due to the change of the chip start data can be suppressed. Thereby, the reliability of the memory chip 11 can be improved.

In addition, the 1 st or 2 nd and the 3 rd examples may be combined. That is, the encrypted chip start data may also be stored in the other memory chip 11.

3. Embodiment 3

Next, embodiment 3 will be described. In embodiment 3, 2 examples of the configuration of a command sequence different from that of embodiment 1 are shown. Hereinafter, differences from embodiment 1 will be mainly described.

3.1 st example 1

First, example 1 will be described. In example 1, a description will be given of an instruction sequence of a cache write operation different from that of embodiment 1 with reference to fig. 19. Fig. 19 is a diagram showing an instruction sequence of the cache write operation and the set operation. In the example shown in fig. 19, the signal DQ and the signal RBn are shown for simplicity of explanation, and the signal CEn, CLE, ALE, WEn and the signal REn are omitted.

As shown in fig. 19, the CPU22 transmits the instruction "ZZh" before transmitting the instruction "85h" in the cache write operation. Instruction "ZZh" is a prefix instruction indicating parameter setting. For example, the parameter of the memory chip 11 before performing the cache write action of the chip start data is a preset value at the time of shipment of the product. For example, when it is desired to speed up the cache write operation (data input operation to the memory chip 11) as compared with the case of using the preset value, the CPU22 transmits the instruction "ZZh". Thereby, the memory chip 11 performs initial parameter setting necessary for high speed. In addition, in the case where the parameter of the preset value of the memory chip 11 is set so that the cache write operation can be speeded up, the instruction "ZZh" may be omitted from the CPU 22. Sequencer 105 sets the parameters when it receives instruction "ZZh". The transmission of the signal DQ after the command "85h" is the same as that of fig. 9 of embodiment 1.

3.2 example 2

Next, example 2 will be described. In example 2, a case where data is transmitted a plurality of times in a cache write operation will be described with reference to fig. 20. Fig. 20 is a diagram showing an instruction sequence of the cache write operation and the set operation. In the example shown in fig. 20, the signal DQ and the signal RBn are shown for simplicity of explanation, and the signal CEn, CLE, ALE, WEn and the signal REn are omitted.

As shown in fig. 20, in the cache write operation, the CPU22 first transmits the instruction "85h" and the address ADD, as in fig. 9. Next, the CPU22 transmits the 1 st chip start data "DAT1" to the memory chip 11. Next, the CPU22 sends an instruction "XAh" to the memory chip 11. The instruction "XAh" is an instruction to issue an instruction in such a manner that data of the latch circuit XDL is sent to the latch circuit ADL of the sense amplifier 113 after the cache write operation is performed. When receiving the instruction "XAh", the sequencer 105 sends the 1 st chip enable data to the latch circuit ADL via the data register 114. After the instruction "XAh", the CPU22 transmits the 2 nd chip start data "DAT2" to the memory chip 11. Next, the CPU22 sends an instruction "15h" to the memory chip 11. Sequencer 105, when receiving instruction "15h", causes the 2 nd chip enable data to be stored in data register 114 (latch circuit XDL). The power-on read operation corresponding to the low power consumption mode is the same as that of fig. 9.

In this example, the case where the chip start data is transmitted 2 times has been described, but the number of times of transmission of the chip start data may be 3 or more. For example, in the case of transmitting the chip start data 3 times, the memory chip 11 may cause the latch circuits XDL, ADL, and BDL to store the chip start data.

3.3 effects of the present embodiment

In the configuration of example 1 of the present embodiment, the memory chip 11 can set parameters in the cache write operation before the set operation is performed. Thus, malfunction due to setting using the preset value can be suppressed. Thereby, the reliability of the memory system 3 can be improved.

Further, in the configuration of example 2 of the present embodiment, the CPU22 can transmit the chip start data a plurality of times during the cache write operation of the chip start data. That is, when the chip start data is 1 page or more, the chip start data can be transmitted in multiple times. Thus, the data amount of the chip start data can be increased compared with 1 page data. That is, the chip start-up data is easily expanded. In this case, in the power-on read operation corresponding to the low power consumption mode, the cell read operation is omitted. Therefore, an increase in the processing time of the power-on read operation and an increase in the maximum consumption current in the case of performing the power-on read operation in the plurality of memory chips 11 can be suppressed.

In addition, example 1 and example 2 of embodiment 3 may be combined. Furthermore, embodiment 3 may be combined with embodiment 2 in example 1 or example 2.

4. Embodiment 4

Next, embodiment 4 will be described. In embodiment 4, in the power-on read operation corresponding to the low power consumption mode, 2 cases will be described in which the chip start data is updated. For example, it is preferable to update the information of the chip start data due to a change in the state of the memory chip 11 caused by degradation of the memory cell transistor MC or the like. In this case, the chip start data is updated. Hereinafter, differences from embodiment 1 will be mainly described.

4.1 1 st example 1

First, example 1 will be described with reference to fig. 21. In example 1, a case will be described in which an overwrite operation of update data is performed on chip start data stored in the data register 114. Fig. 21 is a flowchart showing a power-on read operation corresponding to the low power consumption mode.

As shown in fig. 21, as in fig. 5, the CPU22 transmits chip start data to the memory chip 11 in S103. That is, the CPU22 performs a cache write action of the chip start data. Also, after S103, the CPU22 performs updating of the chip start data stored in the data register 114 (S120). More specifically, the CPU22 performs a cache write action of update data, i.e., an overwrite action of chip-initiated data stored in the data register 114. Thus, in the flow shown in fig. 21, the instruction set of the cache write operation of the chip start data ("85 h", address "ADD", chip start data "DAT", and "15 h"), and the instruction set of the cache write operation of the update data ("85 h", address "ADD", update data "DAT", and "15 h") are transmitted from the memory controller 20 to the memory chip 11. The data length of the update data is arbitrary. The update data may be 1 page data or may be shorter data. In other words, the data of all the latch circuits XDL of the data register 114 may be updated, or the data of a part of the latch circuits XDL may be updated.

The processing after the data update (S120) is the same as fig. 5 of embodiment 1.

4.2 example 2

Next, example 2 will be described with reference to fig. 22. In example 2, a case will be described in which the CPU22 updates the chip start data stored in the RAM24 or the like and transmits the updated chip start data to the memory chip 11. Fig. 22 is a flowchart showing a power-on read operation corresponding to low power consumption.

As shown in fig. 22, when the read of the chip start data is completed in S102 (yes in S102), the CPU22 updates the chip start data stored in the RAM24 (S120). In S103, the CPU22 transmits updated chip start data to the memory chip 11. Thus, in the flow shown in fig. 22, the instruction set of the cache write operation of the updated chip start data is transmitted from the memory controller 20 to the memory chip 11. Other operations are the same as those of fig. 5 of embodiment 1.

4.3 effects of the present embodiment

Further, in the configuration of the present embodiment, the CPU22 can update the chip start data. Thus, the chip start-up data can be optimized. Thereby, the reliability of the memory system 3 can be improved.

Embodiment 4 is also applicable to embodiments 2 and 3.

5. Embodiment 5

Next, embodiment 5 will be described. In embodiment 5, a case where the memory chip 11 is a NOR flash memory 700 will be described. The NOR flash memory 700 is a nonvolatile semiconductor memory device capable of random access. Hereinafter, differences from embodiment 1 will be mainly described.

5.1 constitution of NOR type flash memory

An example of the structure of the NOR flash memory 700 is described with reference to fig. 23. Fig. 23 is a block diagram showing a basic configuration of a NOR-type flash memory 700.

As shown in fig. 23, the NOR flash memory 700 includes a memory cell array 701, a row control circuit 702, a column control circuit 703, an address register 704, a data buffer 705, an input/output shift register 706, a voltage generation circuit 707, and a sequencer 708.

The memory cell array 701 includes a plurality of memory cells (memory cell transistors) MTx. In the NOR flash memory 700, the gate of each memory cell MTx is connected to a corresponding 1 word line WL among the plurality of word lines WL. One end of the current path of each memory cell MTx is connected to a corresponding 1 bit line BL among the plurality of bit lines BL. The other end of the current path of each memory cell MTx is connected to a source line, for example, to ground. The plurality of memory cells MTx are arranged in a two-dimensional array or a three-dimensional array.

Memory cell MTx is a field effect transistor having a stacked gate structure with a charge storage layer. The charge storage layer may be a floating gate electrode or a charge trapping film.

The row control circuit 702 selects a word line corresponding to address information among the plurality of word lines WL. The row control circuit 702 applies a specific voltage to the selected word line (and the unselected word lines) according to a write sequence, a read sequence, an erase sequence, and the like.

The column control circuit 703 selects a bit line corresponding to address information among the plurality of bit lines BL. The row control circuit 702 applies a specific voltage to the selected bit line (and the unselected bit line) according to the write sequence, the read sequence, the erase sequence, and the like.

The address register 704 temporarily stores address information from the input-output shift register 706. The address register 704 sends address information to the row control circuit 702 and the column control circuit 703.

The data buffer 705 temporarily stores read data from the memory cell array 701 and write data from the input/output shift register 706.

The input-output shift register 706 temporarily stores a signal DQ transferred between the memory cell array 701 and the outside of the NOR-type flash memory 700. The signal DQ may include read data, write data, address information, or the like. The input-output shift register 706 sends address information to the address register 704. The input-output shift register 706 sends the write data to the data buffer 705. The input-output shift register 706 transmits the readout data supplied from the memory cell array 701 to the memory controller 20. The input-output shift register 706 may perform parallel-serial conversion of the signal DQ.

The voltage generating circuit 707 generates a plurality of voltages for a write sequence, a read sequence, and an erase sequence, respectively. The voltage generating circuit 707 supplies the generated voltage to the row control circuit 702, the column control circuit 703, and the like.

The sequencer 708 controls the operation of the entire NOR flash memory 700 based on various control signals such as the reset signal RESETn, the hold signal HOLDn, and the write protect signal Wn.

The NOR flash memory 700 may include other components such as a status register. The status register temporarily stores status signals indicating the internal operation status and the execution result of the operation sequence of NOR flash memory 700.

5.2 effects of the present embodiment

6. Variation and the like

The memory system of the embodiment includes a memory chip (11) including a memory cell array (111), and a memory controller (20) that controls the memory chip. The memory cell array stores 1 st data (chip start-up data) used by the 1 st action (POR) performed at the time of the memory chip start-up. The memory chip does not read out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is received from the memory controller, and reads out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is not received from the memory controller.

By the embodiments, a memory system capable of improving processing capability can be provided.

The embodiments are not limited to the above-described embodiments, and various modifications are possible.

For example, in the embodiment, the memory chip 11 may also include a plurality of memory cell arrays 111. In this case, for example, the memory chip 11 may include a memory cell array 111 allocated to the user area and a memory cell array 111 allocated to the ROM fuse area.

For example, the memory chip 11 may include a compression circuit and an expansion circuit instead of the encryption circuit 130 and the decoding circuit 131 described in embodiment 3 of embodiment 2. In this case, the compression circuit compresses the chip start-up data. The memory chip 11 then transmits the compressed chip enable data to the memory controller 20. Further, the expansion circuit expands the chip start-up data received from the memory controller 20.

Furthermore, in the embodiment, the memory chip 11 may include an ECC circuit. In this case, the ECC circuit performs encoding processing and decoding processing of the chip enable data.

Further, "connected" in the above-described embodiment includes a state in which it is indirectly connected with other objects such as a transistor or a resistor interposed therebetween.

The embodiments are examples, and the scope of the present invention is not limited to these embodiments.

Symbol description

1 data processing apparatus

2 host device

3 memory system

10 memory device

11 memory chip

20 memory controller

Host interface circuit 21

22:CPU

23:ROM

24:RAM

25 buffer memory

ECC circuit 26

27 memory interface circuit

101 input/output circuit

102 logic control circuit

103. 704 address register

104 instruction register

105. 708 sequencer

106 ready/busy circuit

107 parameter information register

108 bad block information register

109 bad column information register

110. 707 Voltage generating Circuit

111. 701 memory cell array

112 row decoder

113 sense amplifier

114 data register

115 column decoder

120:RAM

130 encryption circuit

131 decoding circuit

700 NOR type flash memory

702 row control circuit

703 column control circuit

705 data buffer

706, input/output shift register.

Claims

1. A memory system is provided with:

a memory chip including a memory cell array; a kind of electronic device with high-pressure air-conditioning system

A memory controller controlling the memory chip; and is also provided with

The memory cell array stores 1 st data, the 1 st data being used in a 1 st action performed at the time of the memory chip start-up,

The memory chip does not read out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is received from the memory controller, and reads out the 1 st data from the memory cell array in the 1 st operation when the 1 st data is not received from the memory controller.

2. The memory system of claim 1, wherein

A 1 st period of the 1 st operation when the 1 st data is received from the memory controller is shorter than a 2 nd period of the 1 st operation when the 1 st data is not received from the memory controller.

3. The memory system of claim 2, wherein

The memory chip further includes a register storing parameter information included in the 1 st data,

during the 1 st period, a 1 st peak value of consumption current based on the reset of the register is generated in the memory chip,

during the 2 nd period, the 1 st peak value and the 2 nd peak value of at least 1 of the consumption currents based on the 1 st data read operation from the memory cell array are generated.

4. The memory system of claim 3, which

A plurality of the memory chips are also provided,

in the case where the 1 st operation is performed among the plurality of memory chips, a plurality of 1 st peaks corresponding to the plurality of memory chips, respectively, are generated during the 1 st period, without generating the 2 nd peak.

5. The memory system of claim 1, wherein

The memory chip also includes a sense amplifier connected to the memory cell array and a data register connected to the sense amplifier,

the 1 st data received from the memory controller is stored in the data register.

6. The memory system of claim 5, wherein

The memory controller, in a case where the 1 st data is transmitted to the memory chip, transmits an instruction set indicating writing of the 1 st data to the data register to the memory chip.

7. The memory system of claim 6, wherein

The instruction set includes an instruction indicating parameter setting of the memory chip, an instruction notifying a write operation to the data register, an address, and the 1 st data.

8. The memory system of claim 6, wherein

In the instruction set, the 1 st data is transmitted in multiple times.

9. The memory system of claim 1, wherein

The memory controller transmits update data of the 1 st data to the memory chip after transmitting the 1 st data to the memory chip.

10. The memory system of claim 1, wherein

And the memory controller updates the 1 st data and sends the updated 1 st data to the memory chip.

11. The memory system of any one of claims 1 to 10, wherein

The memory cell array includes a 1 st area storing the 1 st data and a 2 nd area storing the 2 nd data received from the outside.

12. The memory system of any one of claims 1 to 10, wherein

The 1 st data includes parameter information, bad block information, and bad column information,

the memory chip includes a register storing the parameter information, a register storing the bad block information, and a register storing the bad column information.

13. A memory system is provided with:

a 1 st memory chip including a 1 st memory cell array; a kind of electronic device with high-pressure air-conditioning system

A memory controller controlling the 1 st memory chip; and is also provided with

The 1 st memory cell array stores 1 st data, the 1 st data being used in a 1 st operation performed at the start-up of the 1 st memory chip,

the memory controller reads out the 1 st data from the 1 st memory chip at a timing different from the start-up time.

14. The memory system of claim 13, wherein

The memory controller transmits the 1 st data to the 1 st memory chip after reading the 1 st data from the 1 st memory chip, and causes the 1 st memory chip to execute the 1 st operation.

15. The memory system of claim 13 or 14, wherein

The 1 st operation performed after the memory controller reads out the 1 st data from the 1 st memory chip does not include an operation of reading out the 1 st data from the 1 st memory cell array.

16. The memory system of claim 13 or 14, wherein

The memory controller includes a volatile 1 st memory storing the 1 st data.

17. The memory system of claim 13 or 14, which

The memory device further includes a 2 nd memory chip, wherein the 2 nd memory chip includes a 2 nd memory cell array which is nonvolatile, and a 1 st memory which stores the 1 st data.

18. The memory system of claim 13 or 14, which

Also provided is a 2 nd memory chip comprising a non-volatile 2 nd memory cell array,

the 1 st data is stored in the 2 nd memory cell array.

19. The memory system of claim 13 or 14, wherein

The 1 st memory chip contains encryption circuitry,

the memory controller reads out the encrypted 1 st data from the 1 st memory chip.

20. The memory system of claim 13 or 14, wherein

The memory controller reads the 1 st data from the 1 st memory chip during a stop operation of the 1 st memory chip, and then turns the 1 st memory chip off.