JP2000147066A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase in chip area and the number of logical stages due to a dummy flip-flop provided for improved failure detection around a memory. SOLUTION: A memory array part 200 which holds a data, a decoding part 201 for decoding an address input, a control part 202 for controlling writing/ reading, a latching circuit 219 which holds data input synchronously with the clock signal supplied from outside, and an I/O part 203 for inputting/outputting between the memory array part 200 and the outside are provided. Here, the latching circuit comprises a selection circuit for selecting between data input and shift input, and the control part 202 activates a specific memory cell, regardless of the address input at abnormal operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor integrated circuit devices, and more particularly to an improvement in a semiconductor memory device having a memory and a logic circuit.

[0002]

2. Description of the Related Art Generally, a logic circuit comprises combinational circuits 1 and 2 and sequential circuits 41 to 46 as shown in FIG. In recent years, with the miniaturization of the manufacturing process of the semiconductor integrated circuit, the memory 3 can be mounted on the same semiconductor integrated circuit device as the logic circuit.

FIG. 5 is a conceptual diagram of a general logic circuit.
In the figure, reference numerals 1 and 2 denote combinational circuits that constitute a logic circuit. When the input value is determined, the output value is determined without depending on the state of the past circuit. Reference numerals 41 to 46 denote sequential circuits constituting a logic circuit, and the output value is determined not only by the input value but also by the past circuit state. The scan test is based on a synchronous design. In recent circuits, a synchronous design using a D flip-flop is mainstream, and a logic circuit is composed of a combination circuit and a D flip-flop (also a kind of sequential circuit). , A D flip-flop is shown here as a sequential circuit. Among the sequential circuits 41 to 46, the sequential circuits 41 to 43 are provided before the combinational circuit 1, and the sequential circuits 44 to 46 are provided after the combinational circuit 2. Reference numeral 3 denotes a memory, which is provided between the combinational circuits 1 and 2. Scan flip-flops 47 to 49 are D flip-flops. Scan flip-flops 47 and 48 are provided between the combinational circuit 1 and the memory 3, and scan flip-flops 49 are provided between the memory 3 and the combinational circuit 2. , Respectively. A selector 500 selects one of the data read from the memory 3 and the data output from the scan flip-flop 49.

A full scan design is generally used for a logic circuit in order to facilitate generation of a test pattern for performing a fault test. In the full scan design, the sequential circuit is replaced with a scan flip-flop so that it operates as a shift register during the test, and an arbitrary input value is set (shifted) in the combinational circuit by inputting a test value from the outside in a shift operation. In) enabled, the output value of the combinational circuit corresponding to the input value is held by the scan flip-flop (capture),
Thereafter, it is possible to output (shift out) to the outside by a shift operation, thereby enabling automatic generation of a test pattern and improving a failure detection rate.

Hereinafter, the operation of this logic circuit will be described. In normal operation, the selector 500 selects the output of the memory 3. The three sets of inputs of the combinational circuit 1 are supplied with three sets of data from the external inputs indicated by solid lines via the sequential circuits 41 to 43, and the combinational circuit 1 performs a logical operation on these three sets of data. Output three sets of data. The memory 3 is set to a write mode by a mode switching signal (not shown), and the memory 3 inputs two sets of these three sets of data as an address input a and a data input di, and outputs the data to an address determined by the address input a. , Write the given data to the data input di.

Next, when the memory 3 is set to the read mode by a mode switching signal (not shown), the combination circuit 1 outputs three sets of data by the same operation as in the write mode. The memory 3 inputs two sets of these three sets of data as an address input a and a data input di. However, since the read mode is set, the data input di is not valid, and the memory 3 is determined by the address input a. Data is read from the address to be output and the data output do
Output more data. Since the selector 500 is in a normal operation, the selector 500 selects the output of the memory 3, and data from the data output do of the memory 3 is input to the combinational circuit 2.
The combinational circuit 2 performs a logical operation on the data to generate two sets of outputs, and the sequential circuits 44 and 45 receive these two sets of outputs and output them to the outside. Note that, of the three sets of outputs output from the combinational circuit 1, the remaining l sets of outputs are not input to the memory 3 but are output to the outside via the sequential circuit 46.

Next, in a test operation, the sequential circuits 41 to 46 together with the scan flip-flops 47 to 49 form a so-called scan path. At this time, the selector 500 selects the output of the scan flip-flop 49.

That is, as shown by a broken line in FIG. 5, the sequential circuits 41 to 43 synchronize test data generated by, for example, an external test device with a clock (not shown) via a scan input scan in. Shift sequentially. The data shifted in this order by the sequential circuits 41 to 43 are input to the scan flip-flop 47, and the data is transferred to the scan flip-flop 47.
To 49 and the sequential circuits 44 to 46 are sequentially shifted in this order and output from the scan output scan out. As a result, since the response of the combinational circuits 1 and 2 to the data input from the scan input scan in is included in the scan output scan out, it is determined whether or not this matches the expected value, for example, by using the test apparatus described above. Thus, it can be determined whether or not the combinational circuits 1 and 2 are out of order.

That is, the sequential circuits 41 to 43 also output the data sequentially shifted in this order to the combinational circuit 1. The combinational circuit 1 includes the sequential circuits 41 to 43
Performs a logical operation on the data given by, and outputs three sets of the operation results. Two of the sets are output to scan flip-flops 47 and 48, which are sequentially shifted, and the scan flip-flop 49 and the sequential circuit 4
The data is further sequentially shifted by 4 to 46 and output to the outside via a scan output scan out. The scan flip-flop 49 sequentially shifts data to the sequential circuits 44 to 46 and outputs the data to the combinational circuit 2. Combination circuit 2 performs a logical operation on the data given by scan flip-flop 49 and outputs two sets of the operation results. These are input to sequential circuits 44 and 45, and are sequentially shifted by sequential circuits 44 to 46. Output to the outside via a scan output scan out.

With such an operation, the scan output scan
Since out includes the response of the combinational circuits 1 and 2 to the data input from the scan input scan in,
By determining whether or not these match the expected values, it is possible to determine whether or not the combinational circuits 1, 2 have failed.

FIG. 6 shows a circuit configuration of a conventional memory. This memory has a plurality of memory cells 2 for holding data.
, An I / O for interfacing external input / output signals with the memory array unit 200
The control unit 202 includes a unit 203, a decoder unit 201 for activating a memory cell 220 in response to an address input, and a control unit 202 for performing read / write control on a memory.

Memory cell 220 of memory array section 200
221 and 222 are N-type MOS transistors (hereinafter referred to as NMOS), 223 and 224 are inverters, and 225 is a tri-state inverter. NM
The OSs 221 and 222 constitute a 6-transistor type static memory circuit together with the inverters 223 and 224, and the output is output from the tri-state inverter 225 to the IO unit 203.

In the IO section 203, 610 is an IO section.
Circuit, 619 is a latch circuit, 211, 212, 214 are NMOSs, 215 is a buffer, and 216 to 218 are inverters. The NMOSs 211, 212, and 214 activate the data write line DWL of the memory array unit 200 when writing data to the memory array unit 200.

In the control unit 202, 640 is a latch circuit, 241 to 243 are inverters, 245 is NMOS, 650 and 651 are inverters, and 255 is AN.
D circuit (hereinafter, referred to as AND). Also, a0, a
1 is an address input, ncs is a chip select, nwe is a write enable, and nre is a read enable.

Reference numeral 201 denotes a decoder for activating the memory cell 220 in response to an address input, and reference numerals 231 to 233 denote ANDs. The input of the AND 231 receives a combination of a signal obtained by latching the address inputs a0 and a1 or an inverted signal thereof, and the word to be selected (W
ORD0 to WORD3). AN
In addition to the output of AND 231, the input of D 232, the inverted signal of the signal that latched the write enable nwe and the chip select ncs, and the clock signal cl, respectively.
k is connected.

The input of the AND 233 is connected to the output of the AND 231 as well as the inverted signal of the signal which latches the read enable nre and the chip select ncs. Hereinafter, the operation of this conventional memory will be described with reference to FIG.

(Normal Operation) During normal operation, the clock signal c
When lk is “LO”, the output of the inverter 650 becomes “H”.
I ", the NMOS 245 is turned on, and the address inputs a0, a1, the write enable nwe, the read enable nre, and the chip select ncs are fetched by the corresponding latch circuits 640, respectively, and are held by them. Circuit 640
Activates the corresponding word from WORD0 to WORD3 in accordance with the address input latched by.
When the clock signal clk is “LO”, the output of the inverter 651 becomes “HI”, and the NMOS 214 is turned on.
As a result, the data inputs di0 to di3 are taken into the corresponding latch circuits 619, respectively, and are held by these.

Next, the operation of the memory according to the value of the chip select ncs will be described for each case. 1) When the chip select ncs = “HI” (stop) When the chip select ncs is “HI”, the output of the latch circuit 640 corresponding to this is “LO”. Both outputs become "LO". Therefore, the memory cells 220 belonging to any word are not activated. Similarly, AND25
5 also becomes “LO” and the output of the latch circuit 619 of the IO unit 203 is not activated, so that the memory 3 is stopped.

2) Case where chip select ncs = "LO" and write enable nwe = "LO" (write) When chip select ncs is "LO" and write enable nwe is "LO", the corresponding latch circuits 640 become “HI” and AND 255
Is also "HI", the data held in the latch circuit 619 of the IO unit 203 is stored in the memory array unit 20.
Output to 0. On the other hand, the AND 232 has the chip select ncs of “LO” and the write enable nwe of “L”.
Since two inputs among three inputs are "HI" because of "O", the output becomes "HI" only during the period when the clock signal clk is "HI", whereby the NMOS 221 of the memory cell 220 of the corresponding word is output. , 222 are turned ON,
The data output from the latch circuit 619 is stored in the memory cell 2
20. Therefore, for example, address inputs a0,
When a1 is “00” and the data inputs di0 to di3 are “0000”, “0000” is stored in the memory cell 220 of word 0.

3) When chip select ncs = "LO" and read enable nre = "LO" (read) When chip select ncs is "LO" and read enable nre is "LO", the corresponding latch circuits 640 Are both "HI", and the decoder unit 2
01, the output of the AND 233 becomes “HI”, the tristate inverter 225 of the memory cell 220 of the corresponding word is turned ON, and the data held in the memory cell 220 is input to the buffer 215 of the IO circuit 610, It is output from the outputs do0 to do3.
Therefore, for example, when the address inputs a0 and a1 are “00”, the memory cell 220 of the previously written word 0
Is read out.

[0021]

As can be seen from the above description, the memory itself outputs data that has been input in the past, which means that the output depends on the state of the circuit in the past. In a sense, they operate like a sequential circuit, but cannot operate like a shift register.

Therefore, when a semiconductor integrated circuit device mainly including a logic circuit includes a memory, a combinational circuit around the memory cannot detect a failure by full scan.
This is a factor that greatly reduces the failure detection rate. Therefore, dummy flip-flops 47 to 49 used only for the full scan test are inserted around the memory, and the input value can be shifted in and out of the combinational circuit by bypassing the memory.

However, in the above configuration, (1) inserting a dummy flip-flop increases the chip area. (2) The number of logic stages increases due to the presence of the selection circuit for selecting the output from the memory and the shift-in data, and the read access to the original memory is delayed by the selection circuit unnecessary for normal operation. Had the problem that

Japanese Patent Application Laid-Open No. HEI 6-174804 discloses a semiconductor integrated circuit device in which a memory and a logic circuit coexist, which can solve the problem that the chip area is increased for facilitating the test. Semiconductor integrated circuits. This is because when a semiconductor integrated circuit including a memory block and a logic block is scanned, the chip area can be reduced by using the output section of the memory block also as a scan shift register. However, in the technique disclosed in Japanese Patent Application Laid-Open No. 6-174804, since the output latch of the memory block also operates as a shift register, a test signal simply passes through the output section of the memory block. However, it is not possible to capture a test signal into the memory.

The present invention has been made in consideration of the above-mentioned problems of the conventional art, and is intended to realize a full scan of a logic circuit including a memory without increasing the chip area and the number of logic stages. It is an object to provide an integrated circuit device.

[0026]

In order to solve this problem, a semiconductor integrated circuit device according to a first aspect of the present invention decodes a memory array unit for storing data and an address input to the memory array unit. A decoding unit that controls writing and reading of the memory array unit;
A latch circuit that holds a data input in synchronization with an externally applied clock signal, an IO unit that performs input / output between the memory array unit and the outside, and a selection unit that is provided in the latch circuit and selects data input and shift input A control circuit that activates a memory cell specified by an address input value during a normal operation, and activates a specific memory cell regardless of the address input value during an unusual operation. It is what was constituted.

According to a second aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the memory cell is a static type memory cell, and the control unit includes the non-normal memory cell. In operation, both reading and writing of data from and to a memory cell belonging to a specific word in the memory array section are enabled.

According to a third aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the plurality of latch circuits are arranged in a direction along a word of the memory array section. Under the control of the control unit, during the non-normal operation, latching and writing data read from the memory cells belonging to a specific word of the memory array unit one by one in a direction along the word is performed. It is configured to make it possible.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the plurality of latch circuits are arranged in a direction along a word of the memory array section. Under the control of the control unit, at the time of the non-normal operation, data to be simultaneously input to all of the memory cells belonging to a specific word of the memory array unit can be latched and written. .

[0030]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4 and Table 1. (Embodiment 1) In Embodiment 1, a memory used together with a logic circuit is activated by activating a specific memory cell irrespective of the value of an address input except during normal operation. Can be used as a scan line.

FIG. 1 is a diagram showing a concept in a case where a full scan design is performed using the memory of the present embodiment. In order to simplify the explanation, the address of a semiconductor memory device (hereinafter, referred to as a memory) is designated. Assume that 2 bits and data are 4 bits.
In FIG. 1, reference numerals 1 and 2 denote combination circuits, and when the input value is determined, the output value is determined without depending on the state of the past circuit. Reference numerals 41 to 46 denote sequential circuits whose output values are determined not only by input values but also by past circuit states. The scan test is based on a synchronous design. In recent circuits, a synchronous design using a D flip-flop is mainstream, and a logic circuit is composed of a combination circuit and a D flip-flop (also a kind of sequential circuit). , A D flip-flop is shown here as a sequential circuit.
Among the sequential circuits 41 to 46, the sequential circuits 41 to 43 are provided before the combinational circuit 1, and the sequential circuits 44 to 46 are provided after the combinational circuit 2. Reference numeral 3 denotes a memory, which is provided between the combinational circuits 1 and 2 so that a shift register as a data transmission route for a scan path can be formed therein. A sequential circuit 47 is provided between the combinational circuit 1 and the memory 3.

The sequential circuits 41 to 43,
47, 44 to 46 (hereinafter also referred to as scan flip-flops) are turned into scan flip-flops,
From scan input (scan-in) to scan output (s
scan input s of the memory 3 on the way to scan-out)
are connected so as to form a shift register via the scan output Sout (hereinafter referred to as a scan line). The scan flip-flops 41 to 47 are composed of D flip-flops. The D input is selectively held during normal operation, the DT input is selectively held during shift operation, the held value is output from Q, and the inverted value is output from NQ. I do.

FIG. 2 is a diagram showing a circuit configuration of the memory according to the first embodiment. In FIG. 2, reference numeral 200 denotes a memory array unit for holding data, 220 denotes a memory cell, 22
Reference numerals 122 and 222 denote N-type MOS transistors (hereinafter referred to as NMOS).
223, 224 are inverters, and 225 is a tri-state inverter. NMOS 221 and 22
The 2-transistor and the inverters 223 and 224 form a 6-transistor static memory circuit, and the output is output from the tri-state inverter 225 to the IO section 203.

The IO unit 203 interfaces between external input / output signals and the memory array 200. In the IO unit 203, reference numeral 210 denotes an IO circuit,
19 is a latch circuit, 211 to 214 are NMOS, 2
15 is a buffer, and 216 to 218 are inverters. The NMOSs 213 and 214 are controlled so as to be exclusively turned on, and the data of the data inputs di0 to diN are input to the latch circuit 219 of the IO unit 203, or the input of each latch circuit 219 is output from the buffer on the right side thereof. Selection circuit S for selecting whether to obtain from shift input sin
Operate as C. When writing data to the memory array unit 200, the NMOSs 211 to 214 activate the data write line DWL of the memory array unit 200. The so terminal of the IO circuit 210 is connected to the IO circuit 210 adjacent to the left side of each IO circuit 210 by a signal line SL.
, And the so terminal of the IO circuit 210 disposed on the leftmost side in the figure is connected to the sout terminal which is the scan output terminal of the memory 3 by a signal line SLo.
The IO circuit 210 arranged on the rightmost side in the figure is connected to the scan input terminal sin of the memory 3 by the signal line SLi.
Connected to terminal.

Reference numeral 202 denotes a control unit; 240, a latch circuit; 241 to 243, inverters;
245 is an NMOS, and 250 to 255 are AND circuits (hereinafter, referred to as AND). NMOS 244, 24
5 operates as a selection circuit SC for selecting an input of the latch circuit 240 by being controlled to be exclusively turned on by ANDs 253 and 252, and outputs address inputs a0 and a0.
a1, chip select ncs, write enable nw
e. The input of the latch circuit 240 is selected so that either the input of the read enable nre or the input of “LO” by the ground line GL is selected.

The input of the AND 250 is a test mode signal t.
md and the shift enable signal sen. AN
The input of D251 receives the inverted output of AND250 and receives the inverted clock signal clk, and its output is connected to the gate of NMOS 214 of IO section 203. The input of AND 252 receives inverted clock signal clk and inverted test mode signal tmd, and its output is connected to the gate of NMOS 245 of latch circuit 240. The input of the AND 253 receives the clock signal clk after inverting the clock signal clk and the test mode signal tm.
d, the output of which is connected to the NMOS of the latch circuit 240
244 gate.

The input of the AND 254 is connected to the output of the AND 250 and receives the inverted clock signal clk, and the output is connected to the gate of the NMOS 213 of the IO circuit 210. Reference numeral 201 denotes a decoder unit for activating the memory cell 220 in accordance with an address input, and reference numerals 231 to 233 denote ANDs. An input of the AND 231 is connected to a word (WORD0 to WORD3) to be selected by a combination of a signal obtained by latching the address inputs a0 and a1 or an inverted signal thereof. AND232
In addition to the output of the AND 231, the inverted signal of the signal that latches the write enable nwe and the chip select ncs and the clock signal clk are connected to the input of the AND gate 231. The input of AND 233 is the output of AND 231,
Read enable nre and chip select ncs
Are connected to each other. Hereinafter, the operation of the memory according to the first embodiment will be described with reference to FIGS.

(Normal Operation) FIG. 3 is a diagram showing a normal operation of the memory according to the first embodiment. Table 1 is a table showing the operation of the selection circuit in the latch circuit of the memory according to the first embodiment.

[0039]

[Table 1]

In Table 1, "*" indicates so-called don't care.

At the time of normal operation, as shown in the second row of Table 1, the test mode signal tmd is "LO", so that the output of the NAND 250 of the control unit 202 is "LO",
As a result, the outputs of the NANDs 253 and 254 are always “LO”, so that the NMOSs 244 and 213
It becomes F. On the other hand, the outputs of the NANDs 251 and 252 become "HI" when the clock signal clk is "LO". At this time, the NMOSs 245 and 214 are turned on, and the address inputs a0 and a1, chip select ncs, write enable nwe and read enable nre correspond. , Respectively. Decoder section 2
01 activates the corresponding word in accordance with the latched address inputs a0 and a1. Further, the data inputs di0 to di3 when the clock signal clk is “LO” are respectively taken into the corresponding latch circuits 219 and held by these.

Next, what operation the memory performs in accordance with the value of the chip select ncs will be described for each case. 1) When chip select ncs = “HI” (stop) When the chip select ncs is “HI”, the output of the corresponding latch circuit 240 becomes “LO”, and the outputs of the ANDs 232 and 233 of the decoder unit 201 become “LO”. LO ", and the memory cells 220 belonging to any of the words (WORD0 to WORD3) are not activated. Similarly, the output of the AND 255 of the control unit 202 also becomes “LO”,
Since the output of the latch circuit 219 of the O section 203 is not activated, the memory 3 is stopped.

2) When chip select ncs = "LO" and write enable nwe = "LO" (write) When chip select ncs is "LO" and write enable nwe is "LO", the corresponding latch circuit 240
Are both "HI", the output of AND 255 is also "HI", and the latch circuit 219 of the IO unit 203
Is output to the memory array unit 200. On the other hand, AND232 sets the chip select ncs to “L”.
O ”and the write enable nwe is“ LO ”,
Since the outputs of the corresponding latch circuits 240 are both "HI", the output becomes "HI" only while the clock signal clk is "HI", whereby the NMOSs 221 and 222 of the memory cell 220 belonging to the corresponding word are output. Is turned ON, and the data output from the latch circuit 219 is stored in the memory cell 220. Therefore, for example, when the address input is “00” and the data input is “0000”, “0000” is stored in the memory cell 220 of word 0.

As shown in FIG. 3, when the address input is "01" and the data input is "0001", "0001" is stored in the memory cell 220 of word 1, and the address input is "10" and When the data input is “0010”, “0010” is stored in the memory cell 220 of word 2, and when the address input is “11” and the data input is “0011”, “0011” is stored in the memory cell 220 of word 3 Is stored.

3) When chip select ncs = "LO" and read enable nre = "LO" (read) When chip select ncs is "LO" and read enable nre is "LO", the corresponding latch circuit 240
Are both "HI", the output of AND 233 is "HI". Thereby, the tri-state inverter 22 of the memory cell 220 belonging to the corresponding word
5 is turned ON, the data held in the memory cell 220 is input to the buffer 215 of the IO circuit 210, and is output from the outputs do0 to do3 of the memory. Therefore, for example, when the address input is “00”, the value “0000” of the memory cell 220 of word 0 previously written is read.

As shown in FIG. 3, when the address input is "01", the value "0001" of the previously written word 1 memory cell 220 is read, and when the address input is "10". The value “0010” of the previously written word 2 memory cell 220 is read, and when the address input is “11”, the value “0011” of the previously written word 3 memory cell 220 is read. .

(Test Operation 1: Shift Operation) FIG. 4 is a diagram showing an operation at the time of testing the memory of the present embodiment. During the shift operation, as shown in the fourth row of Table 1, the test mode signal tmd is “HI” and the shift enable signal se is
n becomes “HI”, so that the NAND 25 of the control unit 202
0 becomes "HI", thereby the NAND 25
Since the output of 2,251 is always "LO", the NMOS
Both 245 and 214 are OFF. On the other hand, NAND
Since the output of the test mode signal tmd is “HI” and the output of the AND 250 is “HI”, the outputs of 253 and 254 are “H” when the clock signal clk is “LO”.
At this time, both the NMOSs 244 and 213 are turned ON, and all the latch circuits 240 of the control circuit 202 are turned on.
Are input with “LO”, and these are held. Therefore, the output of the latch circuit 240 holding the chip select, the read enable and the write enable becomes “HI”, and the chip select, the read and the write are activated, and the decoder unit 201 is activated.
Activates word 0 of the memory array unit 200 irrespective of the value actually input to the address inputs a0 and a1.
The latch circuit 219 of the IO unit 203 holds data input from the si terminal when the clock signal clk is “LO”.
Since the output of ND 255 is “HI”, the held value is output to memory array unit 200. The memory cell 220 of word 0 stores the output from the latch circuit 219 in synchronization with the next clock signal clk becoming “HI”, and outputs the output to the buffer 215 of the IO circuit 210 at the same time. That is, if the clock signal clk is “HI”, the test mode signal tmd and the shift enable signal se
NMOS 245, 244, 214, 2 irrespective of the value of n
13 is OFF, the outputs of the NANDs 252, 253, 254, and 251 become "LO" as shown in the first row of Table 1, and all the latch circuits 24 of the control unit 202 are turned off.
0 input and all the latch circuits 219 of the IO unit 203
Is interrupted, so that when the clock signal clk is already “LO”, the latch circuit 21 of the IO unit 203
9, the input data held by the latch circuit 240 of the control circuit 202.
0 and a1 are both written to “LO”, that is, the memory cell 220 of word 0.

Therefore, for example, the memory cell 2 of word 0
20 is "1111" and the input data at the sin terminal of the memory is "0", the memory cell 2 of word 0 is synchronized with the next clock signal clk becoming "HI".
The value of 20 is shifted by 1 bit to “0111”. Therefore, each time the clock signal clk changes from “LO” to “HI”, the value of the memory cell 220 of word 0 is shifted one bit at a time.

(Test Operation 2: Capture Operation) At the time of the capture operation, as shown in the third row of Table 1, the test mode signal tmd is "HI" and the shift enable signal sen is "LO". AND2 of 202
50 becomes “LO” and the NANDs 252 and 254
Output is always “LO” and the NMOSs 245 and 213
Becomes OFF. On the other hand, the NANDs 253 and 251 become “HI” when the clock signal clk is “LO”, and NM
The OSs 244 and 214 are turned ON, and all “LO” is input to the latch circuit 240 of the control unit 202 and held.
Therefore, the output of the latch circuit 240 holding the chip select, read enable and write enable becomes “HI”, the chip select, read and write are activated, and the decoder unit 201 receives the address input a.
Word 0 is activated regardless of the values of 0 and a1. Since the NMOS 214 is ON, the IO unit 20
The three latch circuits 219 hold data input from the data inputs di0 to di3 when the clock signal clk is “LO”, and output the data to the memory array unit 200. The memory cell 220 belonging to the word 0 stores the output from the latch circuit 219 in synchronization with the next clock signal clk becoming “HI”, and at the same time, the IO circuit 2
Output to ten buffers 215. Therefore, regardless of the address input, the data inputs di0 to di3
Is stored in the memory cell 220 of word 0.

Therefore, as shown in FIG.
Every time the clock signal clk changes from “LO” to “HI” by the in operation, the value of the memory cell 220 of word 0 changes from “1111” to “1111” regardless of the values of the addresses a0 and a1 and the data inputs di0 to di3. 0111 ",
“1011”, “1011”, “0101”, “001”
The value is sequentially shifted by one bit each at 0. Then, by the capture operation, the value “1010” of the data inputs di0 to di3 is stored in the memory cell 220 of word 0 regardless of the address value.

Further, by the shift-in operation,
Each time the clock signal clk changes from “LO” to “HI”, addresses a0 and a1 and data inputs di0 to di0 are input.
3, the value of the memory cell 220 of word 0 changes from “1010” to “0101”, “0010”, “0”.
001 "and" 0000 "are sequentially shifted one bit at a time.

By connecting the semiconductor integrated circuit device of the first embodiment thus configured on a scan line as shown in FIG. 1, that is, the output of the scan register 47 is scanned by the memory 3. By connecting the scan output sout of the memory 3 to the DT input of the sequential circuit 44 while being connected to the input sin, an arbitrary value can be set to the outputs do0 to do3 of the memory by executing the shift operation of the memory 3. Therefore, the dummy flip-flop 49 and the selector 500, which are conventionally required, are not required. Further, by connecting the output of the combinational circuit 1 only to the data input di of the memory 3, the memory 3 executes the capture operation, thereby storing the values of the data inputs di0 to di3 in the memory, and subsequently performing the shift operation to store the external data. Therefore, the dummy flip-flop 48, which is conventionally required, is not required.

As described above, according to the first embodiment, the ANDs 250 to 254 and the NMOS 21
3 and 244, and among the memory cells along a specific word of the memory 3, the input of the latch circuit corresponding to each memory cell is connected to the buffer circuit corresponding to the adjacent memory cell on one side. A signal line SL for inputting and outputting data so as to be obtained from the output is provided in the IO unit, and a ground line GL for grounding the input of the latch circuit of the control unit is provided. Memory cell can be operated as a shift register, a scan flip-flop can be formed by the data input latch circuit and the memory cell, and the memory input belonging to a specific word inside the memory Dummy flip-flow, which was necessary in the past, Flop and the selection circuit is not necessary, it becomes possible to reduce the circuit area and hence the chip area can be realized to reduce the number of logic stages.

That is, the circuits added to the memory to realize the above functions are AND250 to 254 and NMOS
213, 244 and only the signal line SL and the ground line GL, which are very small with respect to the area of the memory itself, have almost no influence, and are eliminated by adding them. Step 4
Since the circuit scale of the circuits 8, 49 and the selection circuit 500 is generally larger than that of the added circuit, the circuit area and, consequently, the chip area can be reduced.

This is because, for example, if the memory data is n bits and the address is m bits, the additional circuit is A
5 NDs (AND 250 to 254) and NMOS
(N + m + 3) (n is an NMOS 24 for address grounding)
Reference numerals 4 and m are NMOSs 213 and 3 for shift data input, NMOSs 244 for chip select, read enable and write enable ground, and six inverters (the inverted inputs of ANDs 251 to 254 are regarded as inverters). As can be seen from the configuration example of the AND shown in (a) and the configuration example of the inverter shown in FIG. 7B, (PMOS × 2 + NMOS × 2) × 5 + NMOS × (n
+ M + 3) + (PMOS + NMOS) × 6 = PMOS ×
16 + NMOS × (n + m + 19)

On the other hand, the circuit to be deleted is 2m D flip-flops (scan flip-flops 48 and 4).
9), 2n NMOSs (constituting the selection circuit 500), and 2 inverters (inverters 650 and 65)
1), which is a configuration example of the D flip-flop shown in FIG. 7 (f), a configuration example of the tri-state inverter shown in FIG. 7 (c) included therein, and a configuration of the transfer gate shown in FIG. 7 (e). As can be seen from the example and the configuration example of the selector (selection circuit) shown in FIG. 7D, (PMOS × 11 + NMOS × 11) × 2m + NMOS
× 2n + (PMOS + NMOS) × 2 = PMOS × (2
2m + 2) + NMOS × (22m + 2n + 2), and if the memory configuration is 32 bits × 64 words, n = 32 and m = 6, and the number of circuits to be deleted is much more than the number of circuits to be added. It can be seen that the chip area can be reduced.

As can be understood from the above description, in the description of the operation of the present embodiment, the address is 2 bits and the data is 4 bits, but the present invention is not limited to this case. Furthermore, the address at the time of the test operation is set to “00”. However, the present invention is not limited to this, and an arbitrary value can be similarly realized. Further, the selection circuit formed inside the memory is constituted by an NMOS transfer gate, but is not limited to this.
A circuit can similarly be realized. Further, the memory cell is not limited to the six-transistor type. Although the reading of the memory cell is performed by the tri-state inverter 225, as shown in FIG. 8, an NMOS 226 may be used instead.

Further, as shown in FIG. 9, a tri-state inverter 227 for inputting a read enable signal in both phases may be used. However, in this case, the positive-phase read enable signal is transmitted to the
The output of D233 is used as it is, and the inverted read enable signal is obtained by inverting the output of AND233 of the decoder unit 201 by the inverter 234, or
A NAND is provided in place of D233, and a negative phase read enable signal uses the output of the NAND of the decoder unit 201 as it is, and a positive phase read enable signal is this NAN.
The output of D may be inverted by an inverter and used.

Further, a so-called dual-port memory or multi-port memory may be provided by providing two or more tri-state inverters (or NMOSs) for reading data from these memory cells for each memory cell. And furthermore, the word direction,
That is, a specific 1 along the row direction in the memory array section.
Although the memory cells for rows can be operated as shift registers, memory cells for one specific column along the column direction may be operated as shift registers.

[0060]

As described above, according to the semiconductor memory device of the present invention, a memory array unit for storing data,
A decoding unit for decoding an address input to the memory array unit, a control unit for controlling writing and reading of the memory array unit, a latch circuit for holding a data input in synchronization with an externally supplied clock signal, and the memory array An IO section for inputting and outputting between the section and the outside; and a selection circuit provided in the latch circuit for selecting a data input and a shift input. The control section is designated by a value of an address input during a normal operation. The memory flip-flop is formed by the data input latch circuit and the memory cell because the memory cell is activated and the specific memory cell is activated during the non-normal operation regardless of the value of the address input. This eliminates the need for dummy flip-flops and selection circuits, which were required in the past, and reduced chip area. Reduction of the fine logic stages is an effect that can be achieved.

According to the semiconductor integrated circuit device of the second aspect of the present invention, in the semiconductor integrated circuit device of the first aspect, the memory cell is a static type memory cell, and the control unit includes: At the time of the non-normal operation, the memory array section is configured so that both reading and writing of data can be performed with respect to the memory cells belonging to a specific word. It is possible to operate as a register, and a scan flip-flop can be formed by a data input latch circuit and a memory cell. Therefore, a dummy flip-flop and a selection circuit, which are conventionally required, become unnecessary, and the chip area is reduced. This has the effect of reducing the number of logic stages and the number of logic stages.

According to a third aspect of the present invention, in the semiconductor integrated circuit device of the first aspect, a plurality of the latch circuits are arranged in a direction along a word of the memory array section. Under the control of the control unit, during the non-normal operation, data read from memory cells shifted one by one in the direction along the word is latched and written to memory cells belonging to a specific word in the memory array unit. So that it is possible to
A memory cell can be operated as a shift register, and a scan flip-flop can be formed by a data input latch circuit and a memory cell, thereby eliminating the need for a dummy flip-flop and a selection circuit, which were conventionally required. This has the effect of reducing the chip area and the number of logic stages.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device of the first aspect, a plurality of the latch circuits are arranged in a direction along a word of the memory array section. Since the control unit controls the non-normal operation, it is possible to latch and write data to be simultaneously input to all of the memory cells belonging to a specific word in the memory array unit. In addition, it is possible to take a memory input belonging to a specific word inside the memory into a memory cell and perform a capture operation. This eliminates the need for a dummy flip-flop and a selection circuit that were required in the past, thereby reducing the chip area and reducing the number of logic stages. This has the effect of realizing the reduction of

[Brief description of the drawings]

FIG. 1 is a conceptual diagram when a full scan design is performed using a memory in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory in the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a normal operation of the memory in the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a diagram showing an operation at the time of testing a memory in the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a conceptual diagram of a general logic circuit.

FIG. 6 is a circuit diagram of a conventional memory.

FIG. 7 is a diagram showing a configuration of a circuit element of a memory.

FIG. 8 is another circuit diagram of the memory in the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 9 is still another circuit diagram of the memory in the semiconductor integrated circuit device according to the first embodiment of the present invention;

[Explanation of symbols]

 1, 2 Combination circuit 3 Memory 41-49 Scan flip-flop 200 Memory array unit 201 Decoder unit 202 Control unit 203 IO unit 210 IO circuit 211-214 NMOS transistor 215 Buffer 216-218 Inverter 220 Memory cell 221, 222 NMOS transistor 223 224 Inverter 225, 227 Tri-state inverter 226 NMOS transistor 230 Decoder circuit 231 to 233 AND circuit 234 Inverter 240 Latch circuit 241 to 243 Inverter 244, 245 NMOS transistor 250 to 255 AND circuit 610 IO circuit 650, 651 Inverter 640 Latch circuit

Claims (4)

[Claims] A memory unit for storing data; a decoding unit for decoding an address input to the memory array unit; a control unit for controlling writing and reading of the memory array unit; A latch circuit for synchronizing and holding a data input, an IO unit for inputting / outputting between the memory array unit and the outside, and a selection circuit provided in the latch circuit, for selecting a data input and a shift input. A semiconductor integrated circuit for activating a memory cell specified by an address input value during a normal operation, and activating a specific memory cell regardless of an address input value during an abnormal operation. apparatus. 2. The semiconductor integrated circuit device according to claim 1, wherein said memory cells are static memory cells, and said control unit is configured to control said memory cells belonging to a specific word of said memory array unit during said non-normal operation. A semiconductor integrated circuit device capable of both reading and writing data. 3. The semiconductor integrated circuit device according to claim 1, wherein a plurality of the latch circuits are arranged in a direction along a word of the memory array unit, and the memory array is controlled by the control unit during the non-normal operation. A semiconductor integrated circuit device capable of latching and writing data read from memory cells shifted one by one in a direction along a word, to a memory cell belonging to a specific word of the section. 4. The semiconductor integrated circuit device according to claim 1, wherein a plurality of said latch circuits are arranged in a direction along a word of said memory array section, and said memory array is controlled by said control section during said non-normal operation. A semiconductor integrated circuit device capable of latching and writing data to be simultaneously input to all of the memory cells belonging to a specific word of the section.