JP2003331600A - Semiconductor test circuit and method for testing semiconductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test circuit and a method for testing semiconductor in which a test time of semiconductor can be shortened and a strict operation speed test of a memory can be performed. <P>SOLUTION: This circuit is provided with a normal circuit for performing a scan test, a BIST control circuit having a mode 1 in which operation is automatically stopped after writing a pattern in the memory and a mode 2 in which a value written from the memory is read and compared with the prescribed expected value, and a memory write prohibiting circuit fixing an input signal to the memory while the normal circuit is in a scan test. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for inspecting a normal circuit and a semiconductor integrated circuit having a built-in memory with high accuracy in a short time, and a test method therefor.

[0002]

2. Description of the Related Art In recent years, the miniaturization of semiconductor processes has advanced,
Large-scale system LSIs have been developed. The system LSI has many built-in RAMs having different configurations such as the number of words because of its many functions. The operating speed has also increased, and at the same time, the leakage current accompanying miniaturization has increased, and the quality and inspection of built-in memory have become more demanding. BIST (Built-In) pre-assembled in a semiconductor circuit from the viewpoint of facilitating the test.
-Self-Test) dedicated circuit for testing (hereinafter referred to as BIS
Inspection using a T circuit) has been performed.

Further, regarding a memory that holds data by electric charge, for example, a RAM, RA due to current leakage.
The RAM pause test is often used to check the data loss of M. In this method, a test pattern is first written in the RAM, and this data is read after a lapse of a certain time to confirm that the data is not lost.

A conventional test circuit will be described below with reference to FIG. In FIG. 2, 101 is a semiconductor normal circuit, and 111 and 112 are FFs included in the normal circuit 101.
(Flip-flop) part, 102 is a clock synchronous RAM, 115 is a part 1 of the FF of the normal circuit 101
Partial circuits other than 11, 112 for exchanging data with the RAM 102, 121 for the selector, 203 for the RAM 10
BIST control circuits 225, 22 for testing 2
Reference numeral 6 is an FF in the BIST control circuit 203.

The signal S242 (CS, RE, ADR, DATA, etc.) from the normal circuit 101 to the RAM 102 is connected to the RAM 102 via the selector 121. Similarly, the signal S147 from the BIST control circuit 203 to the RAM 102 is also connected to the RAM 102 via the selector 121. Further, the output S144 of the RAM 102
Are connected to the normal circuit 101 and the BIST control circuit 203.

The selector 121 is controlled by a control signal (ramtest signal) S161 and has an input S242 from the normal circuit 101 and an input S from the BIST control circuit 203.
147 is selected to input S1 of the RAM 102.
43. That is, the ramtest signal S161 is O
When N, the selector 121 determines that the BIST control circuit 20
Select the input S147 from 3 and also the ramtest signal S1
When 61 is OFF, the selector 121 operates in the normal circuit 1
The input S242 from 01 is selected and supplied to the RAM 102. Further, the clock signal S150 is the normal circuit 101,
It is supplied to each of the BIST control circuit 203 and the RAM 102.

Note that the normal circuit 101 and the BIST control circuit 203 have a separate scan test circuit incorporated therein, and sc
When the anmode signal S151 is asserted, the mode is switched to the scan test mode, and the scan test can be performed from the outside. For details of this scan test circuit,
The description in FIG. 2 is omitted because it becomes complicated.

The BIST control circuit 203 is activated for the RAM test operation by the bistrun signal S162. BI
During the RAM test operation, the ST control circuit 203 makes RA
A series of signals S14 for writing a test pattern in M102
7 through the selector 121, write the test pattern in the RAM 102, and then send a series of signals S147 for reading the test pattern written in the RAM 102 to the RAM 102 through the selector 121, and RA
The data S144 read from M102 is received, and B
The expected value in the IST control circuit 203 is compared, and the determination result is output as a bistfail signal S165. bistdone
The signal S164 indicates whether or not the BIST test has been completed for the entire area of the RAM.

The operation of the series of RAM tests of the BIST control circuit 203 is temporarily stopped or canceled by the pause signal S213. If there are a plurality of RAMs having different internal configurations and a plurality of BIST control circuits corresponding to the RAMs in the semiconductor integrated circuit, the pause
There are as many signals as the number of types of internal configurations of the RAM.

Next, the operation flow of the inspection of the semiconductor circuit by the above-mentioned conventional test circuit will be described with reference to the timing chart of FIG. In the period 381, the scan input to the normal circuit 101 and the BIST control circuit 203 is performed.
When the mode signal S151 is asserted, the normal circuit 101,
The BIST control circuit 203 switches to the scan test mode, receives a predetermined test pattern from the scan chain, performs a scan test, and outputs the test result to the outside.

In the period 382, the scanmode signal S151 is negated to end the scan test. Then ramtes
The t signal S161 is turned on, and accordingly, the selector 1
Reference numeral 21 designates the output from the BIST control circuit 203 as the RAM 10
2 will be switched to select as input to.
In the period 383, when the bistrun signal S162 is asserted, the BIST control circuit 203 generates a test pattern and outputs it to the RAM 102, and in the period 384,
The operation is temporarily stopped by the pause signal S213 from the outside. In the period 385, since the predetermined pause period has passed, the pause signal S213 is released, the BIST control circuit 203 reads the value written from the RAM 102, compares it with the expected value in the BIST control circuit 203, and the comparison result Is output as a bistfail signal S165. When all the tests (comparisons) are completed, the bistdone signal S164 is output to the outside.

As shown in FIG. 3, 301 is a scan test period and 311 is a RAM pause test period.
The RAM pause test period 311 is a period for writing a test pattern into the RAM 312, a RAM pause period 313 for prohibiting the operation of the RAM for a certain period, and a period for reading the value in the RAM written in the period 312 and comparing it with an expected value. And 314. Note that pause [0],
pause [1] and pause [2] are pause signals of the BIST control circuit corresponding to a plurality of RAMs having different internal configurations.

As described above, in the conventional test circuit, the scan test and the RAM pause test are performed sequentially in time, and the total test time 322 is the scan test period 301 and the RAM pause test period 311. And the sum of the test time.

[0014]

However, the above-mentioned conventional structure has the following problems. (1) Control signal 143 to RAM during scan test
(Write enable, chip selector, etc.)
Since it changes depending on the scan data set in 1 or FF 225, even if the inspection data is written in the RAM in advance, the data is overwritten and destroyed. Therefore, there is a problem that the scan test cannot be performed during the pause of the RAM pause test, and both must be performed independently in terms of time.

(2) The conventional BIST control circuit is a RAM
After writing the test pattern to, the reading is automatically continued. After writing the test pattern for the pause period of the RAM pause test, RA of the BIST control circuit
To suspend the M test operation, immediately after the BIST control circuit writes the test pattern to the RAM, and before the reading is started, the BIST pause signal is input from the outside and the BIST pause signal is input.
It is necessary to suspend the IST control circuit. As the internal operation speed increases, it becomes difficult to accurately control the pause signal from outside the LSI at this timing.

The number of write cycles is R
It depends on the capacity of the AM and the clock supplied. However, there are many RAMs having different capacities in the system LSI, and there are cases in which clocks of a plurality of frequencies having different periods are used. Therefore, the time required to write the test pattern differs depending on these combinations,
Therefore, there are multiple timings for inputting the pause signal. When the conventional RAM test circuits are arranged side by side to cope with such a situation, there is a problem that a plurality of terminals for inputting a pause signal at different timings are required.

Further, in order for the BIST control circuit to resume the operation and continue the read operation after the pause is released, it is needless to say that the internal state of the BIST control circuit must be held during the pause period. However,
Even if the contents of RAM are saved after the scan test, the BIS during the pause period of the RAM pause test.
When the T control circuit itself is scan-tested, the state inside the BIST control circuit is destroyed, so that there is a problem that the pause test and the scan test cannot be executed at the same time.

(3) In the conventional RAM test circuit, the BI
Signal S in RAM test mode using ST control circuit
The path for propagating 147 is different from the path for propagating the signal S141 during normal operation. Therefore, even if the actual speed timing test by the BIST control circuit is PASS, the actual speed timing test in the normal operation mode may fail. That is, there is a problem that a strict operation speed test in normal operation cannot be performed by a conventional RAM test circuit.

The present invention has been made to solve the above conventional problems, and shortens the semiconductor inspection time.
Another object of the present invention is to provide a semiconductor test circuit and a test method therefor capable of performing a strict operation speed inspection of a memory.

[0020]

In order to solve the above problems, a semiconductor test circuit according to claim 1 of the present invention comprises a scan test normal circuit and a memory connected to the normal circuit. And a circuit for fixing an input signal to the memory so that a new value is not written to the memory while the normal circuit is in the scan test mode. This allows
During the scan test of the normal circuit, the scan test of the normal circuit and the pause test of the memory can be superimposed without destroying the state of the memory.

A semiconductor test circuit according to a second aspect of the present invention is a semiconductor circuit having a scan test normal circuit and a memory connected to the normal circuit, wherein the normal circuit is in a scan test mode. A circuit for fixing a clock signal to the memory is provided so that a new value is not written to the memory for a certain period. As a result, during the scan test of the normal circuit, the scan test of the normal circuit and the pause test of the memory can be superimposed without destroying the state of the memory.

A semiconductor test circuit according to a third aspect of the present invention is a semiconductor circuit having a normal circuit capable of scan test and one or a plurality of memories connected to the normal circuit. A BIST control circuit for performing a test operation, the BIST control circuit writing a test pattern to the memory and automatically stopping the operation, and reading a value written in the memory to obtain a predetermined expected value. And a second operation mode to be compared with. This allows BI
In the pause test of the memory using the ST control circuit, the pause timing control from the outside is unnecessary, and the scan test of the BIST control circuit itself can be performed during the pause test.

A semiconductor test circuit according to a fourth aspect of the present invention is the semiconductor test circuit according to the first or second aspect, wherein one or a plurality of memories connected to the normal circuit and the memory. And a BIST control circuit for performing a test of the first operation mode, wherein the BIST control circuit writes a test pattern to the memory and automatically stops, and reads a value written in the memory. It has a second operation mode to be compared with a predetermined expected value. As a result, B
In the pause test of the memory using the IST control circuit, it is not necessary to control the pause timing from the outside, and it is also possible to perform the scan test of the BIST control circuit itself during the pause test. It is also possible to overlap the pause test of the memory.

A semiconductor test circuit according to a fifth aspect of the present invention is the semiconductor test circuit according to the first or second aspect, which is based on a switching signal which is interlocked with an external input terminal and a scan test mode selection signal. A selector for selecting an input signal from the normal circuit or an input signal from the external input terminal and supplying the selected signal to the memory, and in the scan test mode, the memory is configured to operate via the selector. It is characterized in that it is connected to an external input terminal. This enables a memory test from the outside while performing a scan test of a normal circuit, and is particularly effective when a scan test and a memory test other than the pause test, such as a march algorithm, are superimposed.

A semiconductor test circuit according to a sixth aspect of the present invention is a semiconductor circuit having a normal circuit including a first FF as an FF in a preceding stage of a memory, and the memory connected to the normal circuit. And a BIST control circuit for inspecting the memory, wherein the first signal supplied from the normal circuit to the memory and the second signal supplied from the BIST control circuit to the memory are respectively The output of the selector is connected to the selector, the output of the selector is connected to the first FF, and the output of the first FF is connected to the memory. As a result, with a simple circuit configuration, the signal during normal operation and the signal during memory test pass through the same propagation path.
It becomes possible to perform a strict write timing test of the memory using the IST control circuit. Further, since the signal from the normal circuit or the BIST control circuit to the memory is temporarily received by the FF, the failure detection rate of these scan tests can be increased.

A semiconductor test circuit according to a seventh aspect of the present invention is the semiconductor test circuit according to the sixth aspect, wherein the normal circuit further includes a second FF as a FF in a subsequent stage of the memory.
The output of the memory is connected to the second FF, and the output of the second FF is connected to the normal circuit or the BIST control circuit, respectively. Is. As a result, a strict read timing test of the memory using the BIST control circuit can be performed with a simple circuit configuration, and a test pattern can be input to the normal circuit and the BIST control circuit from the FF in the subsequent stage of the memory. The failure detection rate of can also be improved.

A semiconductor test circuit according to an eighth aspect of the present invention is the semiconductor test circuit according to any one of the first, second or fifth aspects, wherein the BIST control for inspecting the selector and the memory is performed. And a first signal supplied from the normal circuit to the memory and the BIST control circuit from the BIST control circuit. The second signal supplied to the memory is connected to the selector, the output of the selector is connected to the first FF, and the output of the first FF is connected to the memory. It is what As a result, the scan test and the memory pause test can be performed in parallel, and at the same time, the BIST can be performed with a simple circuit configuration.
A strict speed test of the memory using the control circuit becomes possible, and the failure detection rate of the scan test of the normal circuit and the BIST control circuit can be improved.

A semiconductor test circuit according to a ninth aspect of the present invention is the semiconductor test circuit according to the third or fourth aspect, further comprising a selector, and the normal circuit is an FF in a front stage of the memory. The first signal supplied from the normal circuit to the memory and the second signal supplied from the BIST control circuit to the memory are respectively supplied to the selector. The selector is connected, the output of the selector is connected to the first FF, and the output of the first FF is connected to the memory. As a result, the scan test and the pause test can be performed in parallel, and at the same time, the strict speed test of the memory using the BIST control circuit can be performed with a simple circuit configuration, and the normal circuit and the BIST control circuit can be performed. The fault detection rate of the scan test can also be improved.

A semiconductor test circuit according to a tenth aspect of the present invention is the semiconductor test circuit according to any one of the eighth and ninth aspects, wherein the normal circuit further includes a second FF as a FF in a subsequent stage of the memory. And an output of the memory is connected to the second FF,
The output of the second FF is connected to the normal circuit or the BIST control circuit, respectively. As a result, the scan test and the pause test can be performed in parallel, and at the same time, the strict speed test of the memory using the BIST control circuit can be performed with a simple circuit configuration, and the normal circuit and the BIST control circuit can be performed. The fault detection rate of the scan test can also be improved.

A semiconductor test method according to an eleventh aspect of the present invention is a scan test in which a scan test normal circuit, one or a plurality of memories connected to the normal circuit, and the memory are inspected. A semiconductor test method for testing a semiconductor circuit having a possible BIST control circuit, wherein a write-protected state to the memory is released, and a test pattern is written to the memory using the BIST control circuit. And the write prohibition state to the memory, the normal circuit and the B
The second step of simultaneously performing one or both scan tests with the IST control circuit, the write-protection state to the memory is released, and the value written in the memory in the first step is stored in the BIST control circuit. And a third step of reading and comparing with an expected value. As a result, the scan test and the memory pause test can be superimposed.

A semiconductor test method according to a twelfth aspect of the present invention is a normal circuit capable of scan test, a memory connected to the normal circuit, an external input terminal for sending an input signal to the memory, and the normal circuit. Alternatively, a semiconductor test method for performing a test on a semiconductor circuit having a selector that selects an input signal from the external input terminal and supplies the selector to the memory, wherein a scan test of the normal circuit is performed in a scan test mode. In parallel with the execution, the memory is logically separated from the normal circuit by writing and reading from the external input terminal to test the memory. Thereby, the scan test and the memory test can be superimposed.

[0032]

(First Embodiment) A semiconductor test circuit and a semiconductor test method according to a first embodiment of the present invention will be described below with reference to FIGS. 1 is a diagram showing a configuration of a semiconductor test circuit according to a first embodiment of the present invention.

In FIG. 1, 101 is a semiconductor normal circuit, 111 and 112 are some of FFs included in the normal circuit 101, 102 is a clock synchronous memory (RAM), 1
Reference numeral 15 is a partial circuit for exchanging data with the RAM 102, other than the FF 111 and FF 112 of the normal circuit 101, 1
Reference numeral 21 is a selector, 103 is a BIST control circuit for testing the RAM 102, 125 and 126 are FFs in the BIST control circuit 103, and 105 is a prohibition circuit that prohibits writing to the RAM 102.

The signal S141 (CS, RE, ADR, DATA, etc.) from the normal circuit 101 to the RAM 102 passes through the selector 121, the FF 111, and the RAM 102.
Entered in. Similarly, from the BIST control circuit 103 to RA
The signal S147 to M102 is also F through the selector 121.
It is input to the RAM 102 via F111. Also R
The output signal S144 from the AM 102 is input to the normal circuit 101 and the BIST control circuit 103 via the FF 112.

The selector 121 is controlled by the ramtest signal S161, and receives the input signal S14 from the normal circuit 101.
1 or the input signal S147 from the BIST control circuit 103, and selects RAM1 via the FF111.
02 to the input signal S143. That is, ra
When the mtest signal S161 is ON, the selector 121
Selects the input S147 from the BIST control circuit 103, and when the ramtest signal S161 is OFF, the selector 121 selects the input S141 from the normal circuit 101 and supplies it to the RAM 102.

Further, the clock signal S150 is the normal circuit 10
1, BIST control circuit 103, and write inhibit circuit 1
05, and the clock signal S152 is supplied from the write inhibit circuit 105 to the RAM 102.

The RAM 102 is provided in the write inhibit circuit 105.
When the protect signal S153 is input and the protect signal S153 is asserted, the clock supply to the RAM 102 is stopped, so that the RAM 102 cannot be written. That is,
When the protect signal S153 is asserted, in the first embodiment, the ramtest signal S161 and the scanmode signal S15
RAM 102 regardless of the ON or OFF state with 1
It becomes impossible to write to.

The normal circuit 101 and the BIST control circuit 1
03 has a built-in scan test circuit and scan
When the mode signal S151 is asserted, the mode is switched to the scan test mode, and the scan test can be performed from the outside. Since the details of the scan test circuit are complicated, the description in FIG. 1 is omitted.

The BIST control circuit 103 writes the test pattern in a certain area of the RAM in the first operation (CW:
Checker Pattern Write) sequence and the second operation to read the test pattern written in a certain area and compare it with the expected value (CR: Checker Pattern Read)
Built-in sequence and. C of the BIST control circuit 103
A series of signals S147 for writing the test pattern in the RAM, which are generated by the W operation, are R through the selector 121.
It is written in the AM 102 as a test pattern. A series of signals for reading the test pattern written in the RAM, which is generated by the CR operation of the BIST control circuit 103, is also sent to the RAM 102 via the selector 121, and the data S144 read from the RAM 102 is FF.
It becomes S146 via 112. BIST control circuit 103
Receives S146, compares it with an internal expected value, and outputs the determination result as a bistfail signal S165.

Further, the BIST control circuit 103 is a bistru
The RAM test operation is activated by the n signal S162. During the RAM test operation, the BIST control circuit 103 first performs the CW operation if the 0th bit of the bistmode signal S163 is 1, and moves to the next operation if the 0th bit is 0. In the next operation, if the first bit of the bistmode signal S163 is 1, the CR operation is performed, and if it is 0, the next operation is performed. In the next operation, the BIST control circuit 103 outputs the bistdone signal S
164 is asserted and output to the outside, and the operation is automatically stopped.

Next, the operation of the BIST control circuit 103 will be described with reference to the flowchart shown in FIG. As shown in FIG. 5, in the BIST control circuit 103, first, in step S501, the initial state in which the bistrun signal S162 is 0 moves to step S502. Step S
502 initializes the bistdone signal S164 and bistfa
il signal S165 is set to 0 respectively, and step S
Move to 503. Step S503 is a bistrun signal S16.
It waits for 2 to become 1, and when the bistrun signal S162 becomes 1, the process proceeds to step 504. Step S504 is bistmo
The 0th bit of the de signal S163 is checked. If it is 1, the process proceeds to step S505, and if not, the process skips step S505 and proceeds to step S506. In step S505, a sequence of signals necessary for writing the test pattern in the memory to be tested is generated and output to the RAM 102 to be tested, and the process proceeds to step S506. Step S506 checks the first bit of the bistmode signal S163, and if it is 1, step S507.
Otherwise, skip step S507 and proceed to step S508. In step S507, a sequence of signals for reading data from the memory under test is generated, and the value read from the memory is sequentially compared with the expected value stored in the BIST control circuit 103. If they do not match, 1 is set to the bistfail signal S165. Output as. Then, it progresses to step S508. Step S508 is 1
Is output as a bistdone signal S164 to indicate the end of processing to the outside of the BIST control circuit 103.

Next, the operation of inspecting the semiconductor circuit in the semiconductor test circuit and the semiconductor test method according to the first embodiment will be described with reference to the timing chart of FIG. Ramtes asserted in period 481
When the t signal S161 is input, the selector 121 causes the BI
The output S147 of the ST control circuit 103 is selected to select RAM1.
Set to supply 02. Also, bistmode = 0
1 is input, and the BIST control circuit 103 prepares to execute only the CW operation.

Then, in the period 482, the bistrun signal S16
2 is asserted, and the BIST control circuit 103 activates the RAM test operation. First, a sequence for generating a built-in test pattern is executed to generate a test pattern, and the RAM 10 is passed through the selector 121 and the FF 111.
Write to 2. This completes the (first) CW operation,
The BIST control circuit 103 outputs 1 to the bistdone signal S164 and automatically stops. From the outside in period 483
The protect signal S153 is input to the RAM write inhibit circuit 105, the RAM 102 is placed in the protected state, and preparations for the next scan test are completed.

In the period 484 after the RAM 102 is protected, the scanmode signal S asserted from the outside is output.
151 is sent to the normal circuit 101 and the BIST control circuit 103, and the normal circuit 101 and the BIST control circuit 103 enter the scan test mode. Then, the normal circuit 101, BI
A scan test of the ST control circuit 103 is performed. That is, the normal circuit 1 is externally supplied by a predetermined scan input pin.
01, sends a control signal or test signal to the scan test FF provided in the BIST control circuit 103, receives the scan test result from a predetermined scan output pin, and compares it with a predetermined expected value externally. Then, the normal circuit 101 and the BIST control circuit 103 produce a result indicating whether or not the scan test has passed. During the scan test, the RAM 102 is in the pause test state.

After the above scan test is completed, the protect signal S153 is turned off in the period 485,
The RAM 102 is released from the protected state. Also, bi
Input stmode = 10 and the BIST control circuit 103 sets CR
Prepare to execute only the operation. And in the period 486
When the bistrun signal S162 is asserted, the BIST control circuit 103 enters the second operation mode, and the RAM1
A series of signals S1 for reading what is written in 02
47 through RAM 121 via selector 121 and FF111
Sent to 02 and read from there S144
Is received via the FF 112, compared with the built-in expected value, and the result is output to the outside as a bistfail signal S165. Once all the comparisons are complete, this is (second)
The CR operation ends, and the BIST control circuit 103 sets the bistdone
It outputs 1 to the signal S164 and automatically stops.

As shown in FIG. 4, 301 is a scan test period and 311 is a RAM pause test period.
The RAM pause test period 311 here is a test pattern writing period 312 into the RAM, a RAM pause period 313 in which the operation of the RAM is prohibited for a certain period, and the above period 31.
A period 314 in which the value in the RAM written in 2 is read out and compared with the expected value. Further, 481 is a CW operation preparation period, 482 is a CW operation period, 483 is a scan test preparation period, 484 is a scan test period, and 485 is CR.
An operation preparation period, 486 is a CR operation period.

In other words, in the first embodiment, the scan test is executed in parallel during the pause period of the RAM pause test, so that the total test time 402 of the scan test and the RAM pause test is as shown in FIG. The total test time 322 is shortened.

Further, since the BIST control circuit 103 automatically stops after the CW operation, the BIST control circuit is temporarily stopped immediately after the CW operation ends by using the pause signals 330 to 332 as shown in FIG. There is no need to control externally to stop.

As described above, in the semiconductor test circuit and the test method therefor according to the first embodiment, the write inhibit circuit for inhibiting the write to the RAM during the pause period of the RAM pause test, the input to the memory from the outside and the normal circuit. Select the input to the memory from the memory to logically connect to the memory, write operation mode that automatically stops after writing the test pattern to the memory, and read / expect to read the written value and compare it with the expected value A BIST control circuit having a value comparison mode, the selector is arranged further to the front side than the front stage FF of the memory, and the output of the memory is passed through the rear stage FF before the normal circuit and the BI.
Since the input is made to the ST control circuit, the write inhibition circuit to the memory does not overwrite the data even if the inspection data is written to the memory in advance, and the scan test is performed during the pause period. Even if the internal state of the BIST control circuit changes (destroy) after execution, the BIST control circuit can restart operation from the read / expected value comparison (CR operation) mode after the end of the pause period. The scan test of the normal circuit and the BIST control circuit can be performed in parallel during the test pause period, and the total test time required for testing the semiconductor circuit can be reduced.

Further, the BIST control circuit automatically stops after writing the test pattern for the pause period of the memory pause test, which eliminates the need for the temporary external suspension control, which is conventionally required. The complicated control from the outside, which is required when there are a large number of memories having different capacities, becomes unnecessary and the number of required input terminals can be reduced.

In addition, the operating frequency of the memory is such that the FF from the front stage of the memory to the memory and FF from the memory to the rear stage of the memory.
Is determined by the propagation time of. In the first embodiment, a selector for separating the normal system and the memory test system is arranged further to the front side than the FF in the front stage of the memory, so that the path from the FF in the front stage of the memory to the memory is in the normal operation and the memory test. The signal propagation path is exactly the same during operation. Further, the path from the memory to the subsequent stage of the memory is the same. Therefore, if the memory is tested at the actual speed during the memory test operation, the test is strictly equivalent to the actual speed test of the memory during the normal operation. Further, since the FFs are arranged before and after the memory, the fault detection rate by the scan test of the circuit interacting with the memory is improved.

In the first embodiment, the RAM has been described as an example of the memory, but the present invention is applicable to other types of memory, in particular, a memory having a mechanism for holding data by electric charge, for example, For flash ROM etc.,
The same effect can be exhibited.

Further, in the first embodiment, the description has been made by taking the BIST control circuit as a test for the memory as an example. However, instead of the BIST control circuit, writing / reading by an external input terminal is performed. Even if the memory is tested with, the memory pause test and the normal circuit scan test can be similarly performed in parallel. Similarly, if the actual speed test of the memory is performed during the memory test operation, the inspection is strictly equivalent to the actual speed test of the memory during the normal operation.

In the first embodiment, the RAM write inhibit circuit stops the clock supplied to the RAM as a method of inhibiting access to the RAM. However, in the case of a clock asynchronous type RAM, the write enable of the RAM is enabled. Alternatively, the access may be prohibited by fixing the chip select or the like.

Even when the control signal to the RAM can be directly controlled from the outside during the scan test, the effect that the scan test and the test for the memory can be similarly superposed can be obtained.

[0056]

As described above, according to the semiconductor test circuit of the first aspect of the present invention, in the semiconductor circuit having the normal circuit capable of scan test and the memory connected to the normal circuit, While the circuit is in the scan test mode, a circuit for fixing the input signal to the memory is provided so that a new value is not written in the memory, so that the state of the memory during the pause period of the memory pause test is provided. The memory test and the scan test can be overlapped with each other without the possibility of being destroyed by the scan test, and the total test time of the scan test and the memory pause test can be shortened.

According to the semiconductor test circuit of the second aspect of the present invention, in the semiconductor circuit having the normal circuit capable of scan test and the memory connected to the normal circuit, the normal circuit is in the scan test mode. Since a circuit for fixing a clock signal to the memory is provided so that a new value is not written to the memory while the test data is stored in the memory, the inspection data is previously stored in the memory as in the invention according to claim 1. Even if you write, during the pause period,
Since the clock supply to the memory is stopped and new writing to the memory cannot be performed, it is possible to perform the memory test and scan test in parallel without overwriting and destroying the data. There is an effect that the total test time with the test can be shortened.

According to the semiconductor test circuit of the third or fourth aspect of the present invention, the BIST control circuit for testing one or a plurality of memories writes a test pattern to the memories and automatically stops. Since the BIST control circuit has a first operation mode for performing a memory pause test and a second operation mode for reading a value written in the memory and comparing it with a predetermined expected value. In addition, since the test pattern is automatically stopped after writing, it is not necessary to control the suspension from the outside, which was required in the past. Especially, it is necessary when there are many memories with different capacities such as system LSI. The effect of being able to reduce the number of required input terminals can be eliminated by eliminating the need for complicated control. Further, even if the scan test is executed during the pause period and the internal state of the BIST control circuit changes and is lost, the BIST control circuit can restart the operation from the read / expected value comparison mode after the pause period. Therefore, the scan test of the normal circuit and the BIST control circuit can be simultaneously executed during the pause period of the memory pause test, and the semiconductor test time can be shortened.

According to a fifth aspect of the semiconductor test circuit of the present invention, in the semiconductor test circuit according to the first or second aspect, the external input terminal and the switching signal interlocked with the scan test mode selection signal are used. A selector for selecting an input signal from the normal circuit or an input signal from the external input terminal and supplying the same to the memory based on the above, and in the scan test mode, the memory is operated via the selector. Since it is connected to the external input terminal, it is possible to perform a memory test while performing a scan test of a normal circuit. In particular, when a scan test and a memory test other than a pause test such as march are superposed,
The semiconductor test time can be effectively shortened.

According to the semiconductor test circuit of any one of claims 6 to 10 of the present invention, the signal propagation path during the memory test and the signal propagation path during the normal operation are made the same. Therefore, performing the actual speed test of the memory during the memory test operation is equivalent to performing the actual speed test of the memory during the normal operation, that is, there is an effect that a strict equivalence test can be performed.

According to the semiconductor test method of the eleventh aspect of the present invention, a scan test normal circuit, one or a plurality of memories connected to the normal circuit and having different internal configurations, and an inspection of the memory. A semiconductor test method for performing a test on a semiconductor circuit having a scan testable BIST control circuit, wherein a write inhibit state to the memory is released, and a test is performed on the memory using the BIST control circuit. The first step of writing a pattern and setting the write-protection state to the memory,
The second step of simultaneously performing one or both scan tests of the normal circuit and the BIST control circuit, the write-protection state to the memory is released, and the value written to the memory in the first step is The BIST
Since the third step of reading using the control circuit and comparing with the expected value is provided, it becomes possible to superimpose the scan test and the memory pause test.
This has the effect of shortening the semiconductor inspection time.

According to a twelfth aspect of the semiconductor test method of the present invention, a scan test normal circuit, a memory connected to the normal circuit, an external input terminal for sending an input signal to the memory, and the normal circuit are provided. A semiconductor test method for testing a semiconductor circuit having a circuit or a selector for selecting an input signal from the external input terminal and supplying it to the memory, wherein a scan test of the normal circuit is performed in a scan test mode. In parallel with performing the above, writing and reading from the external input terminal to the memory logically separated from the normal circuit,
Since the memory test is performed, it becomes possible to superimpose the scan test and the memory test,
This has the effect of shortening the semiconductor inspection time.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor test circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional test circuit.

FIG. 3 is an operation timing chart of a conventional test circuit.

FIG. 4 is an operation timing chart of the semiconductor test circuit according to the first embodiment of the present invention.

FIG. 5 is an operation flowchart of the BIST control circuit according to the first embodiment of the present invention.

[Explanation of symbols]

101 normal circuit 102 memory 103 BIST control circuit 105 RAM write prohibition circuit 111, 112, 125, 126, 225, 226 flip-flop 121 selector 150, 152 clock signal 151 scan test mode signal 153 RAM write prohibition control signal 161 memory test mode Signal 162 BIST execution control signal 163 BIST content setting signal 164 BIST execution end signal 203 Conventional BIST control circuits 330 to 332 Conventional BIST stop control timing during pause test

Claims (12)

[Claims] 1. A semiconductor circuit having a scan testable normal circuit and a memory connected to the normal circuit, wherein a new value is not written to the memory while the normal circuit is in a scan test mode. A semiconductor test circuit comprising: a circuit for fixing an input signal to the memory. 2. A semiconductor circuit having a scan testable normal circuit and a memory connected to the normal circuit, wherein a new value is not written to the memory while the normal circuit is in the scan test mode. A semiconductor test circuit comprising: a circuit for fixing a clock signal to the memory. 3. A semiconductor circuit having a scan test normal circuit and one or a plurality of memories connected to the normal circuit, comprising a BIST control circuit for inspecting the memory, wherein the BIST control circuit is provided. Has a first operation mode in which a test pattern is written to the memory and automatically stops, and a second operation mode in which a value written in the memory is read and compared with a predetermined expected value. A semiconductor test circuit characterized by the above. 4. The semiconductor test circuit according to claim 1, comprising one or a plurality of memories connected to the normal circuit, and a BIST control circuit that inspects the memory. The BIST control circuit writes a test pattern in the memory and automatically stops the operation, and a second operation mode in which the value written in the memory is read and compared with a predetermined expected value. A semiconductor test circuit comprising: 5. The semiconductor test circuit according to claim 1, wherein an input signal from the normal circuit, or the input signal from the normal circuit is output based on an external input terminal and a switching signal that is interlocked with a scan test mode selection signal. A semiconductor that selects an input signal from an external input terminal and supplies it to the memory, wherein the memory is connected to the external input terminal via the selector in the scan test mode. Test circuit. 6. A semiconductor circuit having a normal circuit including a first FF as an FF in the preceding stage of the memory and the memory connected to the normal circuit, a selector, and a BIST control circuit for inspecting the memory. A first signal supplied from the normal circuit to the memory and a second signal supplied from the BIST control circuit to the memory are respectively connected to the selector, and the output of the selector is A semiconductor test circuit, wherein the semiconductor test circuit is connected to the first FF, and the output of the first FF is connected to the memory. 7. The semiconductor test circuit according to claim 6, wherein the normal circuit further has a second FF as an FF in the latter stage of the memory, and the output of the memory is the second FF. A semiconductor test circuit, wherein the semiconductor test circuit is connected to an FF, and the output of the second FF is connected to the normal circuit or the BIST control circuit, respectively. 8. The method according to claim 1, claim 2 or claim 5.
In the semiconductor test circuit according to any one of 1 to 3, a selector and a BIST control circuit that inspects the memory are provided, and further, the normal circuit has a first FF as an FF in a front stage of the memory, A first signal supplied from the normal circuit to the memory and a second signal supplied from the BIST control circuit to the memory are respectively connected to the selector, and the output of the selector is the first signal. A semiconductor test circuit, wherein the output of the first FF is connected to the memory. 9. The semiconductor test circuit according to claim 3, further comprising: a selector, wherein the normal circuit further includes a first FF as an FF in a front stage of the memory, A first signal supplied from the normal circuit to the memory and a second signal supplied from the BIST control circuit to the memory are respectively connected to the selector, and the output of the selector is the first signal. A semiconductor test circuit, wherein the output of the first FF is connected to the memory. 10. The semiconductor test circuit according to claim 8, wherein the normal circuit further has a second FF as an FF in a subsequent stage of the memory. An output is connected to the second FF, and an output of the second FF is connected to the normal circuit or the BIST control circuit, respectively. 11. A scan testable normal circuit, one or a plurality of memories connected to the normal circuit, and a scan testable B for inspecting the memory.
A semiconductor test method for performing a test on a semiconductor circuit having an IST control circuit, comprising: canceling a write-protection state to the memory;
A first step of writing a test pattern in the memory using a T control circuit, setting a write inhibit state to the memory, and simultaneously performing a scan test of one or both of the normal circuit and the BIST control circuit. A second step, a third step of releasing the write-protection state to the memory, reading the value written to the memory in the first step using the BIST control circuit, and comparing the value with an expected value; A semiconductor test method comprising: 12. A scan test normal circuit, a memory connected to the normal circuit, an external input terminal for sending an input signal to the memory, and an input signal from the normal circuit or the external input terminal is selected. A semiconductor test method for testing a semiconductor circuit having a selector for supplying the memory to the memory, wherein a logic test from the normal circuit is performed in parallel with a scan test of the normal circuit in a scan test mode. The semiconductor test method is characterized in that the memory is tested by performing writing and reading from the externally input terminal with respect to the memory that has been physically separated.