JP4230717B2 - Semiconductor test circuit and semiconductor test method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test circuit for testing a normal circuit and a semiconductor integrated circuit having a built-in memory with high accuracy in a short time, and a test method therefor.
[0002]
[Prior art]
In recent years, semiconductor processes have been miniaturized and large-scale system LSIs have been developed. The system LSI incorporates a large number of RAMs having different configurations, such as the number of words, because of their large number of functions. The operating speed has been increased, and on the other hand, the leakage current accompanying the miniaturization has increased, and the quality and inspection of the built-in memory have become more demanding.
From the viewpoint of facilitating testing, inspection using a circuit dedicated to testing (hereinafter referred to as BIST circuit) called BIST (Built-In-Self-Test) incorporated in a semiconductor circuit in advance has been performed. Yes.
[0003]
In addition, with respect to a memory that holds data by electric charges, for example, a RAM, a RAM pause test is often used for checking data loss of the RAM due to current leakage. In this method, a test pattern is first written in the RAM, and this data is read after a lapse of a certain time to confirm that no data is lost.
[0004]
Hereinafter, a conventional test circuit will be described with reference to FIG.
In FIG. 2, 101 is a semiconductor normal circuit, 111 and 112 are FFs (flip-flops) included in the normal circuit 101, 102 is a clock synchronous RAM, and 115 is a part of the FFs of the normal circuit 101. , 112 is a partial circuit for exchanging data with the RAM 102, 121 is a selector, 203 is a BIST control circuit for testing the RAM 102, and 225 and 226 are FFs in the BIST control circuit 203.
[0005]
A signal S242 (CS, RE, ADR, DATA, etc.) from the normal circuit 101 to the RAM 102 is connected to the RAM 102 via the selector 121. Similarly, a signal S147 from the BIST control circuit 203 to the RAM 102 is also connected to the RAM 102 via the selector 121. The output S144 of the RAM 102 is connected to the normal circuit 101 and the BIST control circuit 203.
[0006]
The selector 121 is controlled by a control signal (ramtest signal) S161, selects either the input S242 from the normal circuit 101 or the input S147 from the BIST control circuit 203, and supplies it to the input S143 of the RAM 102. That is, when the ramtest signal S161 is ON, the selector 121 selects the input S147 from the BIST control circuit 203, and when the ramtest signal S161 is OFF, the selector 121 selects the input S242 from the normal circuit 101. And supplied to the RAM 102.
The clock signal S150 is supplied to each of the normal circuit 101, the BIST control circuit 203, and the RAM 102.
[0007]
The normal circuit 101 and the BIST control circuit 203 have a configuration in which a separate scan test circuit is incorporated, and when the scanmode signal S151 is asserted, the scan test mode is switched to enable a scan test from the outside. The details of the scan test circuit are complicated, and the description in FIG. 2 is omitted.
[0008]
The BIST control circuit 203 is activated for the RAM test operation by the bistrun signal S162. During the RAM test operation, the BIST control circuit 203 sends a series of signals S147 for writing a test pattern to the RAM 102 via the selector 121, writes the test pattern to the RAM 102, and then reads the test pattern written to the RAM 102. The signal S147 is also sent to the RAM 102 via the selector 121, receives the data S144 read from the RAM 102, compares it with the expected value in the BIST control circuit 203, and outputs the determination result as the bistfail signal S165. The bistdone signal S164 indicates whether or not the BIST test has been completed for all areas of the RAM.
[0009]
The series of RAM test operations of the BIST control circuit 203 are temporarily stopped or released by the pause signal S213. When there are a plurality of RAMs having different internal configurations and a plurality of corresponding BIST control circuits in the semiconductor integrated circuit, there are as many pause signals as the number of types of RAM internal configurations.
[0010]
Next, the operation flow of the inspection of the semiconductor circuit by the conventional test circuit will be described with reference to the timing chart of FIG.
In the period 381, when the scanmode signal S151 input to the normal circuit 101 and the BIST control circuit 203 is asserted, the normal circuit 101 and the BIST control circuit 203 are switched to the scan test mode, and a predetermined test pattern is input from the scan chain. Thus, a scan test is performed and the test result is output to the outside.
[0011]
In the period 382, the scanmode signal S151 is negated and the scan test is terminated. Next, the ramtest signal S161 is turned ON, and accordingly, the selector 121 is switched so as to select the output from the BIST control circuit 203 as the input to the RAM 102. In the period 383, when the bistrun signal S162 is asserted, the BIST control circuit 203 generates a test pattern and outputs it to the RAM 102. In the period 384, the operation is temporarily stopped by an external pause signal S213. The In the period 385, since the predetermined pause period has passed, the pause signal S213 is released, the BIST control circuit 203 reads the value written from the RAM 102, compares it with the expected value in the BIST control circuit 203, and the comparison result Is output as the bistfail signal S165. When all tests (comparison) are completed, the bistdone signal S164 is output to the outside.
[0012]
As shown in FIG. 3, 301 is a scan test period, and 311 is a RAM pause test period. The RAM pause test period 311 includes a test pattern writing period 312 to the RAM, a RAM pause period 313 in which the operation of the RAM is prohibited for a certain period, and a period in which the value in the RAM written in the period 312 is read and compared with an expected value. 314. Note that pause [0], pause [1], and pause [2] are pause signals for the BIST control circuit corresponding to a plurality of RAMs having different internal configurations.
[0013]
As described above, in the conventional test circuit, the scan test and the RAM pause test are performed in time order, and the total test time 322 is a test in the scan test period 301 and the RAM pause test period 311. It is the sum of time.
[0014]
[Problems to be solved by the invention]
However, the above conventional configuration has the following problems.
(1) Control signal to RAM during scan test S Since 143 (write enable, chip selector, etc.) varies depending on the scan data set in the FF 111 or FF 225, the data is overwritten and destroyed even if the test data is written in the RAM in advance. Therefore, the scan test cannot be performed during the pause of the RAM pose test, and both have to be performed independently in time.
[0015]
(2) The conventional BIST control circuit automatically continues reading after writing the test pattern into the RAM. In order to temporarily stop the RAM test operation of the BIST control circuit after writing the test pattern for the pause period of the RAM pause test, the BIST pause circuit immediately after the BIST control circuit writes the test pattern to the RAM and before the reading starts. It is necessary to temporarily stop the BIST control circuit by inputting a signal from the outside. As the internal operation speed increases, there is a problem that it becomes difficult to control the pause signal accurately at this timing from outside the LSI.
[0016]
Further, the number of cycles required for writing differs depending on the capacity of the RAM and the supplied clock. However, there are many RAMs having different capacities in the system LSI, and there are cases where clocks having a plurality of frequencies with different periods are used. Accordingly, the time required for writing the test pattern differs depending on the combination of these, and therefore there are a plurality of timings for inputting the pause signal. When trying to cope with such a situation by arranging conventional RAM test circuits, there is a problem that a plurality of terminals for inputting pause signals at different timings are required.
[0017]
In addition, after the pause is released, in order for the BIST control circuit to resume operation and continue the read operation, it is natural that the internal state of the BIST control circuit needs to be held even during the pause period. However, even if the RAM contents are saved after the scan test, if the BIST control circuit itself is scan-tested during the pause period of the RAM pause test, the internal state of the BIST control circuit is destroyed. There was a problem that the tests could not be executed at the same time.
[0018]
(3) In the conventional RAM test circuit, the path for transmitting the signal S147 in the RAM test mode using the BIST control circuit is different from the path for transmitting the signal S141 during normal operation. Therefore, even if the actual speed timing test by the BIST control circuit is PASS, the actual speed timing test in the normal operation mode may fail. That is, there is a problem that a strict operation speed inspection in normal operation cannot be performed by a conventional RAM test circuit.
[0019]
The present invention has been made to solve the above-described conventional problems, and provides a semiconductor test circuit and a test method thereof capable of shortening a semiconductor inspection time and performing a strict operation speed inspection of a memory. The purpose is to do.
[0020]
[Means for Solving the Problems]
In order to solve the above problems, the present invention Half of The conductor test circuit is a semiconductor circuit having a normal circuit capable of a scan test and a memory connected to the normal circuit so that no new value is written in the memory while the normal circuit is in the scan test mode. And a circuit for fixing an input signal to the memory.
As a result, the normal circuit scan test and the memory pause test can be superimposed without destroying the state of the memory during the normal circuit scan test.
[0021]
In addition, the present invention Half of The conductor test circuit is a semiconductor circuit having a normal circuit capable of a scan test and a memory connected to the normal circuit so that no new value is written in the memory while the normal circuit is in the scan test mode. And a circuit for fixing a clock signal to the memory.
As a result, the normal circuit scan test and the memory pause test can be superimposed without destroying the memory state during the normal circuit scan test.
[0022]
The present invention Half of The conductor test circuit includes a BIST control circuit for inspecting the memory in a semiconductor circuit having a normal circuit capable of a scan test and one or a plurality of memories connected to the normal circuit, and the BIST control circuit Has a first operation mode in which a test pattern is written in the memory and automatically stopped, and a second operation mode in which a value written in the memory is read and compared with a predetermined expected value. It is characterized by.
This eliminates the need for external pause timing control in the memory pause test using the BIST control circuit, and also allows the BIST control circuit itself to perform a scan test during the pause test.
[0023]
The present invention Half of Conductor test circuit Above A semiconductor test circuit comprising one or more memories connected to the normal circuit and a BIST control circuit for inspecting the memory, wherein the BIST control circuit writes a test pattern to the memory And a second operation mode in which a value written in the memory is read and compared with a predetermined expected value.
This eliminates the need for external pause timing control in the memory pause test using the BIST control circuit, and allows the BIST control circuit itself to perform a scan test during the pause test. It is also possible to superimpose the scan test and the memory pause test.
[0024]
The present invention Half of Conductor test circuit Above In a semiconductor test circuit, an input signal from the normal circuit or an input signal from the external input terminal is selected and supplied to the memory based on an external input terminal and a switching signal linked to a scan test mode selection signal. And in the scan test mode, the memory is connected to the external input terminal via the selector.
As a result, a memory test from the outside can be performed while performing a scan test of a normal circuit, and is particularly effective when a scan test and a memory test based on, for example, a March algorithm, etc., which are not pause tests, are superimposed.
[0025]
The present invention Half of The conductor test circuit includes a selector, a BIST control circuit for inspecting the memory, in a semiconductor circuit having a normal circuit including a first FF as an FF in front of the memory and the memory connected to the normal circuit; The first signal supplied from the normal circuit to the memory and the second signal supplied from the BIST control circuit to the memory are connected to the selector, and the output of the selector is It is connected to the first FF, and the output of the first FF is connected to the memory.
As a result, with a simple circuit configuration, the signal during normal operation and the signal during memory test pass through the same propagation path, so that a strict write timing test of the memory using the BIST control circuit is possible. In addition, since the signal from the normal circuit or BIST control circuit to the memory is once received by the FF, the failure detection rate of these scan tests can be increased.
[0026]
The present invention Half of Conductor test circuit Above In the semiconductor test circuit, the normal circuit further includes a second FF as a FF in the latter stage of the memory, and an output of the memory is connected to the second FF, and the second FF is connected to the second FF. Each output is configured to be connected to the normal circuit or the BIST control circuit.
This makes it possible to perform a strict read timing test of the memory using the BIST control circuit with a simple circuit configuration, and to input a test pattern from the FF at the subsequent stage of the memory to the normal circuit or the BIST control circuit. The failure detection rate can be improved.
[0027]
The present invention Half of Conductor test circuit Above The semiconductor test circuit includes a selector and a BIST control circuit for inspecting the memory, and the normal circuit further includes a first FF as an FF in the previous stage of the memory. A first signal supplied to the memory and a second signal supplied from the BIST control circuit to the memory are connected to the selector, and an output of the selector is connected to the first FF, The output of the first FF is configured to be connected to the memory.
Accordingly, the scan test and the memory pause test can be performed in parallel, and at the same time, the memory speed test using the BIST control circuit can be performed with a simple circuit configuration. The failure detection rate of the control circuit scan test can also be increased.
[0028]
The present invention Half of Conductor test circuit Above The semiconductor test circuit includes a selector, and the normal circuit further includes a first FF as an FF in the previous stage of the memory, the first signal supplied from the normal circuit to the memory, and the BIST The second signal supplied from the control circuit to the memory is connected to the selector, the output of the selector is connected to the first FF, and the output of the first FF is sent to the memory. It is set as the structure connected.
As a result, the scan test and the pause test can be performed in parallel, and at the same time, a strict speed test of the memory using the BIST control circuit can be performed with a simple circuit configuration, and the normal circuit and the BIST control circuit can be performed. The failure detection rate of the scan test can be improved.
[0029]
The present invention Half of Conductor test circuit Above In the semiconductor test circuit, the normal circuit further includes a second FF as a FF in the latter stage of the memory, and an output of the memory is connected to the second FF, and the second FF is connected to the second FF. Each output is configured to be connected to the normal circuit or the BIST control circuit.
As a result, the scan test and the pause test can be performed in parallel, and at the same time, a strict speed test of the memory using the BIST control circuit can be performed with a simple circuit configuration, and the normal circuit and the BIST control circuit can be performed. The failure detection rate of the scan test can be improved.
[0030]
The present invention Half of The conductor test method is for a semiconductor circuit having a normal circuit capable of a scan test, one or a plurality of memories connected to the normal circuit, and a BIST control circuit capable of performing a scan test for inspecting the memory. A first test step for canceling a write prohibition state to the memory and writing a test pattern to the memory using the BIST control circuit; and a write prohibition state to the memory. A second step of simultaneously performing a scan test of one or both of the normal circuit and the BIST control circuit, and releasing the write-inhibited state to the memory, and writing to the memory in the first step A third step of reading out the value using the BIST control circuit and comparing it with an expected value. It is intended to.
As a result, the scan test and the memory pause test can be superimposed.
[0031]
The present invention Half of The conductor test method selects a normal circuit capable of a scan test, a memory connected to the normal circuit, an external input terminal for sending an input signal to the memory, and an input signal from the normal circuit or the external input terminal. A semiconductor test method for testing a semiconductor circuit having a selector for supplying to the memory in parallel with performing a scan test of the normal circuit in a scan test mode. In this case, the memory is tested by performing writing and reading from the external input terminal with respect to the memory which has been separated.
Thereby, a scan test and a memory test can be superimposed.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, a semiconductor test circuit and a semiconductor test method according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a diagram showing a configuration of a semiconductor test circuit according to the first embodiment of the present invention.
[0033]
In FIG. 1, reference numeral 101 denotes a semiconductor normal circuit, 111 and 112 denote a part of the FF included in the normal circuit 101, 102 denotes a clock synchronous memory (RAM), and 115 denotes a RAM 102 other than the FF 111 and FF 112 of the normal circuit 101. , A BIST control circuit for testing the RAM 102, 125 and 126 are FFs in the BIST control circuit 103, and 105 is a prohibition circuit for prohibiting writing to the RAM 102.
[0034]
A signal S141 (CS, RE, ADR, DATA, etc.) from the normal circuit 101 to the RAM 102 is input to the RAM 102 via the selector 121 via the FF 111. Similarly, a signal S147 from the BIST control circuit 103 to the RAM 102 is also input to the RAM 102 via the selector 121 via the FF 111. The output signal S144 from the RAM 102 is input to the normal circuit 101 and the BIST control circuit 103 via the FF 112.
[0035]
The selector 121 is controlled by the ramtest signal S161, selects one of the input signal S141 from the normal circuit 101 and the input signal S147 from the BIST control circuit 103, and supplies the selected signal to the RAM 102 via the FF111. That is, when the ramtest signal S161 is ON, the selector 121 selects the input S147 from the BIST control circuit 103, and when the ramtest signal S161 is OFF, the selector 121 selects the input S141 from the normal circuit 101. To the RAM 102.
[0036]
The clock signal S150 is supplied to each of the normal circuit 101, the BIST control circuit 103, and the write inhibit circuit 105, and the clock signal S152 is supplied from the write inhibit circuit 105 to the RAM 102.
[0037]
A write prohibition signal to the RAM 102, that is, a protect signal S153 is input to the write prohibition circuit 105. When the protect signal S153 is asserted, the clock supply to the RAM 102 is stopped, thereby making it impossible to write to the RAM 102. That is, when the protect signal S153 is asserted, in the first embodiment, writing to the RAM 102 becomes impossible regardless of whether the ramtest signal S161 and the scanmode signal S151 are on or off.
[0038]
Note that the normal circuit 101 and the BIST control circuit 103 have a configuration in which a separate scan test circuit is incorporated, and when the scanmode signal S151 is asserted, the scan test mode is switched to enable a scan test from the outside. The details of the scan test circuit are complicated, and the description in FIG. 1 is omitted.
[0039]
The BIST control circuit 103 performs a first operation (CW: Checker Pattern Write) sequence for writing a test pattern in a certain area of the RAM and a second test pattern that reads the test pattern written in the certain area and compares it with an expected value incorporated therein. (CR: Checker Pattern Read) sequence. A series of signals S147, which are generated by the CW operation of the BIST control circuit 103 and write a test pattern in the RAM, are written as a test pattern in the RAM 102 via the selector 121. A series of signals that are generated by the CR operation of the BIST control circuit 103 and read the test pattern written in the RAM are also sent to the RAM 102 via the selector 121, and the data S144 read from the RAM 102 becomes S146 via the FF 112. The BIST control circuit 103 receives S146, compares it with an internal expected value, and outputs the determination result as a bistfail signal S165.
[0040]
In addition, the BIST control circuit 103 starts the RAM test operation by the bistrun signal S162. In the RAM test operation, the BIST control circuit 103 first performs the CW operation if the 0th bit of the bistmode signal S163 is 1, and moves to the next operation if it is 0. In the next operation, if the first bit of the bistmode signal S163 is 1, the CR operation is performed, and if it is 0, the next operation is performed. In the next operation, the BIST control circuit 103 asserts the bistdone signal S164 and outputs it to the outside, and the operation is automatically stopped.
[0041]
Next, the operation of the BIST control circuit 103 will be described with reference to the flowchart shown in FIG.
As shown in FIG. 5, in the BIST control circuit 103, first, in step S501, the bistrun signal S162 is shifted from the initial state where it is 0 to step S502. In step S502, initialization is performed, the bistdone signal S164 and the bistfail signal S165 are set to 0, respectively, and the process proceeds to step S503. Step S503 waits until the bistrun signal S162 becomes 1, and when the bistrun signal S162 becomes 1, the process proceeds to step 504. In step S504, the 0th bit of the bistmode signal S163 is checked. If it is 1, the process proceeds to step S505. If not, the process skips step S505 and proceeds to step S506. In step S505, a signal sequence necessary for writing the test pattern in the test target memory is generated and output to the test target RAM 102, and the process proceeds to step S506. In step S506, the first bit of the bistmode signal S163 is checked. If it is 1, the process proceeds to step S507. If not, the process skips step S507 and proceeds to step S508. In step S507, a signal sequence for reading data from the memory under test is generated, and the values read from the memory are sequentially compared with expected values built in the BIST control circuit 103. If they do not match, 1 is set to the bistfail signal S165. Output as. Thereafter, the process proceeds to step S508. In step S <b> 508, 1 is output as the bistdone signal S <b> 164, indicating the end of processing outside the BIST control circuit 103.
[0042]
Next, the semiconductor circuit inspection operation in the semiconductor test circuit and the semiconductor test method according to the first embodiment will be described with reference to the timing chart of FIG.
When the ramtest signal S161 asserted in the period 481 is input, the selector 121 selects the output S147 of the BIST control circuit 103 and sets it to be supplied to the RAM 102. Also, bistmode = 01 is input, and the BIST control circuit 103 is prepared to execute only the CW operation.
[0043]
In a period 482, the bistrun signal S162 is asserted, and the BIST control circuit 103 starts the RAM test operation. First, a sequence for generating a built-in test pattern is executed to generate a test pattern, which is written into the RAM 102 via the selector 121 and the FF 111. This completes the (first) CW operation, and the BIST control circuit 103 outputs 1 to the bistdone signal S164 and automatically stops. In the period 483, the protect signal S153 is input from the outside to the RAM write inhibit circuit 105, and the RAM 102 is placed in a protected state, and ready for the next scan test.
[0044]
In a period 484 after the RAM 102 is set in the protected state, the scanmode signal S151 asserted from the outside is sent to the normal circuit 101 and the BIST control circuit 103, and the normal circuit 101 and the BIST control circuit 103 enter the scan test mode. Subsequently, a scan test of the normal circuit 101 and the BIST control circuit 103 is performed. That is, a control signal, a test signal, and the like are sent from the outside to a FF for a scan test provided in the normal circuit 101 and BIST control circuit 103 by a predetermined scan input pin, and the result of the scan test is transmitted from the predetermined scan output pin It is received and compared with a predetermined expected value externally, and a result indicating whether the normal circuit 101 and the BIST control circuit 103 pass the scan test is obtained.
During the scan test, the RAM 102 is in the pause test state.
[0045]
When the scan test is completed, in a period 485, the protect signal S153 is turned off to release the RAM 102 from the protected state. Also, bistmode = 10 is input, and the BIST control circuit 103 is prepared to execute only the CR operation. In the period 486, when the bistrun signal S162 is asserted, the BIST control circuit 103 enters the second operation mode. Then, S144 read from the received data is received via the FF 112, compared with the built-in expected value, and the result is output to the outside as a bistfail signal S165. When all the comparisons are completed, the (second) CR operation is finished, and the BIST control circuit 103 outputs 1 to the bistdone signal S164 and automatically stops.
[0046]
As shown in FIG. 4, 301 is a scan test period, and 311 is a RAM pause test period. The RAM pause test period 311 here is a test pattern writing period 312 to the RAM, a RAM pause period 313 that prohibits the operation of the RAM for a certain period, and a value in the RAM written in the period 312 is read and compared with an expected value. It consists of a period 314.
481 is a CW operation preparation period, 482 is a CW operation period, 483 is a scan test preparation period, 484 is a scan test period, 485 is a CR operation preparation period, and 486 is a CR operation period.
[0047]
That is, in the first embodiment, the scan test and the RAM pause test are performed in parallel during the pause period of the RAM pause test, so that the total test time 402 between the scan test and the RAM pause test is the conventional total test shown in FIG. It is shortened compared to time 322.
[0048]
Further, since the BIST control circuit 103 automatically stops after the CW operation, the BIST control circuit is temporarily stopped immediately after the end of the CW operation using the conventional pause signals 330 to 332 as shown in FIG. There is no need for external control.
[0049]
As described above, in the semiconductor test circuit and the test method according to the first embodiment, the write prohibit circuit for prohibiting writing to the RAM during the pause period of the RAM pause test, the external input to the memory, and the normal circuit to the memory. Selector for logically connecting the input to the memory, a write operation mode that automatically stops after writing the test pattern to the memory, and a read / expected value comparison mode that reads the written value and compares it with the expected value The selector is arranged further to the front stage than the FF at the front stage of the memory, and the output of the memory passes through the FF at the rear stage before being sent to the normal circuit and the BIST control circuit. Since the data is input, even if test data is written in the memory in advance by the memory write inhibit circuit Even if the internal state of the BIST control circuit is changed (destroyed) by executing a scan test during the pause period, the BIST control circuit is completely read / expected after the pause period. Since the operation can be resumed from the value comparison (CR operation) mode, the scan test of the normal circuit and the BIST control circuit can be performed in parallel during the pause period of the RAM pause test, which is necessary for the test of the semiconductor circuit. Total test time can be reduced.
[0050]
Also, the BIST control circuit automatically stops after writing the test pattern for the pause period of the memory pause test, eliminating the need for external pause control that has been required in the past, and particularly having a different capacity as in the system LSI. Complicated control from the outside, which is necessary when there are a large number of memories, is unnecessary, and the number of necessary input terminals can be reduced.
[0051]
The operating frequency of the memory is determined by the propagation time of the FF from the FF in the previous stage of the memory to the memory and from the memory to the subsequent stage of the memory. In the first embodiment, a selector that separates the normal system and the memory test system is arranged further upstream than the FF in the previous stage of the memory, so that the path from the FF in the previous stage of the memory to the memory is the same as that in the normal operation and the memory test. The signal propagation path is exactly the same during operation. The path from the memory to the subsequent stage of the memory is the same. Therefore, if the actual speed test of the memory is performed during the memory test operation, the inspection is strictly equivalent to the actual speed test of the memory during the normal operation. In addition, since FFs are arranged before and after the memory, a failure detection rate by a scan test of a circuit that communicates with the memory is improved.
[0052]
In the first embodiment, the RAM has been described as an example of the memory. However, the present invention is not limited to other types of memory, in particular, a memory having a mechanism for holding data by charge, such as a flash ROM. , The same effect can be exhibited.
[0053]
In the first embodiment, the description has been given of the case where the test is performed on the memory using the BIST control circuit. However, instead of the BIST control circuit, the memory is written and read by the external input terminal. Even in the test, the memory pause test and the normal circuit scan test can be performed in parallel. Similarly, if the actual speed test of the memory is performed during the memory test operation, the test is strictly equivalent to the actual speed test of the memory during the normal operation.
[0054]
In the first embodiment, the clock supplied to the RAM is stopped by the RAM write prohibition circuit as a method for prohibiting access to the RAM. However, in the case of a clock asynchronous RAM, the RAM write enable or chip select is stopped. You may decide to prohibit access by the method of fixing.
[0055]
Further, even when the control signal to the RAM can be directly controlled from the outside during the scan test, the scan test and the test for the memory can be similarly superimposed.
[0056]
【The invention's effect】
As described above, the present invention Half of According to the conductor test circuit, a new value is written in the memory while the normal circuit is in the scan test mode in a semiconductor circuit having a normal circuit capable of a scan test and a memory connected to the normal circuit. Since the circuit for fixing the input signal to the memory is provided so that the state of the memory is not destroyed by the scan test during the pause period of the memory pause test, the memory test and the scan test are performed. And the total test time between the scan test and the memory pause test can be shortened.
[0057]
In addition, the present invention Half of According to the conductor test circuit, a new value is written in the memory while the normal circuit is in the scan test mode in a semiconductor circuit having a normal circuit capable of a scan test and a memory connected to the normal circuit. Since the circuit for fixing the clock signal to the memory is provided so as to prevent the clock signal from being supplied to the memory during the pause period even if the test data is written in the memory in advance as in the invention according to claim 1. Since the data cannot be overwritten and the data cannot be overwritten, the memory test and the scan test can be performed in parallel without destroying the data. There is an effect that the time can be shortened.
[0058]
The present invention Half of According to the conductor test circuit, the BIST control circuit for testing one or a plurality of memories writes a test pattern to the memory and automatically stops the operation mode, and the value written in the memory. Since the BIST control circuit automatically stops after the writing of the test pattern for the pause period of the memory pause test, because the second operation mode for comparing the current read and the predetermined expected value is provided. There is no need for external pause control, which was necessary in the past, especially when there are many memories with different capacities like system LSIs, and there is no need for complicated external control, and the number of required input terminals can be reduced. There is an effect that can be. In addition, even if the scan test is executed during the pause period and the internal state of the BIST control circuit changes and is lost, the BIST control circuit can resume operation from the read / expected value comparison mode completely after the pause period. Therefore, the scan test of the normal circuit and the BIST control circuit can be executed simultaneously during the pause period of the memory pause test, and the semiconductor test time can be shortened.
[0059]
The present invention Half of According to the conductor test circuit Above In a semiconductor test circuit, an input signal from the normal circuit or an input signal from the external input terminal is selected and supplied to the memory based on an external input terminal and a switching signal linked to a scan test mode selection signal. In the scan test mode, the memory is connected to the external input terminal via the selector, so that a memory test can be performed while performing a normal circuit scan test. When a test and a memory test that is not a pause test such as a march are superimposed, there is an effect that the test time of the semiconductor can be effectively shortened.
[0060]
The present invention Half of According to the conductor test circuit, the signal propagation path during the memory test and the signal propagation path during the normal operation are made the same. In other words, the actual speed test of the memory is performed, that is, there is an effect that a strict equivalence check can be performed.
[0061]
The present invention Half of According to the conductor test method, a normal circuit capable of a scan test, one or a plurality of memories having different internal configurations connected to the normal circuit, and a BIST control circuit capable of a scan test for inspecting the memory, A semiconductor test method for testing a semiconductor circuit including: a first step of releasing a write-inhibited state in the memory and writing a test pattern in the memory using the BIST control circuit; A second step of setting a write-inhibited state to the memory, simultaneously performing a scan test of one or both of the normal circuit and the BIST control circuit, releasing the write-inhibited state to the memory, and A third step of reading the value written in the memory in the step using the BIST control circuit and comparing it with an expected value . Thus having, it is possible to superimpose a pause test scan test and a memory, there is an effect that it is possible to shorten the semiconductor inspection time.
[0062]
The present invention Half of According to the conductor test method, a normal circuit capable of a scan test, a memory connected to the normal circuit, an external input terminal that sends an input signal to the memory, and an input signal from the normal circuit or the external input terminal A semiconductor test method for performing a test on a semiconductor circuit having a selector to be selected and supplied to the memory, wherein the normal circuit is performed in parallel with a scan test of the normal circuit in a scan test mode. Since the memory is logically disconnected from the external input terminal, the memory test is performed by writing and reading from the external input terminal, so that it is possible to superimpose a scan test and a memory test. The inspection time can be shortened.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a semiconductor test circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a conventional test circuit.
FIG. 3 is an operation timing chart of a conventional test circuit.
FIG. 4 is an operation timing chart of the semiconductor test circuit according to the first embodiment of the present invention.
FIG. 5 is an operation flowchart of the BIST control circuit according to the first embodiment of the present invention.
[Explanation of symbols]
101 Normal circuit
102 memory
103 BIST control circuit
105 RAM write inhibit circuit
111, 112, 125, 126, 225, 226 flip-flop
121 selector
S 150, S 152 clock signal
S 151 Scan test mode signal
S 153 RAM write inhibit control signal
S 161 Memory test mode signal
S 162 BIST execution control signal
S 163 BIST content setting signal
S 164 BIST execution end signal
203 Conventional BIST Control Circuit
330 to 332 BIST stop control timing during conventional pause test

Claims (2)

A semiconductor for testing a semiconductor circuit having a scan testable normal circuit, one or a plurality of memories connected to the normal circuit, and a scan testable BIST control circuit for inspecting the memory A test method,
A first step of canceling the write prohibition state to the memory and writing a test pattern to the memory using the BIST control circuit;
A second step of setting a write prohibition state to the memory and simultaneously performing a scan test of one or both of the normal circuit and the BIST control circuit;
A third step of canceling the state of prohibiting writing to the memory, reading the value written in the memory in the first step using the BIST control circuit, and comparing the read value with an expected value. Semiconductor test method. A normal circuit capable of a scan test, a memory connected to the normal circuit, an external input terminal for sending an input signal to the memory, and an input signal from the normal circuit or the external input terminal is selected and supplied to the memory A semiconductor test method for testing a semiconductor circuit having a selector,
In parallel with performing the scan test of the normal circuit in the scan test mode, writing and reading from the external input terminal to the memory logically separated from the normal circuit, the test of the memory A semiconductor test method characterized in that:

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