JP2005164265A - Method for testing integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform the test of an ASIC, without requiring a complicated circuit or an unnecessary external pin, and to perform the test of the ASIC without troublesome procedure or useless use of a program area. <P>SOLUTION: In the method for testing the integrated circuit, the operation of the integrated circuit having a microprocessor and a storage means is tested. The method includes a storage step for storing a program in the storage means and a control step for performing the control according to the program, wherein, in the control step, the test of the operation of the integrated circuit is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for verifying the operation of an integrated circuit (ASIC) that controls an electronic device such as a printer that performs recording using a recording head.

  As ASIC (integrated circuit) manufacturing technology advances, more and more logic functions are accommodated in a single ASIC. In modern ASICs, a large number of gates are arranged on one silicon chip, and by interconnecting such gates, complicated functions such as printer image processing can be realized. The manufacture of such a large-scale ASIC requires that there be no mistakes in the inside thereof, and thus it is necessary to perform various electrical tests after the manufacture of the chip.

  However, as functions become more complex, the cost and difficulty of verifying and electrical testing each device in the circuit has increased. From an electrical test standpoint, in order to verify that each ASIC gate is functioning properly, in principle (digitally, each gate is either open or closed). Not only can each of the gates be executed individually), it must be able to be executed by any conceivable combination of operations while remaining relevant to the other gates in the circuit.

  Conventionally, such a chip test is performed by an automatic inspection device (ATE) that performs a desired test using a test vector. Here, the test vector is the desired test input (or signal) for all package pins during a given time, the associated one clock pulse (or multiple pulses), and the expected test output (or signal). It is also often used when trying to check a particular macro. An ASIC having a complicated function has a large number of test vectors, and therefore the test time is often long.

  In addition, the creation of such a large number of test vectors by the designer himself has made it possible to use an event-driven simulator that has become considerably faster at the present time. , You are forced to bear a heavy burden.

  Due to such problems, design for testability (DFT) has been promoted in recent years. The purpose of DFT is to increase the ability to observe the inside of the ASIC from external inputs and outputs. In other words, in addition to the functions originally expected from the ASIC (eg, printer image processing, etc.), a module capable of transmitting the functions through specific pins of the ASIC is built in in advance, and a simple test vector Enables chip test by input / output.

  One example often used in DFT is the scan path. The scan path is composed of a series of synchronous clocked master / slave latches or registers, and each latch is connected to a specific node of the logic circuit. Such a latch can be loaded with a serial data stream (scan-in) with the logic circuit nodes preset to a predetermined state. Therefore, the logic circuit can be exercised by a normal method, and the operation result (at each node having the scan latch) is stored in each latch. By unloading (scanning out) the contents of the latch in series, it is possible to read out the result of a specific test operation at the relevant node and analyze the incorrect node operation.

  In addition, the test vector required at this time is normally the most rational and reduced vector can be created by using an inspection pattern automatic generation tool (ATPG). . However, at present, it is not true that all ASIC inspections can be performed by the ASIC test method using this scan path. That is, as described above, the ASIC test method based on the scan path is based on the premise that the module (DUT) to be tested can be observed by a series of synchronous clock type master / slave latches or registers. It is.

  Therefore, (1) if there is a latch that operates asynchronously with a series of synchronous clocks in the ASIC, (2) if the latch has an asynchronous reset (regardless of whether the operating condition is synchronous or asynchronous), and (3) The probability that there is a logic cone out of the scan path, such as when a new synchronous latch is added by ECO after the floorplan is implemented, is not low enough to be ignored.

For example, in the ASIC inspection, about 90% of the chip is tested by scan test, and the remaining 10% (= module out of scan path) is inspected by the test vector created by the designer. There are many cases to do.
JP-A-6-148281.

  However, the ASIC inspection (test) method described above has the following drawbacks. That is, as a recent technological trend, an ASIC of a type called system-on-chip (SOC) in which various memories such as MPU, user logic (UDL), ROM and RAM are included in one chip, If the data bus or address bus for system control inside the chip is closed internally (not open outside the package), the necessary part of the system bus inside the chip is brought out and a vector is given from there. It is normal to perform a chip test while going.

  For example, there is a method of assigning the bus signal to an external pin in advance in an ASIC package so that it can be operated at any time. According to this means, there is no relation at the time of normal operation of the ASIC, and pins used only at the time of the chip test are present in the external pins of the ASIC at least for the system bus control signal.

  Since the unit price of an ASIC greatly depends on the package size, it is rare to increase the number of external pins and design with a large exterior package specification because it easily increases the cost.

  Therefore, the currently adopted method is to reassign the system bus inside the chip to some external pin (ie, it is an external pin assigned by other functions such as motor control in the normal operation mode). There is a method of creating a test mode like this, entering the test mode at the time of chip test, and giving a test vector from the reassigned external pin.

  However, if all the system buses inside the chip are reassigned to the outside, the total number of address buses, data buses, and control buses will be 60 or more. Therefore, reassigning all the system buses in a certain test mode makes the functions of the same number of pins unusable. As a result, the function test of that part cannot be performed. For example, if the system bus is assigned to the motor control pin only during the test, the motor cannot be tested.

  In such a case, the test mode is classified into several types, “in test mode 1, the system bus is assigned to the pin of function A, and function B is usable and the function test is performed”, “in test mode 2, There is also a method of deciding a function test to be performed for each mode, such as assigning a system bus to the pin of function B, and performing a function test with function A being usable. However, the system bus assignment method is increased because there is a need to set the mode in which each pin can be used, so that there is always one mode, such as when planning detailed tests so that all function pins can be tested. (For example, nearly 20 types). In such a case, the mechanism for reassigning the external pin of the system bus according to each test mode is a simple selector, so it looks like a simple mechanism. However, the signal lines of 60 or more system buses are connected to the mode. If it is possible to select with this, the circuit scale on the chip becomes large. In the peripheral portion of the external pin, it is particularly difficult to adjust the timing of the internal signal in creating the ASIC. If a large-scale circuit exists in this portion, the timing adjustment becomes more difficult.

  Recently, for example, there is a platform having an original test mechanism such as ARM's TIC (test interface controller), etc., and the number of external pins (ie, test bus assignment to the external pins becomes easier, and the test mechanism) There is also a mechanism that can manipulate a large internal system bus.

  However, there are cases where this test mechanism itself does not match the chip test policy of the semiconductor vendor and cannot be used for testing (the reason why the system bus read cycle at the time of testing does not match the equipment of other companies (semiconductor vendors). for). Of course, there is a method of redesigning itself to match the same mechanism with the vendor's equipment, but a test mechanism that does not cause bus concentration is designed and arbitration is performed so that it functions as a bus master inside the ASIC system. When even a circuit is incorporated, it becomes a heavy work load.

  Another test mechanism using a test vector is a test using a ROMized object and an MPU. That is, the MPU fetches the machine code from the ROM, decodes it, and performs an operation. In this operation, the UDL necessary part is stimulated. The disadvantage of this approach is that it is difficult to perform the test unless the ROM fetch bus is on an external pin of the ASIC.

  If the ROM fetch bus is output to an external pin of the ASIC, a test can be performed by applying a machine code corresponding to the PC to the external pin of the ASIC in response to a request signal output from the ASIC. However, if no external pin is available, it is necessary to mount a test vector in advance in the ROMized object. This reduces the program area in ROM, which is used for chip testing. It is not suitable to use the code by replacing it.

  As described above, the present case tests the ASIC without the need for complex circuitry or useless external pins. It is another object of the present invention to perform an ASIC test without complicated procedures and unnecessary use of program areas.

  In order to solve the above-mentioned problems and achieve the object, the present invention is an integrated circuit test method for testing the operation of an integrated circuit having a microprocessor and storage means, and a storing step of storing a program in the storage means And a control step of performing control according to the program. The control step comprises performing an operation test of the integrated circuit.

  As described above, according to the present invention, by effectively using the functions originally provided in the ASIC, a complicated circuit for an ASIC test and an increase in unnecessary external pins are suppressed, and complicated procedures and An increase in the program area can be suppressed, and chip testing can be performed with a simple configuration.

  Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings. In the embodiment described below, an integrated circuit (ASIC) for controlling a printer will be described as an example. The ASIC will be described as including an MPU, UDL, and various memories (RAM, MUP ROM, etc.).

[First Embodiment]
FIG. 1 shows a typical configuration of the present embodiment. There is an ASIC 1-1 to be tested, which is connected to an automatic inspection device (ATE) 1-2 via external pins 1-3 of the ASIC 1-1 for testing. The external pins include a CLK pin and a RESET pin necessary for the operation of the ASIC 1-1.

  Next, inside the ASIC 1-1, as also assumed above, the MPU 1-11 that manages the entire system of the printer, the circuit block UDL1-12 designed by the user, the RAM 1-13, and the MPU1- 11 ROM 1-14 is included. Here, the RAM 1-13 may be either a D-RAM or an S-RAM. In some cases, the RAM 1-13 may be a combination of several D-RAM and S-RAM modules. .

  As for the connection between the MPU 1-11 and various modules, data communication between the modules is basically performed by the address bus 1-15 and the data bus 1-16. In particular, the address bus 1-15 is once inputted to the address decoder 1-17, generates a chip select signal group 1-18 for each module, and distributes it to each module in a bundle with the address bus. It is assumed that data communication control is being performed.

  For example, when the MPU accesses the UDL 1-12, the CS 1-180 in the chip select signal group 1-18 becomes active, and when the MPU accesses the RAM 1-13, the CS select 180 in the chip select signal group 1-18. When CS1-181 becomes active and the MPU accesses the ROM 1-14, CS1-182 in the chip select signal group 1-18 becomes active. Here, for the sake of convenience, description will be made using three CSs. Usually, the number of CSs essential for access is included in the chip select signal group 1-18.

  Next, the test circuit mechanism will be described. First, when the RAM 1-13 or the ROM 1-14 is built in the ASIC 1-1, a test mechanism (test block) for confirming whether each cell in the RAM 1-13 and the ROM 1-14 has been normally manufactured. Is implemented.

  Here, it will be referred to as memory test means (memory test circuit) 1-19. At the time of testing, the assignment of external pins is different from that during normal operation, so a test bus selector 1-20 for determining the state of external pins is provided. Furthermore, a test control pin 1-31 for notifying the ASIC system that the specified test mode has been entered is also provided in the external pin 1-3 of the ASIC 1-1. The test control pins 1-31 are provided according to the number of test mode separations.

  In this embodiment, it is sufficient if the number of necessary modes, that is, three modes can be separated. For example, as shown in FIG. 3, the number of test control pins 1-31 is determined as two and (pin0, pin1) = (0, 0): normal operation mode, (pin0, pin1) = (1, 0): RAM test mode, (pin0, pin1) = (0, 1): scenario test mode, pin (pin0, The mode is defined according to the state of pin1).

<Explanation about memory test means>
Next, the operation of the memory test means 1-19 will be described briefly. For example, a memory BIST (built-in self-test) or the like is a typical memory test means, and a general configuration is as shown in FIG.

  Hereinafter, although it is a known technical content, an outline of the operation will be described. First, by inputting the test control pin 1-31, the system of the ASIC 1-1 is put into a mode in which the RAM 1-13 can be separated (in this embodiment, (pin0, pin1) = (1, 0): RAM test) Mode).

  Here, the signal line required for the memory test becomes accessible from the external pin 1-3 of the ASIC 1-1 through the test bus selector 1-20. With the above operation, the system of the ASIC 1-1 is ready to test the RAM 1-13.

  Next, test setting 2-1 is performed from a memory test external pin assigned to the external pin 1-3 of the ASIC 1-1. The test settings referred to here are, for example, settings such as inspection address: 0x ----, data used for confirmation: 0x ----, verification start: on, etc. (these are at a high level of abstraction). Setting). Receiving these test settings 2-1, the memory BIST (memory test means) 1-19 performs verification with a specific transaction in a form matching the RAM 1-13.

  That is, first, the memory BIST 1-19 writes the data designated at the address designated in the test setting 2-1 to the RAM 1-13. At this time, writing is performed in accordance with the RAM 1-13 mechanism. For example, if the RAM 1-13 is S-RAM, the timing for S-RAM is generated, and if it is SD-RAM, the timing for SD-RAM is generated, and the memory BIST (memory test means) 1-19 is RAM 1-13. (Here, it is referred to as a test signal input 2-2 including a transaction (to a memory)).

  Further, the memory BIST 1-19 performs data read-back from the address where the writing is performed. At this time, data is read in a form that matches the RAM 1-13 mechanism (here, it is referred to as a test signal output 2-3 including a transaction (to the memory)).

  Next, the memory BIST (memory test means) 1-19 holds the written data value (this is stored in a register in the memory BIST (memory test means) 1-19 before being written to the RAM 1-13). The read data values are compared, and if both are the same value, it is determined that the cell at the test address: 0x ---- is normal. If the two are different, it is determined that the cell at the test address: 0x ---- is abnormal. The result is transmitted through the external pin of the ASIC 1-1 (usually, this can be easily determined by whether the signal is “H” or “L”).

  The RAM 1-13 is tested by repeating the above operation for all the cells (address to which the RAM 1-13 is assigned).

  As described above, this technique is known and is said to have the following advantages. (1) Since the BIST (= memory test means) has a memory access part, it is not necessary to output all signals necessary for memory access to the external pins of the ASIC (that is, a test bus selector). (2) Since the test is focused only on the memory, it is possible to assign the test pin to the outside without considering the actual use of the external pin of the ASIC (that is, together with the memory) Since the motor is not tested, a test control pin can be assigned to the motor pin).

<Description of operation>
FIG. 5 is a flowchart showing the operation of this embodiment. First, immediately after the test is started (S-100), the system of the ASIC 1-1 enters a mode in which the RAM 1-13 can be separated and tested (P-101). That is, the test control pin 1-31 pin (pin0, pin1) = (1, 0): the RAM test mode is entered, and the RAM 1-13 can be separated and tested. At this time, depending on the system of the ASIC 1-1, there is a case where the specified mode cannot be entered unless an external reset signal is input.

  Next, program data is written into the RAM 1-13 using the operation in the RAM test mode (P-102). This program can be executed by the MPU 1-11, and the execution content of the program needs to be a thing that can test the ASIC 1-1 by the MPU 1-11. For example, it may be a part of the UDL 1-12 that is missing from the scan path, may be a path that is missing in various separation tests, or may be a DC test of the external pins 1-3 of the ASIC 1-1. In short, it is only necessary to make a program that can be executed by the MPU 1-11 into a test item that has been omitted from the ATPG or separation test and is to be verified at the time of shipment from the factory.

  After the necessary program has been written to the RAM 1-13, the RAM 1-13 is temporarily removed from the separation testable mode (P-103) and enters a different test mode. At this time, depending on the system of the ASIC 1-1, the mode cannot be changed unless the external reset signal is input again. In such a case, the restrictions of the system of the ASIC 1-1 are followed.

  At this time, the mode to be entered next is the pin (pin0, pin1) = (0, 1) of the external pin 1-3 of the ASIC 1-1: scenario test mode (P-104). This mode is a mode in which the MPU 1-11 actually executes the program written in the RAM 1-13. At this time, naturally, if MPU 1-11 is run without any mechanism, the PC (program counter) will definitely go to the reset vector (because it will fly), so the test scenario on RAM 1-13 will be executed. It will disappear.

  Accordingly, in the present embodiment, the pins (pin0, pin1) of the external pins 1-3 of the ASIC 1-1 = (0, 1): When entering the scenario test mode, the ROM 1-14 operates in conjunction with the address decoder 1-17. The mechanism (configuration) in which the system address of the RAM 1-13 and the system address of the RAM 1-13 are interchanged.

  That is, when the MPU 1-11 tries to access the program on the ROM 1-14 after this address exchange, the RAM 1-13 already exists in the RAM 1-13. It will access the -13 object. That is, the MPU 1-11 is nothing but the inspection of the ASIC 1-1 by itself.

  In this way, the MPU 1-11 is used to test each part of the ASIC 1-1 based on the executable program in the RAM 1-13 = validation scenario (P-105). Then, after the execution of necessary test items is completed, the test is terminated (E-106).

  The termination method is that the ASIC 1-1 system and the MPU 1-11 operate on the basis of the clock given from the external pin 1-3 of the ASIC 1-1, so that the number of clocks necessary to perform the verification scenario to the end. It is sufficient to finish the test after confirming that the number of clocks (+ α) has been given.

  The number of clocks required to complete the verification scenario can be counted when the pattern confirmation is performed by the event-driven simulator before the actual ASIC 1-1 can be written to the tester. In addition, when the test is finished, if an executable program = verification scenario is worried about runaway, a dynamic stop routine (= infinite loop) is used as in the program shown in FIG. 7 (C language description example). As a result, the PC of the MPU 1-11 continues to stay at an appropriate position.

  First, in this example, the description has been made assuming that the memory test means 1-19 is a BIST, but this need not necessarily be a BIST. For example, when the object to be verified by the memory test means 1-19 is an S-RAM or the like, the memory interface is so simple that the BIST is not solved and all the S-RAM buses are connected to the external pins 1 of the ASIC 1-1. In many cases, the memory test is performed directly after assigning to -3.

  Further, since the test scenario can be written in the S-RAM, the characteristic operation of the present embodiment, that is, the flowchart-1 can be performed. Conversely, when using BIST, if a BIST of a type that automatically generates addresses and data internally is designed, it cannot be used in this case. Although there is no problem with the address, the test scenario cannot be realized unless the data can be written freely according to the designer's intention.

Furthermore, a mechanism is created to reflect the results of the ASIC chip test on external pins. That is, in the scenario test mode, no test bus or the like is assigned to the external pin 1-3 of the ASIC 1-1. If the result of the test (= operation) is reflected on any of the external pins 1-3 of the ASIC 1-1 like a motor, there is no problem at all, but the function like DMA is verified by a chip test. When the processing is completely closed inside the ASIC 1-1, such as when it is desired, the following is performed.
(1) The DMA results in the destination are sequentially read and dispensed to the general-purpose port. (2) The expected value of the DMA result is also converted into a data table in the test scenario and downloaded to the RAM 1-13 together with the data table. Then, the scenario is configured so that the expected value can be compared. If there is a mismatch, the motor is rotated counterclockwise. Continue.

  As described above, in the present embodiment, it is possible to perform a vector input test using the functions (here, MPU, RAM, RAM test mechanism, etc.) attached to the ASIC system. Here, the newly added configuration is about two external pins for testing and its decoding circuit, which is a very simple configuration.

  Another feature of the MPU is that the MPU performs the ASIC stimulus rate, but since the program is written in the RAM, the ROM area to be used in the normal mode is not wasted.

[Second Embodiment]
Next, a second embodiment will be described. In the above example, the scenario test mode is provided as the mode for performing the ASIC chip test. This method may not be suitable. That is, first, since a new test mode is provided in this way, it is necessary to separate it from other modes (in this case, it is called a system mode different from the normal mode and the RAM test mode). Need a way to do that). In the above-described embodiment, this is determined by the state of the test control pin 1-31 that is a part of the external pin 1-3 of the ASIC 1-1. Increasing the number of pins in the ASIC causes a cost increase. Therefore, in the present embodiment, means for realizing the function equivalent to the above-described example in the normal mode (= actual use mode of ASIC) will be described.

<Description of configuration>
The basic configuration is roughly equivalent to FIG. However, unlike the first embodiment, since the scenario test mode is eliminated, the mode to be separated is reduced by one among several system modes as shown in FIG. 3 (however, the RAM test mode is necessary). This eliminates the need for the control signal 1-21 (shown in dotted lines) in FIG. That is, the function to be assigned to the test control pin 1-31 that is a part of the external pin 1-3 of the ASIC 1-1 is reduced by one (= suggesting that one test pin can be reduced), and the mode is changed. It can be seen that the configuration is simplified from the first embodiment by eliminating the need to decode one and reducing the number of signal lines.

<Description of operation>
FIG. 6 shows an operation flow of the second embodiment.

  Basically, the same operation as in FIG. 5 is performed during (S-200)-(P-203). First, immediately after the test is started (S-200), the system of the ASIC 1-1 enters a mode in which the RAM 1-13 can be separated by the information on the test control pin 1-31 (P-201), and the RAM 1-13 is tested. Program data is written (P-202). After the necessary test scenario has been written to the RAM 1-13, the RAM 1-13 is temporarily removed from the mode in which the separation test is possible (P-203).

  At this time, depending on the system of the ASIC 1-1, the mode cannot be changed unless the external reset signal is input again. In such a case, the restrictions of the system of the ASIC 1-1 are followed. When the ASIC 1-1 requests reset from the external pin 1-3 at the time of (P-201) and (P-203), the restriction that the ASIC 1-1 follows that is also the same as in FIG.

  Next, unlike the flow of FIG. 5, the scenario mode is entered instead of the normal mode (P-204). If the program is run without doing anything, the normal operation of the ASIC 1-1 is entered, so a new device for testing is required. And it is first made in the code in ROM1-14.

  After entering the normal mode, the ASIC 1-1 system sets the PC to a specified address and executes the startup routine program in the ROM 1-14. The contents performed here are various, such as system initialization, stack setting, and bus access cycle number setting, and depend on the system of the ASIC 1-1. After the start-up is completed, the system of the ASIC 1-1 branches to the execution of the program at the normal operation (with a branch instruction corresponding to the MPU 1-11). Therefore, the following very simple work is performed in this startup routine program.

  That is, the system of the ASIC 1-1 next determines whether to perform a normal operation or to execute a test scenario, and this is performed by the following method. Typically, there are several ports on the ASIC external pins that can read their logical values directly (ie, with a digital value of “1”, “0”, not a voltage value). For example, the port can be used for various purposes, such as reading on / off of a switch of a device on which an ASIC is mounted, or reading values of various sensors. In short, the state is divided by using the input value of the port. For example, the external pin 1-3 of the ASIC 1-1 has two input ports, both of which are used for ON / OFF reading of a certain type of switch (schematically, FIG. 4). become that way). And, if the input port 0 and the input port 1 in Fig. 4 are never in the state of (input port 0, input port) = (1, 1) at the same time during normal operation, Separate behavior and test scenario behavior.

  This is not necessarily limited to (input port 0, input port) = (1, 1), and any state such as (0, 0), (1, 0), (0, 1) may be used. Absent. In addition, if it is impossible to distinguish between two input ports, the same mechanism may be realized using three or more input ports. On the contrary, if the separation can be performed by one input port, the same mechanism may be realized by using one input port.

  Furthermore, it is also important that the location where this separation is performed is in the startup routine, that is, since the PC passes through the startup routine only once after the hard reset is released, it is synchronized with this timing. Then, a combination of input patterns determined in advance (which is usually impossible) may be considered.

  For example, in the above example, (input port 0, input port) = (1, 1) is in the normal normal operation of the ASIC 1-1 system, but immediately after the hard reset is released. If such an input is not possible, (input port 0, input port) = (1, 1) can be sufficiently used as a separation pattern of normal operation and test scenario operation.

  Returning to the flowchart 2 again, the flow as described above will be described. That is, immediately after the PC enters the startup routine program in the ROM 1-14 (input port 0, input port). A small program for polling logical values is installed (P-205).

  If (input port 0, input port) = (1, 1), the process branches to the test scenario routine written in the RAM 1-13 (P-206), that is, the PC is written into the RAM 1-13. Point the start address of the test scenario routine.

  Conversely, if the value is other than (input port 0, input port) = (1, 1), the program is mounted in the ROM 1-14 so as to branch to the normal operation routine (E-208).

  As a program for this processing, processing such as load of input port value-> pattern comparison-> flag jump is executed, so that it can be executed with a machine code of about 3 words at the worst. That is, a part of the program area in the ROM 1-14 is used for chip test, but the size of the program can be ignored.

  This is the end of the description of the characteristic part of the present embodiment, but a supplementary explanation is added for some points.

  It is preferable that the test program for separating the test scenario and the normal operation in the startup routine described above is performed as early as possible after entering the startup routine. The reason is that if the time to enter the test scenario is long, the time for chip test is extended.

  The startup routine program initializes the ASIC 1-1 system, which is initialized assuming normal operation. However, the system initialization required for a test scenario is usually different, for example, stack, heap or global variable initialization has no meaning if the test scenario does not use it. . In addition, the bus cycle may not be determined for a part that is used in normal operation but is not used in a test scenario. The point is that if you do not create a separation program that strictly considers the necessary initialization and what is not, it will be a wasteful chip test. This is an important point to keep in mind.

  As described above, the second embodiment can realize a simpler test configuration than the first embodiment.

  The outline of the ASIC test mechanism (configuration) described above will be described below.

  The ASIC to be tested has means capable of analyzing the micro program and performing control operations according to the contents of the micro program, analyzing the micro program, and It has a readable / writable storage device for storing programs for means capable of performing control operations according to the contents of the micro program, and can perform control operations according to the contents of the micro program. This means performs a chip test on the ASIC to be tested by itself according to the contents of the micro program in the writable / readable storage device.

  Further, it has means capable of performing a control operation according to the contents of the micro program, and the means capable of performing the control operation according to the contents of the micro program is an MPU.

  Further, the ASIC to be tested has an MPU capable of analyzing a micro program and performing a control operation according to the contents of the micro program, and for storing the MPU program. It has a readable / writable storage device and basically has a mechanism to perform chip verification using boundary scan, which is a well-known technology, but it is excluded from the scan path and verification is required. For the logic module in the ASIC, the MPU is removed from the scan path according to the contents of the microprogram in the writable / readable storage device, and verification is required. The logic module in the ASIC is tested by itself.

  Further, the writing of the internal logic module test test program to the writable / readable storage device is provided separately from the ASIC test mechanism proposed in claim 3 above, and the writable / readable memory is provided. It is performed using a test mechanism dedicated to the apparatus.

  Further, the ASIC to be tested has an MPU capable of analyzing a micro program and performing a control operation according to the contents of the micro program, and for storing the MPU program. A storage device test device having a storage device that can be written and read, and capable of testing the storage device that can be written and read by a mechanism different from the test mechanism intended by the present proposal, In addition, while having a mechanism for performing chip verification using boundary scan, which is a known technology, the logic module inside the ASIC that is excluded from the scan path and requires verification, A program for testing the logic module in the ASIC that requires the verification using the storage device test device. RAM is written to the writable / readable storage device, and the MPU is removed from the scan path and verified according to the contents of the written test program in the writable / readable storage device. It is characterized in that the necessary logic module inside the ASIC is tested by itself.

Explanatory drawing of the ASIC test mechanism of 1st Embodiment which concerns on this invention. Explanatory drawing of the memory test means of 1st Embodiment Explanatory drawing of the test pin function of 1st Embodiment. Explanatory drawing of the input / output pin function of 2nd Embodiment. The operation | movement flow of 1st Embodiment. The operation | movement flow of 2nd Embodiment. Example program

Explanation of symbols

ASIC1-1 ASIC
ATE1-2 ATE
1-3 ASIC external pins 1-11 MPU
1-12 UDL
1-13 RAM
1-14 ROM
1-15 Address Bus 1-16 Data Bus 1-17 Address Decoder 1-18 Chip Select Signal Group 1-19 Memory Test Means 1-20 Test Bus Selector

Claims (3)

An integrated circuit test method for testing an operation of an integrated circuit having a microprocessor and a storage means, comprising:
A storage step of storing a program in the storage means, and a control step of performing control according to the program,
The method of testing an integrated circuit, wherein the control step performs an operation test of the integrated circuit.   2. The integrated circuit testing method according to claim 1, wherein the control step is performed by the microprocessor.   A test method for an integrated circuit, wherein the operation test is performed using a boundary scan.

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