US6415403B1 - Programmable built in self test for embedded DRAM - Google Patents
Programmable built in self test for embedded DRAM Download PDFInfo
- Publication number
- US6415403B1 US6415403B1 US09/334,569 US33456999A US6415403B1 US 6415403 B1 US6415403 B1 US 6415403B1 US 33456999 A US33456999 A US 33456999A US 6415403 B1 US6415403 B1 US 6415403B1
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- test
- state machine
- finite state
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
- G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Definitions
- This invention relates to testing of integrated circuits and in particular to testing embedded DRAM's
- U.S. Pat. No. 5,825,785 Barry et al.
- a built in self test circuit receives a scan vector that describes the parameters of the embedded macro that is to be tested.
- U.S. Pat. No. 5,764,655 Kerrihata et al.
- an integrated circuit chip is described that contains a built in self test and a nonvolatile RAM and includes an RF circuit for transmitting test results to a detector external to the chip.
- the present invention is described in C. Huang et al., “A Programmable BIST CORE for Embedded DRAM”, IEEE Design & Test of Computers, January-March 1999, pp 2-13.
- BIST built-in self-test
- Testing embedded memories such as DRAM's, is more difficult than testing commodity memory chips because of the accessibility of the embedded memory.
- the surrounding logic must be isolated and a design for testability can result in extra hardware overhead.
- An external memory tester is expensive, and considering the increased speed and bandwidth associated with embedded memories, it is difficult to produce an adequate test capability. Trying to maintain an adequate test capability in an environment of engineering change only adds to the difficulties of an external tester.
- Providing a built in self test capability allows a much simpler and less costly tester to be used in testing a chip containing an embedded memory.
- the embedded memory With built in self test the embedded memory can be more easily isolated and can be tested at operating speeds. Testing at higher levels of assembly to can provide diagnostics in situ.
- a built in self test can test for critical timing during wafer test, pre-burn-in test, burn-in test and final test. Providing the user the capability to program different test algorithms and optimize the tests for a specific embedded memory adds important flexibility to built in self test.
- the BIST is constructed of a controller circuit and a sequencer circuit.
- the controller circuit provides test sequences to the sequencer circuit that generates test data and timing sequences to be applied to the embedded DRAM.
- a comparator located in the sequencer is used to compare the output data to the input data of the DRAM and produces a go/no go signal which is connected to an external tester.
- the controller circuit includes a BIST controller which is a finite state machine, multiple scan chains used to provide test commands, diagnostic information, and a BIST scan path for testing the BIST logic except the finite state machine.
- the BIST controller controls the scan chains, shifting in test patterns and commands, and shifting out results.
- the finite state machine controls the BIST scan operation which is done first to insure that the built in self test circuitry is operating properly.
- the sequencer circuit accepts commands and diagnostic information from the controller circuit and turns the commands into timing sequences and data to be connected to the embedded DRAM.
- the comparator contained within the sequencer circuit compares data outputted from the DRAM to the original input data and creates an error signal when a discrepancy is found.
- Timing sequences are created with the use of counters and a timing generator contained within the sequencer circuit.
- DRAM interface buffers contained within the sequencer circuit provide for address data, row and column access signals, write enable and data input and data output to be connected to the embedded DRAM.
- the sequencer output signals to the embedded DRAM are glitch free resulting from the state transition of the finite state machine being on the rising edge of the BIST clock and the control signals for the DRAM being on the falling transition.
- the BIST controller finite state machine is configured to control the operations of the BIST by selecting a test mode, decoding the commands of the test mode, scanning in test patterns, executing the tests and pausing for observations or a retention test.
- the length of the pause for retention test is a user determined length of time, and the finite state machine can be reset to an initial state by the application of four consecutive logical zeros from any operational state.
- the BIST supports several test modes including a scan test, a memory test, a burn-in test and a timing fault test.
- the scan test is used to test the BIST except the controller finite state machine to insure correct functionality before testing of the embedded DRAM takes place.
- the BIST functionally tests the DRAM using march algorithms which exercises the DRAM in page and non-page modes. During march testing of the DRAM, read-write sequences are moved from cell to cell across the rows and columns of the embedded DRAM.
- the BIST also tests refresh and memory retention.
- the burn-in test exercises the entire embedded memory and can use a march algorithm supported in the memory test mode.
- Timing fault testing is accomplished by running the BIST clock at an appropriate speed and determining whether various memory operations were performed within the clock period. These timed memory operations include setup time, hold time, and data arrival time for various controls and data signals.
- the sequencer is designed for flexibility and can be used with a wide range of embedded memories of different dimensions and timing requirements.
- the sequence controller finite state machine generates timing sequences for single read/write commands as well as for page mode read/write commands for march elements defined in the controller.
- the page mode access cycle comprises a row access followed by a sequence of column access.
- the DRAM under test first latches the row address and then latches, one by one, the column address for the whole page.
- the sequencer also tests a DRAM refresh mechanism for a variety of refresh states, including self refresh, hidden refresh and RAS only refresh state.
- the sequencer outputs are implemented such as to be glitch free when the BIST is in use and in a high state when the BIST is not in use.
- the state transitions are timed to be on the rising edge of the BIST clock and the control timing signals for the DRAM are on the falling edge of the clock producing glitch free sequencer outputs. If test time is important, testing multiple memory banks and multiple words simultaneously with multiple built in self test sequences can be used to reduce test time.
- FIG. 1 is a circuit diagram of the memory BIST of this invention
- FIG. 2 is a state diagram of the BIST controller finite state machine
- FIG. 3 is a timing diagram for the BIST control circuit sequence
- FIG. 4 is a state diagram of the sequence controller for march tests and refresh.
- FIG. 1 a block diagram of the memory BIST 10 of this invention.
- the memory BIST 10 is comprised of a controller circuit 11 and a sequencer circuit 12 .
- An embedded DRAM 13 is connected to a DRAM interface buffer 14 within the sequencer circuit.
- the DRAM interface buffer 14 connects data D, address ADDR, row access signal xRAS, column access signal xCAS, and write enable xWE to the embedded DRAM 13 , and receives from the DRAM 13 data output Q.
- a sequence controller 15 receives commands and data from the controller circuit 11 and controls the row address counter 16 and the column address counter 17 to produce the appropriate address sequence exercise the DRAM 13 for the various march and burn-in tests.
- a control counter 18 is also controlled by the sequence controller 15 to produce the timing of signals from the timing generator 19 to control the timing sequence of signals connected to the DRAM 13 from the interface buffer 14 .
- Data is transferred from the sequence controller 15 to the data composer 20 which inputs data D to the DRAM 13 through the interface buffer 14 .
- Data form the data composer 20 is also connected to the comparator 21 which received data out Q from the DRAM 13 .
- the comparator compares the input data D from the data composer 20 to the output data Q from the DRAM 13 and outputs a go/no go signal BGO.
- the sequence controller 15 outputs a BRD signal that indicates when a particular BIST sequence is finished and the BGO signal is valid and can be read for that test sequence.
- a BIST controller 22 operating as a finite state machine where the state transitions are controlled by the BIST control section input BCS.
- a BIST clock BCK is connected to the memory BIST 10 to provide clocking to the controller circuit 11 and the sequencer circuit 12 .
- An activation control signal BAC connected to the BIST controller 22 is at a logical zero when the DRAM is in normal operations and goes high to a logical one to activate the BIST logic to test the embedded DRAM 13 .
- the BIST controller 22 controls scanning in data through a scan input BSI into the scan chains 24 and scanning out data through the multiplexer 25 to the scan output BSO.
- the decode logic 23 and the test mode selection 26 determine which data register to scan in the test commands and when complete activate the sequencer circuit 12 .
- the BRS input signal to the BIST controller 22 resets the BIST and implements a scan of all registers in the BIST controller 22 and the logic in the memory BIST 10 excluding the BIST controller 22 . This insures that everything is operating properly before commencing test of the embedded DRAM 13 .
- the scan chains 24 allow different tests to be performed on the embedded DRAM 13 ranging from non-page mode to page mode where data is either read or written to more complex sequences where data is read, complimented and immediately written back to the DRAM 13 . These tests can be performed under timing control to check the performance of the embedded DRAM 13 .
- a burn-in test sequence allows not only for the burn-in testing of the chip and eliminates the need for a tester until at burn-in test..
- a state diagram is shown for the finite state machine of the BIST controller 22 for testing the embedded DRAM 13 .
- the numbers associated with the arrows between states represent state transitions controlled by BCS as do any numbers associated with the state transition arcs 40 .
- the decode state 43 decodes commands and generates internal control signals including selecting the appropriate scan chain for shifting in a data sequence.
- FIG. 3 is shown the BIST circuit control sequence.
- the BIST circuit When the BAC control signal is high, a logical one, the BIST circuit is activated to test the embedded memory 13 . All signals are synchronized with the BIST clock, BCK.
- the BRS signal is pulled high along with BCS at the beginning of the BAC control signal to perform a scan test to verify that the BIST controller is operating correctly. Scan chains are formed between BSI and BSO to apply patterns and collect responses.
- the BRS signal is pulled low to reset the BIST controller, and BCS remains low to generate a reset sequence.
- the BRD and BGO signal are also brought low, and the BIST controller performs a scan test for the remainder of the BIST circuitry.
- a test algorithm is applied to the embedded DRAM 13 in accordance with the control sequence of the finite state machine shown in FIG. 2 .
- BRD is brought high and BGO is sampled to read out the test results.
- BAC is set to a low state to return the DRAM 13 to normal operations.
- FIG. 4 is shown the state diagram of the sequence controller finite state machine for march and refresh tests.
- Timing sequence generation modules shown as circles in FIG. 4, are implemented for single read/write commands 63 and page mode (Pg M) read/write commands 64 for march tests defined in the controller 11 .
- the test sequences performed on each cell of the embedded DRAM are: Ra read; Wa write; RaWa′ read contents of cell, complement and immediately write back the complement; and RaWa′Ra′ read contents of cell, complement and immediately write back the complement, and read back the compliment from the cell.
- the row address is latched first by the embedded DRAM 13 .
- a refresh test 65 is performed to cover self refresh, hidden refresh and RAS only refresh, and a refresh 62 of the embedded DRAM 13 is accommodated by the built in self test to allow the memory cells to be maintained a proper state.
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Abstract
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Cited By (47)
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US20020083380A1 (en) * | 2000-12-20 | 2002-06-27 | Robert Kaiser | Integrated circuit having a data processing unit and a buffer memory |
US20020089887A1 (en) * | 1996-04-30 | 2002-07-11 | Hii Kuong Hua | Built-in self-test arrangement for integrated circuit memory devices |
US20020147949A1 (en) * | 2001-04-10 | 2002-10-10 | International Business Machines Corporation | Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test |
US20030033558A1 (en) * | 2001-08-07 | 2003-02-13 | Parvathala Praveen K. | Tool for generating a re-generative functional test |
US6532571B1 (en) * | 2000-01-21 | 2003-03-11 | International Business Machines Corporation | Method to improve a testability analysis of a hierarchical design |
US6546503B2 (en) * | 1999-01-19 | 2003-04-08 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device capable of reducing test cost and method of testing the same |
US20030084386A1 (en) * | 2001-10-25 | 2003-05-01 | Barth John E. | ECC Based system and method for repairing failed memory elements |
US20030131307A1 (en) * | 2002-01-10 | 2003-07-10 | Taylor Richard D. | System and method of recovering from soft memory errors |
US20030159095A1 (en) * | 2002-02-15 | 2003-08-21 | Wehage Eric R. | Low cost built-in self test state machine for general purpose RAM testing |
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US6691264B2 (en) * | 2001-01-22 | 2004-02-10 | Lsi Logic Corporation | Built-in self-repair wrapper methodology, design flow and design architecture |
US20040049724A1 (en) * | 2002-07-22 | 2004-03-11 | Colin Bill | Built-in-self-test (BIST) of flash memory cells and implementation of BIST interface |
US20040103356A1 (en) * | 2002-11-26 | 2004-05-27 | Infineon Technologies North America Corp. | Modular test controller with BISTcircuit for testing embedded DRAM circuits |
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US20080195901A1 (en) * | 2007-02-12 | 2008-08-14 | Marvell Semiconductor Israel Ltd. | Op-code based built-in-self-test |
US7533309B2 (en) | 2004-02-26 | 2009-05-12 | Nilanjan Mukherjee | Testing memories using algorithm selection |
US20100052727A1 (en) * | 2000-11-30 | 2010-03-04 | Fujitsu Limited | Synchronous semiconductor device, and inspection system and method for the same |
US7721175B2 (en) | 2007-08-21 | 2010-05-18 | Micron Technology, Inc. | System, apparatus, and method for memory built-in self testing using microcode sequencers |
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US20130326295A1 (en) * | 2012-05-31 | 2013-12-05 | SK Hynix Inc. | Semiconductor memory device including self-contained test unit and test method thereof |
US20140177371A1 (en) * | 2012-12-20 | 2014-06-26 | Lsi Corporation | Suspend sdram refresh cycles during normal ddr operation |
US20140258780A1 (en) * | 2013-03-05 | 2014-09-11 | Micron Technology, Inc. | Memory controllers including test mode engines and methods for repair of memory over busses used during normal operation of the memory |
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US6546503B2 (en) * | 1999-01-19 | 2003-04-08 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device capable of reducing test cost and method of testing the same |
US6532571B1 (en) * | 2000-01-21 | 2003-03-11 | International Business Machines Corporation | Method to improve a testability analysis of a hierarchical design |
US6671837B1 (en) * | 2000-06-06 | 2003-12-30 | Intel Corporation | Device and method to test on-chip memory in a production environment |
US6622274B1 (en) * | 2000-09-05 | 2003-09-16 | Advanced Micro Devices, Inc. | Method of micro-architectural implementation on bist fronted state machine utilizing ‘death logic’ state transition for area minimization |
US6928593B1 (en) * | 2000-09-18 | 2005-08-09 | Intel Corporation | Memory module and memory component built-in self test |
US7424660B2 (en) | 2000-11-13 | 2008-09-09 | Omar Kebichi | Synchronization point across different memory BIST controllers |
US7036064B1 (en) * | 2000-11-13 | 2006-04-25 | Omar Kebichi | Synchronization point across different memory BIST controllers |
US20100052727A1 (en) * | 2000-11-30 | 2010-03-04 | Fujitsu Limited | Synchronous semiconductor device, and inspection system and method for the same |
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US6757857B2 (en) * | 2001-04-10 | 2004-06-29 | International Business Machines Corporation | Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test |
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US20030033558A1 (en) * | 2001-08-07 | 2003-02-13 | Parvathala Praveen K. | Tool for generating a re-generative functional test |
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