JP2003344502A - Semiconductor integrated circuit and its failure analyzing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the test pattern required for analyzing the failure of a semiconductor integrated circuit while enhancing the efficiency of failure analysis by interrupting the operation at a moment at the time of observing the internal condition and making it possible to resume the operation after the internal condition of the semiconductor integrated circuit was observed from the outside thereof. <P>SOLUTION: A shift feedback selector 25 for selecting one of two signals inputted to a scan chain is provided and a signal being inputted from the outside of the semiconductor integrated circuit or an output signal from the scan chain is selected. A scan chain having a small number of flip-flops is provided with additional flip-flops such that the number of the flip-flops becomes constant among the scan chains. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit capable of reducing a test pattern for failure analysis of a semiconductor integrated circuit and improving failure analysis efficiency, and a failure analysis method thereof.

[0002]

2. Description of the Related Art A scan method is often adopted as a method of testing a logic portion in which a desired logic circuit is built in a semiconductor integrated circuit.

FIG. 3 is a circuit diagram of the inside of a conventional semiconductor integrated circuit equipped with a scan circuit. In the figure, a symbol "□" to which a symbol SEN, a symbol CLK and the like are attached is a terminal for inputting or outputting a signal to the outside of the semiconductor integrated circuit.

In this scan method, the logic portion of the semiconductor integrated circuit is divided into blocks for each function to form a circuit, and a scan flip-flop is provided for each signal between blocks. Further, the internal signal of the semiconductor integrated circuit is externally monitored by shifting the data taken in the scan chain constituted by the scan flip-flop (shift mode).

For example, in FIG. 3, the logic circuit parts 10 to 12 are shown.
There are three blocks. Further, between these blocks, a flip-flop 22 is provided as a scan circuit together with the selector 21 for each signal. Selector 21
Is a scan enable signal S that controls switching selection.
EN is input.

When a semiconductor integrated circuit is normally operated,
Set the scan enable signal SEN to "0 (L state)"
(Normal operation mode) is set and the clock signal CLK is tapped.

On the other hand, when the internal state of the semiconductor integrated circuit is monitored by the scan method, the scan
Each time the enable signal SEN is set to "1 (H state)" and the clock signal CLK is hit, the data fetched from the internal circuit and held in the scan flip-flop can be shifted, and the data is shifted. Each time, it can be observed outside the semiconductor integrated circuit from the output terminals SOUT1 and SOUT2. In the shift process, the data input from the outside of the semiconductor integrated circuit is shifted between the scan flip-flops by the input terminals SIN1 and SIN2, and thus the data held in the scan flip-flops is set from the outside. You can do it.

By the scanning method, when testing the operation of each block inside the semiconductor integrated circuit, the pattern input from the outside of the semiconductor integrated circuit is scanned.
Let's call it a pattern. Further, the test patterns other than the scan pattern will be called function patterns.

In the failure analysis for finding the failure location after the failure is found due to the mismatch of expected values by the test, if the operating state of the semiconductor integrated circuit is observed only by the normal output signal, the output signal Even if there is an abnormality, which part of the internal malfunction causes the abnormality,
It is difficult to estimate. For example, even if the output signal OUT1 is abnormal in FIG.
It is almost impossible to estimate which part of the operation is malfunctioning.

On the other hand, when the scan path method is adopted for the failure analysis, the signal input / output states of the logic circuit parts 10 to 12 can be observed from the outside of the semiconductor integrated circuit. It is possible to estimate which part of ˜12 has a malfunction.

For example, in the process of inputting a certain function pattern to the semiconductor integrated circuit of FIG. 3 from the outside, a malfunction (fault) is found in the semiconductor integrated circuit, and in order to find the internal part of the malfunction, Failure analysis shall be performed. 2A to 2E are time charts showing the operation of the conventional failure analysis. The function pattern is “function pattern” shown at the top of FIG.
Pattern a ”, which has a time length of 7000 nS, for example. The "function pattern a" is not a pattern dedicated to the scan path method,
It is also used for other purposes. Also, in the process of inputting the “function pattern a”, 0 nS
2000nS after starting (2010n)
It is assumed that malfunction occurs due to a failure at the time when S has elapsed and when 2020 nS has elapsed.

In such a failure analysis, the internal state of the semiconductor integrated circuit is analyzed at the time point when these 2000 nS have elapsed, 2010
The internal state of the semiconductor integrated circuit is observed from the outside at the time point when nS has elapsed and the time point when 2020nS has elapsed.
Moreover, in order to observe at these respective time points, "function pattern b" to "function pattern d" as shown in FIG. 2 are used.

First, the shaded portion of "function pattern b" is the same as the pattern from "0 nS (at the time of start)" to "2000 nS after elapse" in "function pattern a". Next, the shaded portion of "function pattern c" is "function pattern a".
It is the same as the pattern from 0 nS (at start) to after 2010 nS. In addition, "function
The shaded portion of "pattern d" is from 0 nS (at the start) to 2020 nS in "function pattern a".
It is the same as the pattern up to the lapse. In other words, in any of the shaded areas, 0 nS (at the start) in the "function pattern a" is added to the beginning of the area.
There is the same pattern as that after 000 nS. Further, the portions denoted by reference numeral P1 are the same as each other, and the internal state of the semiconductor integrated circuit held in the scan chain is read out while being shifted, and is observed or held in the scan chain. This is an operation for setting data from the outside.

For example, when the scan path method is adopted for the failure analysis in FIG. 3 and there is an abnormality in the signal output from the logic circuit portion 10 and held in the flip-flop 22 indicated by the symbol F04, the logic in the figure is used. It is estimated that there is an abnormality in the range indicated by the alternate long and short dash line of the circuit portion 10.
Further, when the signal output from the logic circuit portion 10 and held in the flip-flop 22 with the code F05 is abnormal,
It is estimated that there is an abnormality in the range indicated by the chain double-dashed line of the logic circuit portion 10 in the figure. Further, the flip-flop 22 with the code F04 output from the logic circuit portion 10
And the signal held by the flip-flop 2 with the code F05
If there is an abnormality in the signal held in 2, it is estimated that there is an abnormality in the circuit in the hatched area rising to the right in the figure.

[0015]

However, there is a problem even when the scan path method is used for the failure analysis. That is, in the failure analysis, the scan enable signal SEN is set to “1” and the clock signal CLK is sequentially input from the outside of the semiconductor integrated circuit at a plurality of time points at which it is estimated that the malfunction is caused by the failure, and the logic Circuit part 10
Each of the operating states (1) to (12) is observed from outside the semiconductor integrated circuit. When observing each of these points,
It is necessary to reproduce the initial state of the semiconductor integrated circuit for each observation at each time point, and the reproduced operation state is shifted in the scan chain to output the output signals SOUT1 and SOUT.
Observed from the outside as OUT2. For example, in FIG. 2, in order to observe a time point after 2000 nS has elapsed from 0 nS (at the start), a time point after 2010 nS, and a time point after 2020 nS, the internal state of the semiconductor integrated circuit is initialized each time, It is necessary to perform each of the function pattern b ”to the“ function pattern d ”.

This is because, in FIG. 2, when the internal state of the semiconductor integrated circuit is shifted and observed at the portion P1, the logic state held in the scan chain after the observation is different from that immediately before the observation. Therefore, the operation immediately before the observation cannot be continued after the observation, and it is necessary to reproduce the operation state of the semiconductor integrated circuit from the initial state every time the observation is performed at a desired time.

In the scan path method, when the scan chain is shifted to observe the internal state, the contents of the scan chain immediately before the shift are grasped in advance by simulation or the like and stored in a tester memory or the like. deep. Then, after observing the internal state, based on the storage, for example, the input signal SIN1 or the input signal SIN2 from the outside of the semiconductor integrated circuit of FIG. 1 is input, and the scan chain is reproduced to the contents just before the shift. It is also possible to do it. However, this causes problems such as a need for simulation and a need for a tester memory. Therefore, since the defective portion of the semiconductor integrated circuit is different for each chip, the timing of observing the internal state becomes various, and there is a problem that such a simulation is performed every time and the capacity of the tester memory increases. .

Further, as described above, "function pattern b" to "function pattern d"
When each of the above is sequentially performed, it becomes as shown in the "total time of the pattern" indicated by the symbol e in FIG. As described above, conventionally, there is also a problem that failure analysis takes a long time.

The present invention has been made to solve the above-mentioned conventional problems. When the internal state is desired to be observed, the semiconductor integrated circuit is switched from the normal operation mode to the shift mode, and the semiconductor integrated circuit is externally connected to the shift mode. After observing the internal state of the semiconductor integrated circuit, the shift mode is switched to the normal operation mode so that the stopped internal operation can be resumed continuously, thereby reducing the pattern of failure analysis of the semiconductor integrated circuit, and An object of the present invention is to provide a semiconductor integrated circuit capable of improving failure analysis efficiency and a failure analysis method thereof.

The internal state of the semiconductor integrated circuit is not constant because the data held by the scan flip-flop changes due to the shift, but the internal state is not fixed after the observation is completed. Say.

[0021]

First, a semiconductor integrated circuit according to a first invention of the present application is a semiconductor integrated circuit having a scan chain configured by connecting a plurality of scan flip-flops. The above problem is solved by providing a shift feedback selector for the signal input and selecting a signal input from outside the semiconductor integrated circuit or an output signal of the scan chain. .

Further, in the semiconductor integrated circuit, a plurality of scan chains are provided and the scan
If the number of flip-flops is different between the chains, it is possible to add the flip-flops to the scan chain with few flip-flops so that the scan chains have the same number of flip-flops. After the logical state held in is read, the held logical state can be restored to the initial state at the same time.

Next, in a failure analysis method for a semiconductor integrated circuit according to a second aspect of the present invention, the semiconductor integrated circuit is subjected to failure analysis, the semiconductor integrated circuit is switched from a normal operation mode to a shift mode, and the shift feedback is performed. For selecting the output signal of the scan chain, sequentially reading the data of the scan flip-flop to the outside of the semiconductor integrated circuit while sequentially inputting the clock signal, the number of flip-flops of the scan chain, The problem is solved by switching from the shift mode to the normal operation mode after inputting the clock signal and continuing the operation.

The operation of the present invention will be briefly described below.

According to the present invention, when the output signal of the scan chain is selected by the shift feedback selector, the scan chain is configured like a ring counter. That is, when the clock signal is sequentially input in the selected state, the output signal of the scan chain is input as the input signal of the scan chain and fed back. Therefore, in the scan chain, one cycle of data is sequentially shifted, and the data held in each scan flip-flop returns to the initial state before the one cycle after the one cycle.

Therefore, according to the present invention, when the internal operation of the semiconductor integrated circuit is stopped and then the data is cycled while being sequentially shifted in the scan chain as described above, all of these data are stored in the semiconductor. It can be observed from outside the integrated circuit. Further, since the held data is returned to the initial state after the one cycle, the internal operation of the above stop can be continued thereafter.

As described above, according to the present invention, at the time when it is desired to observe the internal state, the internal operation of the failure analysis observation target of the semiconductor integrated circuit is stopped, and the semiconductor integrated circuit is operated from outside the semiconductor integrated circuit. After observing the internal state, it is possible to continue and restart the internal operation that has been stopped so that the failure analysis pattern of the semiconductor integrated circuit can be reduced and the failure analysis efficiency can be improved.

In the present invention, the internal state of the semiconductor integrated circuit for observing while sequentially shifting the data in the scan chain may be the state after the operation by the scan pattern, or the operation by the function pattern. The present invention is not specifically limited as to how the internal state was obtained.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a logic part built in a semiconductor integrated circuit of an embodiment to which the present invention is applied.

The configuration of the present embodiment applies the present invention to
The shift feedback selector of the present invention is provided at the signal input of the scan chain used for the scan path method failure analysis. The shift feedback selector is a selector that selects one of the two signals, and selects a signal input from outside the semiconductor integrated circuit or an output signal of the scan chain.

Here, when the scan chain is shifted to observe the internal state, the external selection signal SEL input from the semiconductor integrated circuit is set to "1" (H state). In this case, the scan chain is configured as if it were a ring counter, and when the clock signal CLK is sequentially input, the output signal of the scan chain is input as the input signal of the scan chain and fed back.

In the present embodiment, the plurality of scan chains constituted by the flip-flops 22 originally differ in the number of flip-flops between the scan chains. Therefore, by adding the flip-flop 27 to the scan chain having a small number of flip-flops 22,
This ensures that the scan chains have the same number of flip-flops.

In FIG. 1, two flip-flops 27 indicated by reference numerals F11 and F12 are provided in comparison with FIG. 3 described above so that the number of flip-flops is the same. By providing these flip-flops 27, the number of flip-flops 22 that holds the signals passed between the logic circuit portions 10 and 11 is 6
The number is equal to the number (4 + 2 = 6) of the flip-flops 22 and 27 holding the signals transferred between the logic circuit portions 11 and 12.

As described above, when the internal state is observed by shifting the scan chain, the external selection signal S
By setting EL to "1" (H state), the output signal of any scan chain is fed back as its input signal, and the number of flip-flops included in these scan chains is the same. ,
In both cases, the number of shift steps is the same (6 steps). Therefore, when the external selection signal SEL is set to "1" (H state) and the scan chain is shifted six times while sequentially inputting the clock signal CLK, all the flip-flops 22 and 22 The state held in 27 can be observed from the output terminals SOUT1 and SOUT2.

Further, since the output signal of the scan chain is fed back as its input signal during the shift, the state held in the scan chain is not observed after the internal state observation by the number of shifts equal to the number of shift stages. The state before the shift is restored again, and in the present embodiment, after the sixth shift, the state held in the scan chain is restored again to the state before the sixth shift. Therefore, after the six shifts, the logic circuit portion 10
It is also possible to restart the operation of the semiconductor integrated circuit of this embodiment, which has been interrupted during the six shifts, including the respective operation states of 12 above.

For example, in the "function pattern a" of FIG. 2, 0nS (at the start) to 2000nS
Time after S, time after 2010 nS, 2020
Consider a case in which the data representing the internal state of the semiconductor integrated circuit, which is held in the scan chain, is read out and observed outside while being shifted at each time point after nS has elapsed. In this case, in the present embodiment, the test is performed with the pattern shown as the “pattern of the embodiment (hereinafter, referred to as a function pattern f)” shown in FIG.

First, in the internal state observation at the time of 2000 nS, the same function pattern from 0 nS to 2000 nS of "function pattern a" from time ta to tb in "function pattern f" is input. After that, from time tb to tc, the internal state of the semiconductor integrated circuit held in the scan chain is shifted and read out to the outside for observation, as indicated by the symbol P1. The state held in the scan chain after the shift is restored before the shift.

Because of the recovery in this way, the internal state observation at the time of 2010 nS can be continued following the above observation without the need to initialize the semiconductor integrated circuit and the scan chain. Then, in “function pattern f”, 10n from time tc
2000 of "function pattern a" up to S
Input the same function pattern as the pattern from nS to 2010nS. Then, as indicated by the symbol P1, the internal state of the semiconductor integrated circuit held in the scan chain is shifted, read out to the outside, and observed. The state held in the scan chain after the shift observation is restored before the shift.

Subsequent to the observation, the pattern of 10 nS from time td of "function pattern f" is from 2010 nS to 2020 of "function pattern a".
Input the same function pattern as the pattern up to nS. Then, as indicated by the symbol P1,
The internal state of the semiconductor integrated circuit held in the scan chain is shifted and read out to the outside for observation.

In this embodiment, as described above, the operation of the failure analysis observation target is stopped when the internal state is desired to be observed,
It is possible to observe the internal state from the outside of the semiconductor integrated circuit and continue and resume the operation that has been stopped after the observation. As a result, the internal state observation at three time points of 2000 nS time point, 2010 nS time point, and 2020 nS time point is performed at the time point ta of the above-mentioned one “function pattern f” starting at the time point ta, respectively.
This is possible at tc and td, and it is possible to reduce the test pattern for failure analysis of the semiconductor integrated circuit and improve the failure analysis efficiency.

In addition, "function pattern f",
As is clear from comparison with the above-mentioned “total time of pattern” indicated by the reference sign e, according to the present embodiment, the failure analysis time can be shortened.

As described above, the present invention can be effectively applied in this embodiment.

[0044]

According to the present invention, it is possible to reduce the test pattern for failure analysis of a semiconductor integrated circuit and improve the failure analysis efficiency.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a logic unit built in a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the failure analysis of the above-described embodiment and the operation of a conventional example compared with the failure analysis.

FIG. 3 is a circuit diagram of a logic portion inside a semiconductor integrated circuit for performing failure analysis by a general scan path method, which has been conventionally used.

[Explanation of symbols]

10 to 12 ... Logic circuit portion 21 ... Selector 22 ... Flip-flop 25 ... Shift feedback selector SEN ... Scan enable signal CLK ... Clock signals SIN1, SIN2 ... Input signals SOUT1, SOUT2 from outside semiconductor integrated circuit ... Semiconductor integrated circuit External output signal SEL ... External selection signal (for implementing the operation of the present invention)

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2G132 AA01 AB01 AC03 AC14 AD06                       AG00 AG08 AH07 AK07 AK09                       AK11 AK14 AK15 AK23 AK24                       AL09                 4M106 AA01 AA02 AA04 AC01 BA01                 5F038 DF16 DT06 DT15 DT17 DT18                       EZ20

Claims (3)

[Claims] 1. A semiconductor integrated circuit having a scan chain configured by connecting a plurality of scan flip-flops, wherein a shift feedback selector is provided at a signal input of the scan chain, the semiconductor integrated circuit external to the semiconductor integrated circuit. A semiconductor integrated circuit, characterized in that it is configured to select a signal input from the device or an output signal of the scan chain. 2. The semiconductor integrated circuit according to claim 1, wherein a plurality of scan chains are provided, and when the number of flip-flops is different among the scan chains, the flip-flops are provided in a scan chain having few flip-flops. The semiconductor integrated circuit is characterized in that the number of flip-flops is made the same between the scan chains by adding a group. 3. The semiconductor integrated circuit according to claim 2 is subjected to failure analysis, the semiconductor integrated circuit is switched from a normal operation mode to a shift mode, and an output signal of the scan chain is selected by the shift feedback selector. Then, while sequentially inputting clock signals, the data of the scan flip-flops is read to the outside of the semiconductor integrated circuit, and after inputting the clock signals by the number of flip-flops of the scan chain, the normal mode is shifted from the shift mode. A failure analysis method for a semiconductor integrated circuit, comprising switching to an operation mode and continuing the operation.