JP2009085632A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect a fault on a scan chain using a random pattern. <P>SOLUTION: The semiconductor integrated circuit 1 comprises a logic circuit 10, a pattern generation circuit 30, a step-number adjustment circuit 40, and a comparison circuit 60. The logic circuit 10 has N scan chains (11, 12). The pattern generation circuit 30 inputs a random pattern RPAT into input terminals (P1, P2) of the N scan chains (11, 12), respectively. The step-number adjustment circuit 40 has N output terminals (Y1, Y2) and inserts an additional flip-flop between output terminals (Q1, Q2) of the N scan chains (11, 12) and the N output terminals (Y1, Y2), respectively. The comparison circuit 60 performs comparison between patterns (COUT1, COUT2) output from the N output terminals (Y1, Y2), respectively. The step-number adjustment circuit 40 sets the step number of the additional flip-flop to be zero or more and to be variable. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit. In particular, the present invention relates to a semiconductor integrated circuit including a scan chain.

  Scan design is known as a method for design for testability (DFT) of semiconductor integrated circuits. According to the scan design, all or a part of the flip-flops in the design circuit is replaced with the scan flip-flops. At the time of the scan test, the scan flip-flops are connected to each other to form a scan chain (scan path) including multi-stage scan flip-flops. A scan test is performed by inputting and outputting a test pattern through the scan chain (see, for example, Patent Document 1).

  Patent Document 2 describes a technique for detecting a failure of the scan chain itself. Specifically, a plurality of scan chains and a comparison circuit are provided. Before the normal scan test, data “0” or “1” is supplied to all the scan flip-flops. The outputs of the plurality of scan paths are compared with each other by the comparison circuit.

  In addition, a technique for applying stress to an element using a scan chain during a burn-in test is known (see Patent Document 3, Patent Document 4, and Patent Document 5).

  Patent Document 4 describes a technique for easily detecting whether or not an element is destroyed by burn-in. Specifically, a regular pattern “101010...” Is input to a single scan chain during the burn-in test. Then, the EXOR circuit compares the outputs of two scan flip-flops separated by an odd number on the single scan chain. If there is a fault on the scan chain, the output of the EXOR circuit becomes L level.

  Patent Document 5 describes a technique for determining whether or not a desired stress is applied to an element during a burn-in test. Specifically, at the design stage, one scan chain is divided into a first half part and a second half part, and the respective outputs of the first half part and the second half part are connected to the input of the comparison circuit. At this time, the division is performed so that the number of stages in the first half and the second half are equal. When the number of stages of one scan chain is an odd number, a flip-flop is added between the output of the first half part or the second half part and the comparison circuit. During the burn-in test after device manufacture, the same random pattern is simultaneously supplied to the first half and the second half. Then, the comparison circuit compares the outputs of the first half and the second half. If the comparison results do not match, it means that there is a fault on the scan chain. Therefore, it is determined that the desired stress is not applied to the element.

JP 2005-214981 A JP 2006-349548 A JP 2003-302451 A JP 2004-219336 A Japanese Patent Laid-Open No. 2004-233101

  The inventor of the present application paid attention to the following points. In order to detect a failure on the scan chain during the burn-in test, it is conceivable to compare the outputs of a plurality of scan chains. At this time, in order to increase the activation rate of the element, it is desirable to supply “random patterns” to a plurality of scan chains. When a random pattern is used, it is necessary to design so that the number of stages of each of the plurality of scan chains is equal. Otherwise, there is no point in comparing the outputs, and a fault on the scan chain cannot be detected accurately. Therefore, it is necessary to configure a plurality of scan chains so that the number of stages is equal at the stage of circuit design.

  However, defects are often found after circuit design and circuit corrections are often made. In that case, if the circuit design is re-executed from the beginning, the TAT is greatly increased. Therefore, normally, the connection between the nodes is changed in order to eliminate the problem in the upper wiring layer of the base layer in which the transistor or the like is formed. That is, wiring reconnection is performed in the upper wiring layer so as to eliminate the problem.

  The reconnection of the wiring is likely to affect the configuration of the original scan chain. That is, there is a high possibility that the wiring change will disturb the number of scan chain stages at the time of design. Initially, even if each of the plurality of scan chains is designed to have the same number of stages, the number of stages does not match as a result of the subsequent wiring change. In that case, a failure on the scan chain cannot be detected using a random pattern during a test after device manufacture.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In one embodiment of the present invention, the semiconductor integrated circuit (1) includes a logic circuit (10), a pattern generation circuit (30), a stage number adjustment circuit (40), and a comparison circuit (60). The logic circuit (10) has N (N is an integer of 2 or more) scan chains (11, 12). The pattern generation circuit (30) inputs a random pattern (RPAT) to the input terminals (P1, P2) of the N scan chains (11, 12). The stage number adjustment circuit (40) has N output terminals (Y1, Y2), and each of the output terminals (Q1, Q2) of the N scan chains (11, 12) and N output terminals (Y1, Y2). An additional flip-flop (53) is inserted between each of the output terminals (Y1, Y2). The comparison circuit (60) compares the patterns (COUT1, COUT2) output from each of the N output terminals (Y1, Y2).

  The stage number adjustment circuit (40) sets the number of stages of the additional flip-flop (53) to 0 or more and variably. That is, the stage number adjustment circuit (40) can change the stage number of the additional flip-flop (53) according to the situation. For example, in the test, the number of flip-flops between the input terminals (P1, P2) of each of the N scan chains (11, 12) and the N output terminals (Y1, Y2) may be equalized. it can. In other words, the number of stages of a plurality of chains connected to the input of the comparison circuit (60) can be made uniform. As a result, a failure on the scan chain (11, 12) can be accurately detected using a random pattern (RPAT).

  Even if a defect is discovered after the circuit design and wiring is switched in the upper wiring layer, the stage number adjusting circuit (40) can cope with it. In other words, even if the number of stages of the scan chain (11, 12) at the time of design is disturbed due to rewiring, the number of stages of a plurality of chains connected to the input of the comparison circuit (60) can be made uniform as described above. . Alternatively, in the design stage, it is not always necessary to arrange the number of stages of the plurality of scan chains (11, 12) in advance. Therefore, the degree of freedom in scan design is improved.

  In another embodiment of the present invention, the semiconductor integrated circuit (1) includes a logic circuit (10), a pattern generation circuit (30), a stage number adjustment circuit (40), and a comparison circuit (60). The logic circuit (10) has N (N is an integer of 2 or more) scan chains (11, 12). The pattern generation circuit (30) generates a random pattern (RPAT). The stage number adjusting circuit (40) has N input terminals (X1, X2) to which a random pattern (RPAT) is input, and each of the N input terminals (X1, X2) and N An additional flip-flop (53) is inserted between each input terminal (P1, P2) of the scan chain (11, 12). The comparison circuit (60) compares the patterns (COUT1, COUT2) output from the output terminals (Q1, Q2) of the N scan chains (11, 12).

  The stage number adjustment circuit (40) sets the number of stages of the additional flip-flop (53) to 0 or more and variably. That is, the stage number adjustment circuit (40) can change the stage number of the additional flip-flop (53) according to the situation. For example, in the test, the number of flip-flop stages between each of the N input terminals (X1, X2) and each of the output terminals (Q1, Q2) of the N scan chains (11, 12) may be equalized. it can. In other words, the number of stages of a plurality of chains connected to the input of the comparison circuit (60) can be made uniform. As a result, a failure on the scan chain (11, 12) can be accurately detected using a random pattern (RPAT).

  Even if a defect is discovered after the circuit design and wiring is switched in the upper wiring layer, the stage number adjusting circuit (40) can cope with it. In other words, even if the number of stages of the scan chain (11, 12) at the time of design is disturbed due to rewiring, the number of stages of a plurality of chains connected to the input of the comparison circuit (60) can be made uniform as described above. . Alternatively, in the design stage, it is not always necessary to arrange the number of stages of the plurality of scan chains (11, 12) in advance. Therefore, the degree of freedom in scan design is improved.

  According to the present invention, even after circuit design, the number of stages of a plurality of chains connected to the input of the comparison circuit can be made uniform. As a result, it is possible to accurately detect a failure on the scan chain using a random pattern.

1. 1. First embodiment 1-1. Configuration FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit 1 according to a first embodiment of the present invention. The semiconductor integrated circuit 1 includes a logic circuit 10, a master sequencer 20, a random pattern generation circuit 30, a stage number adjustment circuit 40, a comparison circuit 60, a mask circuit 70, and a JTAG circuit 80.

  The logic circuit 10 includes a large number of logic gates and flip-flops. At least a part of the flip-flop is a scan flip-flop used for a scan test. At the time of the scan test, the scan flip-flops are connected to each other to form a scan chain composed of multi-stage scan flip-flops.

  In the present embodiment, the logic circuit 10 has N (N is an integer of 2 or more) scan chains. For example, in FIG. 1, the logic circuit 10 includes two scan chains: a first scan chain 11 and a second scan chain 12. The first scan chain 11 has an input terminal P1 and an output terminal Q1. The second scan chain 12 has an input terminal P2 and an output terminal Q2. Each of the scan chains 11 and 12 includes a multi-stage scan flip-flop 13 connected in series between an input terminal and an output terminal.

  The master sequencer 20 is a test control circuit for controlling a test using a scan chain described later. Master sequencer 20 operates based on clock signal CLK. At the start of the test, the master sequencer 20 outputs a start signal ST to the random pattern generation circuit 30 and the mask circuit 70.

  The random pattern generation circuit 30 is a circuit for generating a random pattern RPAT. Examples of the random pattern RPAT include an M series and a Gold series. The random pattern generation circuit 30 operates based on the clock signal CLK, and supplies the random pattern RPAT to each of the N scan chains in response to the start signal ST. For example, in FIG. 1, the same random pattern RPAT is input in parallel to the input terminal P1 of the first scan chain 11 and the input terminal P2 of the second scan chain 12.

  The stage number adjusting circuit 40 is a circuit for adding an additional flip-flop to the scan chain as necessary. Specifically, the stage number adjustment circuit 40 includes N scan pad circuits 50 corresponding to each of the N scan chains. For example, in FIG. 1, the stage number adjustment circuit 40 includes two scan pad circuits 50-1 and 50-2.

  The scan pad circuit 50-1 has an input terminal X1 and an output terminal Y1. The input terminal X1 is connected to the output terminal Q1 of the first scan chain 11. The scan pad circuit 50-1 inserts an additional flip-flop between the output terminal Q1 and the output terminal Y1 in response to the selection signal SEL1. On the other hand, the scan pad circuit 50-2 has an input terminal X2 and an output terminal Y2. The input terminal X2 is connected to the output terminal Q2 of the second scan chain 12. The scan pad circuit 50-2 inserts an additional flip-flop between the output terminal Q2 and the output terminal Y2 in response to the selection signal SEL2.

  The scan pad circuits 50-1 and 50-2 have the same configuration. FIG. 2 shows an example of the configuration of one scan pad circuit 50, for example, the configuration of the scan pad circuit 50-1. As shown in FIG. 2, the scan pad circuit 50-1 includes a plurality of unit adjustment circuits 51A to 51K connected in series between the input terminal X1 and the output terminal Y1. Each of the unit adjustment circuits 51 </ b> A to 51 </ b> K includes a selector 52 and one or more additional flip-flops 53. The number of additional flip-flops 53 included in each of the unit adjustment circuits 51A to 51K may be different from each other. For example, in FIG. 2, the number of additional flip-flops 53 included in each of the unit adjustment circuits 51A to 51K is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024.

  In each unit adjustment circuit 51, the selector 52 receives two types of signals. Specifically, the selector 52 directly receives the input signal input to each unit adjustment circuit 51 and receives the input signal through the additional flip-flip 53. Then, the selector 52 selects one of the received two types of input signals and outputs the selected one to the unit adjustment circuit 51 (or output terminal Y1) at the next stage. The selection signal SEL1 controls the selection of the input signal. For example, the selection signal SEL1 is an 11-bit digital signal, and each bit (A to K) is input to each selector 52 of the unit adjustment circuits 51A to 51K. Each selector 52 selects the input signal received directly when the bit is “0”, and selects the input signal received through the additional flip-flop 53 when the bit is “1”.

  The total number of additional flip-flops 53 through which the input signal passes changes between the input terminal X1 and the output terminal Y1 according to the combination of these 11 bits. For example, when all the bits are “0”, the number of additional flip-flops 53 through which the input signal passes is zero. When all the bits are “1”, the number of additional flip-flops 53 through which the input signal passes is 2047. In this way, the number of additional flip-flops 53 between the input terminal X1 and the output terminal Y1 can be set to 0 or more and variably. In other words, the scan pad circuit 50-1 sets the number of stages of the additional flip-flop 53 to 0 or more and variably according to the selection signal SEL1.

  FIG. 3 shows another example of the configuration of the scan pad circuit 50-1. In FIG. 3, the scan pad circuit 50-1 includes a plurality of additional flip-flops 53 and a selector 54. The input terminal X1 is connected to one input of the selector 54 and one input of one additional flip-flop 53. The output of one additional flip-flop 53 is connected to one input of the selector 54 and the input of another additional flip-flop 53. With such a configuration, the input signal input to the scan pad circuit 50-1 is converted into a plurality of types of input signals through a different number of additional flip-flops 53 of 0 or more. The plurality of types of input signals are input to the selector 54.

  The selector 54 selects any one of the received plural types of input signals according to the selection signal SEL1. Then, the selector 54 outputs one selected input signal to the output terminal Y1. Thus, the number of stages of the additional flip-flop 53 through which the input signal passes between the input terminal X1 and the output terminal Y1 can be set to 0 or more and variably. In other words, the scan pad circuit 50-1 sets the number of stages of the additional flip-flop 53 to 0 or more and variably according to the selection signal SEL1.

  Referring to FIG. 1 again, the stage number adjusting circuit 40 described above is connected to the subsequent stage of the scan chains 11 and 12. As described above, the stage number adjusting circuit 40 has an additional flip-flop 53 inserted between the output terminals Q1 and Q2 of the scan chains 11 and 12 and the output terminals Y1 and Y2 of the stage number adjusting circuit 40, respectively. Can do. The number of stages of additional flip-flops 53 to be inserted can be set to 0 or more and variably according to the selection signals SEL1 and SEL2.

  The chain from the input terminal P1 of the first scan chain 11 to the output terminal Y1 of the scan pad circuit 50-1 is hereinafter referred to as a “first test chain”. On the other hand, the chain from the input terminal P2 of the second scan chain 12 to the output terminal Y2 of the scan pad circuit 50-2 is hereinafter referred to as a “second test chain”. It can be said that the stage number adjustment circuit 40 is a circuit for adjusting the number of stages of the first test chain and the second test chain. When the random pattern RPAT is input to the input terminal P1 of the first test chain, the first chain output signal COUT1 is output from the output terminal Y1 of the first test chain. When the random pattern RPAT is input to the input terminal P2 of the second test chain, the second chain output signal COUT2 is output from the output terminal Y2 of the second test chain.

  The comparison circuit 60 is connected to the output terminal Y1 of the first test chain and the output terminal Y2 of the second test chain, and receives the first chain output signal COUT1 and the second chain output signal COUT2. The comparison circuit 60 compares the chain output signals COUT1 and COUT2, and outputs a comparison result signal MTCH indicating the comparison result. The comparison circuit 60 is, for example, an EXOR circuit. When the comparison result is coincident, the comparison result signal MTCH is “0”, and when the comparison result is disagreement, the comparison result signal MTCH is “1”.

  Mask circuit 70 is interposed between comparison circuit 60 and master sequencer 20. The comparison result signal MTCH output from the comparison circuit 60 is sent to the master sequencer 20 through the mask circuit 70. Mask circuit 70 masks comparison result signal MTCH for a certain period in response to start signal ST. For example, the mask circuit 70 includes a counter that operates based on the clock signal CLK, and measures a certain period using the counter.

  The JTAG circuit 80 generates the selection signals SEL1 and SEL2 according to the JTAG code CODE. The JTAG code CODE is a control code for setting the number of stages of the additional flip-flop 53. The generated selection signals SEL1 and SEL2 are input to the stage number adjustment circuit 40.

  The scan chains 11 and 12, the master sequencer 20, the random pattern generation circuit 30, the stage number adjustment circuit 40, the comparison circuit 60, the mask circuit 70, and the JTAG circuit 80 described above realize the test method described below. A test circuit is configured.

1-2. Test Method Assume that the number of stages of the scan flip-flip 13 in each of the scan chains 11 and 12 is equal. In this case, when the same random pattern RPAT is input to the scan chains 11 and 12, the same pattern should be output from each of the scan chains 11 and 12 at the same timing. If the outputs of the scan chains 11 and 12 do not match each other, it means that a failure has occurred on one of the scan chains. In this way, a failure on the scan chain can be detected by inputting the same random pattern RPAT to the scan chains 11 and 12 having the same number of stages and comparing the outputs.

  In particular, a “hold error” in the scan chain can be detected. The reason is as follows. A clock signal is supplied to a flip-flop in the logic circuit 10 from a clock tree (not shown). Generally, on the scan chain, no other element is interposed between the scan flip-flops, and the path between the scan flip-flops is short. Therefore, a hold error tends to occur on the scan chain when the clock skew increases.

  Thus, the scan chain is sensitive to fluctuations in the clock skew, and a hold error is likely to occur when the clock skew becomes large. In other words, verifying whether or not a hold error has occurred in the scan chain is equivalent to examining the stability of the clock system. A clock system test can be performed by checking the occurrence of a hold error using the scan chain. Such a test is hereinafter referred to as a “timing test”.

  As described above, in order to perform a timing test using the scan chains 11 and 12 and the random pattern RPAT, the number of stages of the scan chains 11 and 12 needs to be equal. Therefore, for example, the scan chains 11 and 12 are configured so that the number of stages is equal at the stage of circuit design.

  However, defects are often found after circuit design and circuit corrections are often made. In that case, if the circuit design is re-executed from the beginning, the TAT is greatly increased. Therefore, normally, the connection between the nodes is changed in order to eliminate the problem in the upper wiring layer of the base layer in which the transistor or the like is formed. That is, wiring reconnection is performed in the upper wiring layer so as to eliminate the problem. The reconnection of the wiring is highly likely to affect the configuration of the original scan chains 11 and 12. That is, there is a high possibility that the reconnection of the wiring will disturb the number of stages of the scan chains 11 and 12. Initially, even when the scan chains 11 and 12 are designed to have the same number of stages, the number of stages does not match as a result of subsequent wiring changes. In that case, there is no point in inputting the random pattern RPAT to each of the scan chains 11 and 12 and comparing the outputs. That is, the timing test becomes impossible.

  The above-described stage number adjusting circuit 40 solves this problem. As described above, the stage number adjustment circuit 40 is configured such that the additional flip-flop 53 can be inserted even after circuit design. Moreover, the stage number adjustment circuit 40 is configured to set the number of stages of the additional flip-flop 53 to be inserted to 0 or more and variably. Therefore, by using the stage number adjustment circuit 40, the number of flip-flop stages in the first test chain and the second test chain can be made uniform. In the timing test, the first test chain and the second test chain may be used.

  Alternatively, since the stage number adjustment circuit 40 is provided, it is not necessary to prepare the respective stages of the scan chains 11 and 12 in advance in the design stage. Even if the number of stages of the scan chains 11 and 12 is different in the design stage, the number of stages of the first test chain and the second test chain can be made uniform in the timing test stage. In the timing test, the first test chain and the second test chain may be used.

  FIG. 4 is a flowchart showing an example of a test method for the semiconductor integrated circuit 1 according to the present embodiment.

Step S1:
First, a difference in the number of stages of the scan flip-flop 13 between the plurality of scan chains 11 and 12 is detected. A JTAG code CODE that eliminates the difference in the number of stages is input to the JTAG circuit 80. In response to the JTAG code CODE, the JTAG circuit 80 generates selection signals SEL1 and SEL2. The selection signals SEL1 and SEL2 are input to the stage number adjustment circuit 40. The stage number adjustment circuit 40 sets the number of stages of the additional flip-flop 53 according to the selection signals SEL1 and SEL2. Specifically, the stage number adjustment circuit 40 sets the stage number of the additional flip-flop 53 so that the number of flip-flop stages on the first test chain and the second test chain are equal.

Step S10:
Next, a burn-in test is performed. That is, an energization test of the semiconductor integrated circuit 1 is performed in a high temperature environment. During the burn-in test, the above-described “timing test” is performed (step S11). Thereby, stress can be applied to the elements in the logic circuit 10 by using the scan chains 11 and 12 simultaneously with the timing test. Use of the random pattern RPAT is preferable from the viewpoint of the activation rate of the element in the burn-in test.

  FIG. 5 is a timing chart showing an example of the operation of the semiconductor integrated circuit 1 during the timing test (step S11).

  At time t1, a reset signal RESET is input to the master sequencer 20. At time t2, master sequencer 20 outputs start signal ST. The start signal ST is input to the random pattern generation circuit 30 and the mask circuit 70.

  In response to the start signal ST, the random pattern generation circuit 30 generates a random pattern RPAT. From time t3, the random pattern RPAT is sequentially input to the input terminals P1 and P2 of the first test chain and the second test chain. The first chain output signal COUT1 and the second chain output signal COUT2 are output from the output terminals Y1 and Y2 of the first test chain and the second test chain, respectively.

  The comparison circuit 60 compares the first chain output signal COUT1 and the second chain output signal COUT2, and outputs a comparison result signal MTCH. Since the value of the scan flip-flop 13 is indefinite in the initial state, the comparison result may be inconsistent. Accordingly, the mask circuit 70 masks the comparison result signal MTCH for a certain period from the time t3 when the start signal ST is input. Specifically, the comparison result signal MTCH is masked until time t4 when a pattern corresponding to the random pattern RPAT starts to be output from the output terminals Y1 and Y2. For example, the mask circuit 70 includes a counter that operates based on the clock signal CLK, and measures a certain period using the counter. The mask circuit 70 keeps the comparison result signal MTCH inputted to the master sequencer 20 at “0” for at least the period from time t3 to time t4.

  From time t4, patterns corresponding to the random pattern RPAT start to be output as the first chain output signal COUT1 and the second chain output signal COUT2. The comparison circuit 60 compares the first chain output signal COUT1 and the second chain output signal COUT2, and outputs a comparison result signal MTCH. After time t4, the comparison result signal MTCH is not masked and is input to the master sequencer 20 as it is.

  At time t5, the first chain output signal COUT1 and the second chain output signal COUT2 do not match. Therefore, the comparison result signal MTCH is “1” indicating a mismatch. This means that a failure such as a hold error has occurred on any scan chain. When the comparison result signal MTCH becomes “1”, the master sequencer 20 outputs an error signal ERROR.

  Referring to FIG. 4 again, when the error signal ERROR is output from the master sequencer 20 (step S12; Yes), the burn-in is stopped (step S13). Then, the semiconductor integrated circuit 1 is immediately determined as a “defective product”.

Step S20:
If the error signal ERROR is not output during the timing test (step S12; No), it is considered that a failure such as a hold error has not occurred on the scan chain. Therefore, after the burn-in test is completed, an operation test of the semiconductor integrated circuit 1 is performed. By the burn-in test, the deterioration of the elements in the logic circuit 10 is accelerated. In particular, since the random pattern RPAT is used, the activation rate of the element during the burn-in test is high, and the deterioration of the element is promoted. Accordingly, screening can be performed with high accuracy in the operation test.

  When the result of the operation test is FAIL (step S21; No), the semiconductor integrated circuit 1 is determined to be “defective”. On the other hand, when the result of the operation test is PASS (step S21; Yes), the semiconductor integrated circuit 1 is determined as “good”.

1-3. Effect The semiconductor integrated circuit 1 according to the present embodiment includes a stage number adjustment circuit 40 that can change the number of stages of a plurality of test chains even after circuit design. By using this stage number adjustment circuit 40, the number of flip-flop stages on a plurality of test chains can be made equal after circuit design. Therefore, it is possible to accurately perform the timing test by inputting the random pattern RPAT to each of the plurality of test chains and comparing the respective outputs.

  Even if a defect is discovered after the circuit design and wiring is switched in the upper wiring layer, the stage number adjusting circuit 40 can cope with it. Alternatively, in the design stage, it is not always necessary to arrange the number of stages of the plurality of scan chains (11, 12) in advance. Even if the plurality of scan chains (11, 12) are freely designed, the number of stages of the plurality of test chains can be made uniform by the stage number adjusting circuit 40 thereafter. Therefore, the degree of freedom in scan design is improved.

  As described above, the timing test (step S11) is preferably performed during the burn-in test (step S10). During a high temperature test such as a burn-in test, the current tends to increase. As a result, noise that can affect the clock system is stronger than during normal operation. When the result of the timing test under such a noise environment is PASS, it can be said that the reliability of the semiconductor integrated circuit 1 is high. That is, the accuracy and reliability of the timing test are further improved by verifying the stability of the clock system in the extreme state.

  Furthermore, in the present embodiment, the random pattern RPAT is supplied to the scan chains 11 and 12 during the burn-in test (step S10). Thereby, the activation rate of the logic element connected to the scan flip-flop 13 in the logic circuit 10 increases. When a fixed pattern or a regular pattern is used, the logic value of the logic element connected to the scan flip-flop 13 is fixed or limited. Therefore, the activation rate is not sufficient. By using the random pattern RPAT, burn-in can be promoted, and contact failure, short-circuit failure, etc. can be made obvious. As a result, the screening accuracy in the operation test after the burn-in test (step S20) is improved.

2. Second Embodiment FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit 1 according to a second embodiment of the present invention. In FIG. 6, the same reference numerals are given to the same components as those in the first embodiment, and overlapping descriptions are omitted as appropriate.

  In the second embodiment, the stage number adjusting circuit 40 described above is connected to the preceding stage of the scan chains 11 and 12. That is, the output terminal Y1 of the scan pad circuit 50-1 is connected to the input terminal P1 of the first scan chain 11. The output terminal Y2 of the scan pad circuit 50-2 is connected to the input terminal P2 of the second scan chain 12. In this case, the chain from the input terminal X1 of the scan pad circuit 50-1 to the output terminal Q1 of the first scan chain 11 is a “first test chain”. A chain from the input terminal X2 of the scan pad circuit 50-2 to the output terminal Q2 of the second scan chain 12 is a “second test chain”.

  The random pattern 30 generated by the random pattern generation circuit 30 is input to each of the input terminals X1 and X2 of the stage number adjustment circuit. The comparison circuit 60 is connected to the respective output terminals Q1, Q2 of the scan chains 11, 12, and receives the chain output signals COUT1, COUT2 from the respective output terminals Q1, Q2.

  The stage number adjusting circuit 40 can insert an additional flip-flop 53 between the input terminals X1 and X2 and the input terminals P1 and P2 of the scan chains 11 and 12, respectively. The number of stages of additional flip-flops 53 to be inserted can be set to 0 or more and variably according to the selection signals SEL1 and SEL2. Accordingly, the number of flip-flop stages in the first test chain and the second test chain can be made uniform during the test. As a result, the same effect as in the first embodiment can be obtained.

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the configuration of the scan pad circuit. FIG. 3 is a circuit diagram showing another example of the configuration of the scan pad circuit. FIG. 4 is a flowchart showing an example of a method for testing a semiconductor integrated circuit according to the present invention. FIG. 5 is a timing chart showing the operation of the semiconductor integrated circuit during the test. FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 10 Logic circuit 11 1st scan chain 12 2nd scan chain 13 Scan flip-flop 20 Master sequencer 30 Random pattern generation circuit 40 Stage number adjustment circuit 50 Scan pad circuit 51 Unit adjustment circuit 52 Selector 53 Additional flip-flop 54 Selector 60 Comparison circuit 70 Mask circuit 80 JTAG circuit CLK Clock signal ST Start signal RESET Reset signal ERROR Error signal RPAT Random pattern CODE JTAG code SEL1 Selection signal SEL2 Selection signal COUT1 First chain output signal COUT2 Second chain output signal MTCH Comparison result signal

Claims (14)

A logic circuit having N (N is an integer of 2 or more) scan chains;
A pattern generation circuit for inputting a random pattern to each input terminal of the N scan chains;
A stage number adjusting circuit having N output terminals and inserting an additional flip-flop between each of the N scan chains and each of the N output terminals;
A comparison circuit that compares patterns output from each of the N output terminals, and
The stage number adjusting circuit sets the number of stages of the additional flip-flop to 0 or more and variably. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
During the test, the stage number adjustment circuit sets the number of stages of the additional flip-flops so that the number of stages of the flip-flops between the input terminals of each of the N scan chains and the N output terminals becomes equal. Set semiconductor integrated circuit. The semiconductor integrated circuit according to claim 2,
The test is performed during a burn-in test of the semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 1 to 3,
A semiconductor integrated circuit further comprising a mask circuit for masking the output of the comparison circuit for a certain period. A semiconductor integrated circuit according to any one of claims 1 to 4,
The stage number adjusting circuit includes N scan pad circuits connected between the output terminals of the N scan chains and the N output terminals, respectively.
Each of the N scan pad circuits sets the number of stages of the additional flip-flops to 0 or more and variably according to a selection signal. The semiconductor integrated circuit according to claim 5,
Each of the N scan pad circuits includes a plurality of adjustment circuits connected in series,
Each of the plurality of adjustment circuits includes:
A selector,
A predetermined number of the additional flip-flops, and
The selector directly receives an input signal input to each of the adjustment circuits as a first input signal, and receives as a second input signal through the predetermined number of additional flip-flops,
The selector selects one of the first input signal and the second input signal according to the selection signal, and outputs the selected input signal to a next stage adjustment circuit. The semiconductor integrated circuit according to claim 5,
Each of the N scan pad circuits includes:
A selector,
A predetermined number of the additional flip-flops, and
Input signals input to each of the scan pad circuits are converted into a plurality of types of input signals through different numbers of additional flip-flops among the predetermined number of additional flip-flops,
The selector selects any one of the plurality of types of input signals according to the selection signal, and outputs the selected input signal to the comparison circuit. A logic circuit having N (N is an integer of 2 or more) scan chains;
A pattern generation circuit for generating a random pattern;
A stage number adjusting circuit having N input terminals to which the random pattern is input, and inserting an additional flip-flop between each of the N input terminals and each input terminal of the N scan chains; ,
A comparison circuit for comparing patterns output from the output terminals of each of the N scan chains,
The stage number adjusting circuit sets the number of stages of the additional flip-flop to 0 or more and variably. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 8, comprising:
During the test, the stage number adjustment circuit adjusts the number of stages of the additional flip-flops so that the number of stages of flip-flops between each of the N input terminals and each output terminal of the N scan chains is equal. Set semiconductor integrated circuit. The semiconductor integrated circuit according to claim 9, wherein
The test is performed during a burn-in test of the semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 8 to 10,
A semiconductor integrated circuit further comprising a mask circuit for masking the output of the comparison circuit for a certain period. A semiconductor integrated circuit according to any one of claims 8 to 11,
The stage number adjusting circuit has N scan pad circuits connected between each of the N input terminals and each input terminal of the N scan chains,
Each of the N scan pad circuits sets the number of stages of the additional flip-flops to 0 or more and variably according to a selection signal. The semiconductor integrated circuit according to claim 12, wherein
Each of the N scan pad circuits includes a plurality of adjustment circuits connected in series,
Each of the plurality of adjustment circuits includes:
A selector,
A predetermined number of the additional flip-flops, and
The selector directly receives an input signal input to each of the adjustment circuits as a first input signal, and receives as a second input signal through the predetermined number of additional flip-flops,
The selector selects one of the first input signal and the second input signal according to the selection signal, and outputs the selected input signal to a next stage adjustment circuit. The semiconductor integrated circuit according to claim 12, wherein
Each of the N scan pad circuits includes:
A selector,
A predetermined number of the additional flip-flops, and
Input signals input to each of the scan pad circuits are converted into a plurality of types of input signals through different numbers of additional flip-flops among the predetermined number of additional flip-flops,
The selector selects any one of the plurality of types of input signals according to the selection signal, and outputs the selected input signal to a corresponding scan chain.

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