JP7257842B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device having a logic circuit, and more particularly to a liquid crystal driving semiconductor integrated circuit for driving a liquid crystal panel.

2. Description of the Related Art Semiconductor devices having logic circuits such as flip-flops and latches are used, for example, in liquid crystal drivers that drive source lines of color liquid crystal panels using TFTs (thin film transistors). A shift register consisting of serially connected flip-flops has the function of converting serial data into parallel data, so a serial/parallel conversion circuit is incorporated in the signal driver of a display device (patent Reference 1).

JP 2016-114695 A

2. Description of the Related Art Flat-panel display devices such as liquid crystal panels using signal drivers are widely installed inside automobiles. In the case where the mirrors of automobiles are composed of liquid crystal panels, etc., the malfunction of the display device affects the life of the passengers of the automobile. For this reason, components such as signal drivers are required to have high reliability.

In recent years, part of the serial/parallel conversion circuits used in signal drivers have been designed with RTL (Resister Transfer Level), so scan circuits for general scan tests have also been introduced to detect failures at the time of shipment. .

For example, as shown in FIG. 1, the scan circuit has three D-type flip-flops (hereinafter simply referred to as DFFs) 1, 2 and 3 synchronized by a clock CLK between normal mode logic circuits. It is a circuit in which a scan chain as shown in FIG. 2 is formed in the configured clock synchronization circuit. Although only one set is shown in FIG. 1, a general clock synchronization circuit has a structure in which DFFs are alternately sandwiched between logic circuits (combination circuits). The DFF is a clock-synchronized sequential circuit having a function of holding (storing) the input state at the moment the clock rises. In the scan chain of the scan circuit, an output terminal (Q terminal) is connected to each input terminal (D terminal) of DFF1, DFF2, and DFF3, and a selector SC1, a selector SC2, and a selector SC3, which are two-input multiplexers, are arranged and serially connected. is formed. Each DFF with each selector arranged at the input terminal is called a scan flip-flop.

The same scan enable signal (hereinafter referred to as SE signal) is supplied to all selectors of the scan circuit. In the scan circuit, the selectors SC1, SC2 and SC3 of the input terminals of DFF1, DFF2 and DFF3 are simultaneously switched by the SE signal to form a scan chain. That is, when the SE signal has a logical value of "1" (scan mode=H), shift register operation is performed, and the output of the previous stage DFF is input to all selectors SC1, selector SC2, and selector SC3 except for the foremost selector SC1. and all DFF1, DFF2, and DFF3 operate as shift registers. When the SE signal has a logical value of "0" (scan mode=L), the outputs of the normal mode logic circuits are input to the connected selectors, and the outputs of the normal mode logic circuits are stored in all the DFFs. Note that the scan mode is a mode in which the internal DFF group is connected to a shift register.

The normal mode is scan mode = L, and each operates to process serial/parallel conversion, but during the scan test of the shipment test, the scan mode becomes H, and the output of DFF is connected to the D input of other DFFs and shifted. It becomes like a register connection.

A scan test is a test that uses shift register connections to detect DFF failures in a circuit. First, in the scan chain state (SE signal "1") in which the DFFs are sequentially connected, the test pattern input from the SCAN-IN terminal is sequentially set in the DFFs. Subsequently, after a value is set in the DFF (scan-in step), the SE signal is set to "0", one clock is operated in the normal operation mode (capture step), and the operation result is stored in the DFF. After that, the SE signal is set to "1" again, and the values stored in the DFF are sequentially output from the SCAN-OUT terminal (scan out step). The value observed at the SCAN-OUT terminal is compared with the expected value obtained in advance (value when there is no failure) to determine the presence or absence of failure.

In this way, in the scan test of the scan circuit, the clock of the shift register, the input of the first stage and the output of the last stage can be set and observed outside the large-scale integrated circuit chip, so test patterns and expected values can be used. can detect manufacturing failures.

However, in display device components including logic circuits, failures that occur during manufacturing can be detected by shipping tests such as scan tests, but display defects occur due to failures that occur during use, such as deterioration over time and shocks. If the serial/parallel conversion circuit of the display device breaks down, the degree of influence is particularly large because all the latch circuits in the subsequent stages of the serial/parallel conversion circuit also stop operating.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of executing a scan test during a blank period between operations of a logic circuit in the semiconductor device.

A semiconductor device according to the present invention includes a logic circuit that constitutes a scan chain when a scan mode is set and has a scan input terminal to which a test signal is input; and an abnormality detection circuit having a selector for switching to the scan input terminal or the test signal generation circuit.

According to the present invention, a scan test can be implemented during a blank period between operations of logic circuits in a semiconductor device.

1 is a diagram showing a typical clock synchronization circuit; FIG. 1 is a diagram showing a scan circuit forming a general scan chain; FIG. 1 is a schematic block diagram showing a liquid crystal panel display device using a serial/parallel conversion circuit including an abnormality detection circuit according to a first embodiment; FIG. Figure 4 is a schematic block diagram of a signal driver of the display device of Figure 3; 4 is a schematic circuit diagram of an abnormality detection circuit in a part of the logic circuit of the serial/parallel conversion circuit of the first embodiment; FIG. 6 is a timing chart of the operation when there is no flip-flop failure in the circuit shown in FIG. 5; 6 is a timing chart of operation when a flip-flop failure occurs in the circuit shown in FIG. 5; 6 is a timing chart of another operation when a flip-flop failure occurs in the circuit shown in FIG. 5; FIG. 11 is a schematic circuit diagram of an abnormality detection circuit in part of the logic circuit of the serial/parallel conversion circuit of the second embodiment; FIG. 10 is a timing chart of the operation when there is no flip-flop failure in the circuit shown in FIG. 9; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings. In addition, in the embodiments, components having substantially the same functions and configurations are denoted by the same reference numerals, thereby omitting redundant description.

(First embodiment)
FIG. 3 shows the configuration of a liquid crystal panel display device 10 for automobile mirrors using a serial/parallel conversion circuit including an abnormality detection circuit according to this embodiment. FIG. 4 shows the configuration of the signal driver 1 of FIG.

As shown in FIG. 3, the display device 10 includes a signal driver 1, a scanning driver 2, a display panel 3, and a timing controller 4. FIG. Although the number of signal drivers 1 and scanning drivers 2 is eight and four, respectively, the number of signal drivers 1 and scanning drivers 2 is an example and is not limited to these. The signal driver 1 of this example is a signal driver having 960 output signal lines. Display data for 960 channels are serially transmitted from the timing controller 4 .

Pixels (not shown) are arranged in a matrix on the display panel 3 . The scanning driver 2 is connected to the pixels in the row direction via a plurality of scanning lines (not shown). The signal driver 1 is connected to the pixels in the column direction via a plurality of signal lines (not shown). Each pixel is located at each intersection of each scanning line and each signal line.

The timing controllers 4 are connected to the signal drivers 1 via data lines 7, respectively. Also, the timing controller 4 is connected to the scanning driver 2 via the control line 5 and to the signal driver 1 via the control line 6 .

The timing controller 4 inputs in parallel video data groups representing red R, green G, and blue B, and timing signals representing a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal. The timing controller 4 generates a scan driver control signal for controlling the scan driver 2 and a signal driver control signal for controlling the signal driver 1 based on the timing signal. In addition, according to the configuration of the signal driver 1, processing such as rearrangement of video data, timing adjustment, and bit number conversion is performed.

The timing controller 4 transmits a scan driver control signal to the scan driver 2 via the control line 5 . Each scan driver 2 drives a scan line group according to a scan driver control signal.

The timing controller 4 also transmits a signal driver control signal to the signal driver 1 via a control line 6, and transmits display data obtained by serializing a video data group to the signal driver via a data line 7, respectively. Send to 1. Each of the signal drivers 1 drives a signal line group according to a signal driver control signal and display data.

As shown in FIG. 4, the signal driver 1 includes an internal bus 13, a first latch circuit 14, a second latch circuit 15, a digital/analog (D/A) converter 16, and an output amplifier circuit 17. is equipped with

A serial/parallel conversion circuit 12 receives display data from the timing controller 4 . The serial/parallel conversion circuit 12 performs serial/parallel conversion on the display data and outputs the video data group to the first latch circuit 14 via the internal bus 13 .

The signal driver 1 incorporates a shift register, and shifts a start signal indicating that it is the first display data in one horizontal period, and uses it as a clock for fetching data into the first latch circuit 14 . When the input of the final display data for one horizontal period is finished, the load signal is raised after a certain time. The load signal falls before the rise of the start signal for the next horizontal period. This load signal is used as a clock for the second latch circuit 15 .

The first latch circuit 14 stores the video data group and outputs the video data group to the second latch circuit 15 according to the signal driver control signal. The second latch circuit 15 takes in data at the rising edge of the clock, D/A converts the data, and the output amplifier circuit 17 drives the display panel.

That is, the second latch circuit 15 stores the video data group from the first latch circuit 14 in one horizontal period, and outputs the video data group to the D/A converter 16 according to the signal driver control signal. . The D/A converter 16 performs digital/analog conversion on the video data group from the second latch circuit 15 and outputs an output voltage group corresponding to the video data group. The output amplifier circuit 17 outputs the output voltage group to the signal line group of the display panel 3 (FIG. 1).

The first latch circuit 14, the second latch circuit 15, the D/A converter 16, and the output amplifier circuit 17 corresponding to one output signal line are called bit cells. There are as many bit cells as the number of

FIG. 5 is a schematic circuit diagram of an abnormality detection circuit in part of the logic circuit of the serial/parallel conversion circuit of this embodiment.

The serial/parallel conversion circuit of this embodiment has a logic circuit such as the serial/parallel conversion circuit shown in FIG. It has a terminal SCAN-IN and a scan output terminal SCAN-OUT. By using this scan mode during a blank period or the like during logic circuit operation, it is determined whether or not a failure has occurred in the DFF inside the circuit.

As shown in FIG. 5, in the scan chain, an output terminal (Q terminal) is connected to each input terminal (D terminal) of DFF1, DFF2, and DFF3, and selectors SC1, SC2, and SC3, which are two-input multiplexers, are arranged. are serially connected to each other. After replacing each DFF with one scan cell circuit in which each corresponding selector is combined, the scan chain may be connected.

In order to initiate failure detection from the logic circuit in normal mode, a blank period detector 20 is provided in the logic circuit, which detects a test start signal (hereafter, start signal) is generated and output to the test start signal line TSS. Although the timing differs depending on the specifications, for example, it is performed during a blank period during which the driver does not need to operate for abnormality detection.

The abnormality detection circuit 21 of this embodiment has a test signal generation circuit 22 that generates a test signal. The test signal generation circuit 22 has a pair of flip-flops DFF4 and DFF5 connected in series to the scan chain while being synchronized with the above scan flip-flops. A pair of flip-flops DFF4 and DFF5 are connected to a test start signal line TSS and generate an inverted 2-bit test pattern as a test signal according to the test start signal. The DFF4 and DFF5 are provided with a set terminal S and a reset terminal R, and the test start signal line TSS is connected to the set terminal S and the reset terminal R, which are different from each other. Therefore, in response to the test start signal, the abnormality detection circuit 21 changes the test signal between the set state in which each Q terminal stores "H" and the reset state in which "L" is stored. A 2-bit test pattern can be generated.

The abnormality detection circuit 21 has a selector (hereinafter referred to as a mode selector) 24 for switching to the scan input terminal SCAN-IN or the test signal generation circuit 22 . The anomaly detection circuit 21 can input a 2-bit test pattern added to the scan chain including DFF4 and DFF5 via this according to the state of the mode selector 24 . The 2-bit test pattern for expected value determination makes it possible to construct a scan chain to which additional DFF4 and DFF5 for 2 bits (H and L are 1 bit each) are added.

The abnormality detection circuit 21 includes a scan mode setting unit 23, which causes a mode selector 24 to switch from the scan input terminal SCAN-IN to the test signal generation circuit 22 in response to the test start signal from the blank period detection unit 20 in the logic circuit. to input the test signal to the scan chain.

The abnormality detection circuit 21 has a counter 26 which is a test period signal generation circuit connected to the test start signal line TSS. The counter 26 generates a test period signal (hereinafter also referred to as a period signal) having the same number of bits as the total number of flip-flops of the scan chain and the pair of flip-flops DFF4 and DFF5 while synchronizing with the above scan flip-flops. It feeds the scan chain according to the signal. A counter 26 counts the sensing periods using the test start signal. The value of this counter 26 is the same as the number of scan flip-flops connected to the shift register. In the example shown in FIG. 5, the counter 26 has a value of 5 because there are five stages of shift register connections. The counter 26 also generates a test end signal (hereinafter also referred to as an end signal) indicating the end of the test period signal.

The abnormality detection circuit 21 has a failure determination section 28 for determining failure. The failure determination unit 28 determines a circuit abnormality by comparing outputs from the pair of flip-flops DFF4 and DFF5 in response to the test end signal. Since the initial value of DFF4 is L and the initial value of DFF5 is H, the shift register is circulated to determine that the value of DFF4 is L and the value of DFF5 is H as expected values. The timing for determination is made by the counter 26 described above. If one of the DFFs fails in the mode of fixing to L or H, both the values of DFF4 and DFF5 become L or H, so it is determined as a failure. The fault determination unit 28 has communication means (referred to as an SDO terminal) with the system as an output terminal of the driver. The failure determination unit 28 outputs H in normal and L in abnormal to the SDO terminal, and informs the system outside the driver via the SDO terminal.

(Description of operation)
FIG. 6 is a timing chart of the operation when there is no flip-flop failure in the circuit shown in FIG. The values of DFF4 and DFF5 are L and H, respectively, when the start signal rises, and are L and H, respectively, when the end signal rises. The SDO terminal output remains H and returns normal.

FIG. 7 is a timing chart of the operation when a flip-flop failure in which DFF2 turns to L occurs in the circuit shown in FIG. FIG. 8 is a timing chart when a flip-flop failure in which DFF3 turns to H occurs in the circuit shown in FIG. In FIGS. 7 and 8, the SDO terminal output becomes L and an abnormality is returned.

According to this embodiment, it is possible not only to detect failures that occur during manufacturing, but also to detect failures that occur during use of the signal driver by introducing an additional abnormality detection circuit 21 or the like. .

(Second embodiment)
FIG. 9 is a schematic circuit diagram of the second embodiment. In the semiconductor device having the abnormality detection circuit of this embodiment, in addition to the scan circuit and abnormality detection circuit 21 of the first embodiment as shown in FIG. , DFF6, DFF7 and DFF8 connected in series to the failure determination section 28 and connected to the divided wiring DVL in synchronization with the scan flip-flop of DFF1, and a comparison wiring CML for comparing the outputs of DFF7 and DFF8. have Other configurations are the same as those of the first embodiment.

In the first embodiment, one scan chain with shift register connection is explained, but the detection period is extended according to the number of DFFs, which may become an obstacle when it is desired to shorten the blank period. In that case, the detection period can be shortened by dividing the shift register connection. In the case of division, by arranging the number of scan flip-flops forming shift register connections in the divided scan chains, the counter 26 for failure detection and the like can be shared.

That is, in the scan circuit and abnormality detection circuit 21, when the scan chain before division is composed of m (m is an integer, m≧2) scan flip-flops, n (n is an integer, m>n, n≧1) The shift register portion of the scan flip-flops is divided into a first scan chain SCH1 consisting of n scan flip-flops and a second scan chain SCH2 consisting of mn second scan flip-flops. be able to. Further, the abnormality detection circuit 21 is provided with n+2 additional flip-flops connected in series from the first scan chain SCH1 of the n scan flip-flops to the failure determination unit 28 .

The configuration shown in FIG. 9 is a scan circuit in which m=3 and n=1 and the shift register connection is divided into two, a first scan chain SCH1 and a second scan chain SCH2.

The added DFF6 is for aligning the number of DFFs forming the shift register connection, and the DFF7 and DFF8 are for detecting failures in the added scan chains.

(Description of operation)
FIG. 10 is a timing chart of the operation when there is no flip-flop failure in the case shown in FIG. The values of DFF4 and DFF5 and DFF7 and DFF8 are L and H respectively when the start signal rises, and are L and H respectively when the end signal rises. The SDO terminal output remains H and returns normal.

In the timing chart of FIG. 10, compared with the timing chart of FIG. 6, it can be seen that the count value is reduced from 5 to 4, thereby shortening the failure detection period. Since the detection period depends on the number of DFFs forming one shift register, the greater the total number of DFFs, the greater the effect of division.

In any of the embodiments, the function of the signal driver has been described, but any semiconductor device (IC) to which a scanning circuit for shipping is applied and which is used in such a way that there is an idle period can be applied.

1 signal driver 10 display device 20 blank period detector 21 abnormality detection circuit 22 test signal generation circuit 24 mode selector 26 counter 28 failure determination unit

Claims (3)

a logic circuit that configures a scan chain when a scan mode is set and has a scan input terminal to which a test signal is input;
an abnormality detection circuit having a test signal generation circuit that generates the test signal in a blank period between operations of the logic circuit, and a selector that switches to the scan input terminal or the test signal generation circuit ;
The logic circuit generates a test start signal at the start of a blank period during its operation, and switches the selector from the scan input terminal to the test signal generation circuit according to the test start signal to perform the test. inputting a signal into the scan chain;
wherein the test signal generation circuit generates an inverted 2-bit test pattern as the test signal in accordance with the test start signal, and includes a pair of flip-flops connected in series with the scan chain. Device. The abnormality detection circuit is
A test period signal generation that supplies a test period signal having the same number of bits as the total number of flip-flops of the scan chain and the pair of flip-flops to the scan chain and generates a test end signal indicating the end of the test period signal. a circuit;
a failure determination unit that compares outputs from the pair of flip-flops in response to the test end signal to determine a circuit abnormality;
2. The semiconductor device according to claim 1 , further comprising: The abnormality detection circuit is
The scan chain is composed of m (integer, m≧2) scan flip-flops, and the shift register portions of n (integer, m>n, n≧1) scan flip-flops are divided into n When divided into a first scan chain consisting of scan flip-flops and a second scan chain consisting of mn second scan flip-flops, from the first scan chain of the n scan flip-flops to the failure determination unit 3. A semiconductor device according to claim 2 , further comprising n+2 additional flip-flops connected in series up to n+2.

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