JP4234357B2 - Failure analysis method for semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a failure analysis method for a semiconductor integrated circuit capable of reducing a test pattern for failure analysis of a semiconductor integrated circuit and improving failure analysis efficiency.
[0002]
[Prior art]
A scan method is often used as a test method for a logic portion in which a desired logic circuit is built in a semiconductor integrated circuit.
[0003]
FIG. 3 is a circuit diagram inside a conventional semiconductor integrated circuit equipped with a scan circuit. In the figure, “□” symbols to which symbols SEN, CLK, etc. are attached are terminals for inputting or outputting signals to the outside of the semiconductor integrated circuit.
[0004]
In this scan method, the logic part of the semiconductor integrated circuit is divided into blocks for each function to form a circuit, and a scan flip-flop is provided for each signal between blocks. Also, the internal signal of the semiconductor integrated circuit is monitored from the outside (shift mode) by shifting the data taken into the scan chain constituted by the scan flip-flop.
[0005]
For example, in FIG. 3, there are three blocks of logic circuit portions 10-12. Between these blocks, a flip-flop 22 is provided for each signal as well as a selector 21 as a scan circuit. The selector 21 receives a scan enable signal SEN for controlling the switching selection.
[0006]
When the semiconductor integrated circuit is normally operated, the scan enable signal SEN is set to “0 (L state)” (normal operation mode) and the clock signal CLK is beaten.
[0007]
On the other hand, when the internal state of the semiconductor integrated circuit is monitored by the scan method, the scan enable signal SEN is set to “1 (H state)” and the clock flip-flop is turned on every time the clock signal CLK is hit. The held data taken from the internal circuit can be shifted, and the data can be observed outside the semiconductor integrated circuit from the output terminals SOUT1 and SOUT2 for each shift. In the shifting process, the data input from the outside of the semiconductor integrated circuit is shifted between the scan flip-flops by the input terminals SIN1 and SIN2, and the data held in the scan flip-flops is thus set from the outside. It can be done.
[0008]
Note that a pattern input from the outside of the semiconductor integrated circuit when testing the operation of each block inside the semiconductor integrated circuit by the scan method is referred to as a scan pattern. A test pattern other than the scan pattern is called a function pattern.
[0009]
When a failure analysis is performed to find the failure location after a failure is found due to a mismatch in expected values due to a test, when the operating state of the semiconductor integrated circuit is observed only with a normal output signal, there is an abnormality in the output signal. However, it is difficult to estimate which part of the interior is caused by the malfunction. For example, even if there is an abnormality in the output signal OUT1 in FIG. 3, it is usually impossible to estimate which part of the logic circuit parts 10 to 12 has a malfunction.
[0010]
On the other hand, if the scan path method is employed for failure analysis, the signal input / output states of the logic circuit portions 10 to 12 can be observed from the outside of the semiconductor integrated circuit. It is possible to estimate which part is malfunctioning.
[0011]
For example, in the process of inputting a certain function pattern to the semiconductor integrated circuit of FIG. 3 from the outside, an operation failure (failure) is found in the semiconductor integrated circuit, and failure analysis is performed in order to find the internal location of the operation failure. Assumed to be performed. 2A to 2E are time charts showing a conventional failure analysis operation. The function pattern is “function pattern a” shown at the top in FIG. 2, and this is assumed to have a time length of 7000 nS, for example. The “function pattern a” is not a pattern dedicated to the scan path method, but is also used for other purposes. Also, in the process of inputting the “function pattern a”, it is estimated that a malfunction has occurred due to a failure at the time when 2000 nS has elapsed from 2010 nS (at the start), 2010 nS has elapsed, and 2020 nS has elapsed. And
[0012]
In such a failure analysis, the internal state of the semiconductor integrated circuit is observed from the outside at each of these 2000 nS elapsed time, 2010 nS elapsed time, and 2020 nS elapsed time. Further, in order to observe at each of these times, “function pattern b” to “function pattern d” as shown in FIG. 2 are used.
[0013]
First, the hatched portion of “function pattern b” is the same as the pattern from 0 nS (at the start) to after 2000 nS has elapsed in “function pattern a”. Next, the hatched portion of “function pattern c” is the same as the pattern from 0 nS (at the start) to after 2010 nS has elapsed in “function pattern a”. The shaded portion of “function pattern d” is the same as the pattern from 0 nS (at the start) to after 2020 nS has elapsed in “function pattern a”. That is, in any hatched portion, the same pattern as the pattern from 0 nS (at the start) to 2000 nS after the “function pattern a” exists at the beginning of the hatched portion. The parts denoted by reference numeral P1 are the same as each other, and the internal state of the semiconductor integrated circuit held in the scan chain is read out and observed while being shifted, or held in the scan chain. This is an operation for setting data from the outside.
[0014]
For example, when the scan path method is adopted for failure analysis in FIG. 3 and the logic circuit portion 10 outputs and the signal held in the flip-flop 22 of the code F04 is abnormal, the logic circuit portion 10 in FIG. It is presumed that there was an abnormality in the range indicated by the alternate long and short dash line. Also, when there is an abnormality in the signal output from the logic circuit portion 10 and held in the flip-flop 22 of the symbol F05, there is an abnormality in the range indicated by the two-dot chain line in the logic circuit portion 10 in the figure. It is estimated to be. Further, when there is an abnormality in the signal held in the flip-flop 22 with the reference sign F04 and the signal held in the flip-flop 22 with the sign F05, which is output from the logic circuit portion 10, the area in the shaded area rising to the right in the figure. It is presumed that there was an abnormality in the circuit.
[0015]
[Problems to be solved by the invention]
However, there is a problem even when the scan path method is used for failure analysis. That is, in the failure analysis, the scan enable signal SEN is set to “1” and the clock signal CLK is sequentially input from the outside of the semiconductor integrated circuit at a plurality of points in time at which it is estimated that a malfunction has occurred due to the failure. The operating states of the circuit portions 10 to 12 are observed from the outside of the semiconductor integrated circuit. When observing each of these time points, it is necessary to reproduce each time from the initial state of the semiconductor integrated circuit for each observation, and the reproduced operation state is shifted in the scan chain as output signals SOUT1 and SOUT2. Observe from outside. For example, in FIG. 2, the internal state of the semiconductor integrated circuit is initialized each time in order to observe the time after 2000 nS from 0 nS (starting time), the time after 2010 nS, and the time after 2020 nS. It was necessary to perform each of the function pattern b ”to“ function pattern d ”.
[0016]
This is because, in FIG. 2, when the internal state of the semiconductor integrated circuit is shifted and observed at the portion P1, the logical state held in the scan chain after observation is different from that immediately before observation. For this reason, the operation immediately before the observation cannot be continued after the observation, and it is necessary to reproduce the operation state of the semiconductor integrated circuit every time from the initial state every observation at a desired time point.
[0017]
In the scan path method, when the scan chain is shifted and the internal state is observed, the contents of the scan chain immediately before the shift are grasped in advance by a simulation or the like and stored in a tester memory or the like. Then, after the internal state is observed, based on the storage, for example, the input signal SIN1 or the input signal SIN2 from the outside of the semiconductor integrated circuit of FIG. It is also possible to do. However, if this is done, there are problems such as the need for simulation and the need for tester memory. Therefore, there are various timings for observing the internal state, such as different locations of defective semiconductor integrated circuits for each chip, and there is a problem that such a simulation is performed every time and the capacity of the tester memory is increased. .
[0018]
Further, as described above, when each of “function pattern b” to “function pattern d” is sequentially performed, the “pattern total time” indicated by symbol e in FIG. As described above, there is a problem that the failure analysis conventionally requires a long time.
[0019]
The present invention has been made to solve the above-mentioned conventional problems, and when it is desired to observe the internal state, the semiconductor integrated circuit is switched from the normal operation mode to the shift mode, and the semiconductor integrated circuit is externally connected to the semiconductor integrated circuit. After observing the internal state of the semiconductor integrated circuit, it is possible to switch from the shift mode to the normal operation mode so that the internal operation that has been stopped can be resumed continuously, thereby reducing the failure analysis pattern of the semiconductor integrated circuit and the failure analysis efficiency. An object of the present invention is to provide a failure analysis method for a semiconductor integrated circuit that can be improved.
[0020]
Here, the internal state of the semiconductor integrated circuit is not constant because it fluctuates when the data held by the scan flip-flop changes due to the shift, but returning to the original state after the observation of the internal state is called operation stop.
[0021]
[Means for Solving the Problems]
According to the present invention, a function pattern having a predetermined time length is input to a semiconductor integrated circuit subject to failure analysis, which includes a plurality of logic circuit portions in its internal circuit , and at least first and second of the function patterns are input. In the failure analysis method of a semiconductor integrated circuit for observing the internal state of the semiconductor integrated circuit at a point of time , a plurality of scan chains provided by connecting a plurality of scan flip-flops provided between the logic circuit portions comprising, if the number of flip-flops are different between these scan chain, by adding a flip-flop to flip-flop is small scan chain, to as number flip-flop is identical between scan chain Rutotomoni, the signal inputs of these scan chains, Se shift feedback It comprise Kuta signal input from the outside of the semiconductor integrated circuit, or so as to feedback within each scan chain, and configured so that can enter the output signal of the scan chain, first, the semiconductor integrated In the normal operation mode in which the circuit is normally operated , the logic circuit at the most upstream side of the signal flow in the plurality of logic circuit portions from the input terminal provided for inputting a signal from the outside of the semiconductor integrated circuit in part, to enter up to the first point of the Fankushi ® emission pattern, maintains an internal state of the semiconductor integrated circuit to the scan flip-flop, then the normal operating mode, captured into the scan chain I cut data into the shift mode for monitoring the internal signal of the semiconductor integrated circuit from outside by shifting the The shift feedback selector selects the output signal of the scan chain, reads the data of the scan flip-flop outside the semiconductor integrated circuit while sequentially inputting the clock signal, and the scan chain By inputting the clock signals as many as the number of flip-flops, the internal state held in the scan flip-flops is restored to the state before the shift, and then the shift mode is switched to the normal operation mode, and the function is again performed. This time , the pattern is input from the first time point to the second time point, the internal state of the semiconductor integrated circuit is held in the scan flip-flop, and the normal operation mode is switched to the shift mode. The scan feedback selector This problem is solved by selecting the output signal of the chain and reading out the data of the scan flip-flop to the outside of the semiconductor integrated circuit while sequentially inputting the clock signal.
[0024]
The operation of the present invention will be briefly described below.
[0025]
In the present invention, when the output signal of the scan chain is selected by the selector for shift feedback, the scan chain is configured as a ring counter. That is, when the clock signal is sequentially input in the selected state, the output signal of the scan chain is input as the input signal of the scan chain and fed back. Accordingly, the data goes round while sequentially shifting in the scan chain, and the data held in each scan flip-flop returns to the initial state before the round after the round.
[0026]
Therefore, according to the present invention, when the internal operation of the semiconductor integrated circuit is stopped and then the data is cycled while sequentially shifting in the scan chain as described above, all these data are stored in the semiconductor integrated circuit. It can be observed from the outside. In addition, since the retained data is restored to the initial state after the first round, the internal operation of the stop can be continued thereafter.
[0027]
As described above, according to the present invention, when it is desired to observe the internal state, the internal operation of the semiconductor integrated circuit failure analysis observation target is stopped, and the internal state of the semiconductor integrated circuit is externally determined from the semiconductor integrated circuit. After the observation, the internal operation that has been stopped can be resumed, and the failure analysis pattern of the semiconductor integrated circuit can be reduced and the failure analysis efficiency can be improved.
[0028]
In the present invention, the internal state of the semiconductor integrated circuit observed while sequentially shifting data in the scan chain may be the state after being operated by the scan pattern, or after being operated by the function pattern. The present invention does not specifically limit how the internal state is obtained.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0030]
FIG. 1 is a circuit diagram of a logic unit built in a semiconductor integrated circuit according to an embodiment to which the present invention is applied.
[0031]
In the configuration of the present embodiment, the present invention is applied, and the shift feedback selector 25 of the present invention is provided at the signal input of the scan chain used for the scan path type failure analysis. The shift feedback selector 25 is a selector that selects one of the two signals, and selects a signal input from the outside of the semiconductor integrated circuit or an output signal of the scan chain.
[0032]
Here, when the internal state is observed by shifting the scan chain, the external selection signal SEL input from the semiconductor integrated circuit is set to “1” (H state). In this case, the scan chain is configured as a ring counter, and when the clock signal CLK is sequentially input, the output signal of the scan chain is input as an input signal of the scan chain and fed back.
[0033]
In the present embodiment, the plurality of scan chains constituted by the flip-flops 22 originally have different numbers of flip-flops among the scan chains. For this reason, a flip-flop 27 is added to a scan chain having a small number of flip-flops 22 so that the number of flip-flops is the same between the scan chains.
[0034]
In FIG. 1, two flip-flops 27 denoted by reference numerals F11 and F12 are provided with respect to FIG. 3 so that the number of flip-flops is the same. By providing these flip-flops 27, the number of flip-flops 22 that hold signals passed between the logic circuit portions 10 and 11 and the signals passed between the logic circuit portions 11 and 12 are held. The number of flip-flops 22 and 27 (4 + 2 = 6) is equal.
[0035]
As described above, when the internal state is observed by shifting the scan chain, the output signal of any scan chain is set to “1” (H state) by setting the external selection signal SEL to “1” (H state). The number of flip-flops fed back as the input signals and included in these scan chains is the same, and the number of shift stages is the same (six stages). Therefore, when the external selection signal SEL is set to “1” (H state) and the scan chain is shifted six times while sequentially inputting the clock signal CLK, all flip-flops 22 and 27 can be observed from the output terminals SOUT1 and SOUT2.
[0036]
Also, since the output signal of the scan chain is fed back as its input signal when shifting, the state held in the scan chain after these internal states are observed by shifting the number of times equal to the number of shift stages. In this embodiment, after the sixth shift, the state held in the scan chain returns to the state before the six shifts again. Therefore, after the six shifts, the operation of the semiconductor integrated circuit according to the present embodiment, which was interrupted at the time of the six shifts, can be resumed including the respective operation states of the logic circuit portions 10 to 12. is there.
[0037]
For example, in the "Function pattern a" in FIG. 2, 0 ns (start time) from after the lapse 2000nS time (first time), the time (second time point) after the elapse 2010NS, time after lapse 2020NS (No. Let us consider a case where the data representing the internal state of the semiconductor integrated circuit held in the scan chain is shifted to the outside and observed at each time point 3) . In this case, in the present embodiment, the test is performed using a pattern shown as “embodiment pattern (hereinafter referred to as function pattern f)” shown in FIG.
[0038]
First, in the internal state observation at the time of 2000 nS, the same function pattern from 0 nS to 2000 nS of “function pattern a” from time ta to tb in “function pattern f” is input. After that, from the time tb to tc, as indicated by the symbol P1, the internal state of the semiconductor integrated circuit held in the scan chain is shifted, read out and observed. After the shift, the state held in the scan chain is restored before the shift.
[0039]
Thus, the internal state observation at the time of 2010 nS can be continued following the above observation without the need to initialize the semiconductor integrated circuit or the scan chain. In the “function pattern f”, the same function pattern as the pattern from 2000 nS to 2010 nS of “function pattern a” from time tc to 10 nS is input. After that, as indicated by the symbol P1, the internal state of the semiconductor integrated circuit held in the scan chain is shifted, read out and observed. After the shift observation, the state held in the scan chain is restored before the shift.
[0040]
Following the observation, the same function pattern as the pattern from 2010 nS to 2020 nS of “function pattern a” is input as the pattern of “function pattern f” from time td to 10 nS. After that, as indicated by the symbol P1, the internal state of the semiconductor integrated circuit held in the scan chain is shifted, read out and observed.
[0041]
In this embodiment, as described above, when the internal state is desired to be observed, the operation of the failure analysis observation target is stopped, the internal state is observed from outside the semiconductor integrated circuit, and the operation after the observation is stopped is continued. It can be resumed. As a result, the internal state observation at three time points, 2000 nS time point, 2010 nS time point, and 2020 nS time point, starts at time ta, and each time “tb, tc, This is possible at td, and it is possible to reduce the test pattern for failure analysis of the semiconductor integrated circuit and improve the failure analysis efficiency.
[0042]
Further, as apparent from comparison between the “function pattern f” and the “total pattern time” indicated by the conventional symbol e described above, according to the present embodiment, the failure analysis time can be shortened. It becomes possible.
[0043]
As described above, in the present embodiment, the present invention can be effectively applied.
[0044]
【The invention's effect】
According to the present invention, it is possible to reduce test patterns for failure analysis of a semiconductor integrated circuit and improve failure analysis efficiency.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a logic unit built in a semiconductor integrated circuit according to an embodiment to which the present invention is applied. FIG. 2 is a time chart showing failure analysis of the embodiment and operation of a conventional example compared with the failure analysis. FIG. 3 is a circuit diagram of a logic unit in a semiconductor integrated circuit that performs failure analysis by a conventional scan path method.
DESCRIPTION OF SYMBOLS 10-12 ... Logic circuit part 21 ... Selector 22 ... Flip-flop 25 ... Shift / feedback selector SEN ... Scan enable signal CLK ... Clock signal SIN1, SIN2 ... Input signal SOUT1, SOUT2 from outside semiconductor integrated circuit ... Semiconductor integrated circuit Output signal SEL to outside ... External selection signal (for operation of the present invention)

Claims (1)

A function pattern having a predetermined time length is input to a semiconductor integrated circuit subject to failure analysis, which includes a plurality of logic circuit parts in its internal circuit , and the function pattern at least at the first and second time points is input. In a semiconductor integrated circuit failure analysis method for observing the internal state of a semiconductor integrated circuit,
If there are multiple scan chains provided by connecting multiple scan flip-flops provided between the logic circuit parts, and the number of flip-flops differs between these scan chains, scans with fewer flip-flops chain by adding flip flops, as the number of flip-flops are the same between the scan chain to Rutotomoni,
The signal input of these scan chains is equipped with a selector for shift feedback, and the signal input from the outside of the semiconductor integrated circuit, or the output of the scan chain so as to be fed back in each scan chain configured to so that can input a signal,
First, in a normal operation mode in which the semiconductor integrated circuit is normally operated , the most upstream of the signal flow among the plurality of logic circuit portions from an input terminal provided for inputting a signal from the outside of the semiconductor integrated circuit. the logic circuit portion of the side, enter up to the first point of the Fankushi ® emission pattern, maintains an internal state of the semiconductor integrated circuit to the scan flip-flop,
Next, from the normal operation mode , the data captured in the scan chain is shifted to switch to the shift mode for externally monitoring the internal signal of the semiconductor integrated circuit , and the shift feedback selector is switched to the shift chain selector. By selecting an output signal and reading the data of the scan flip-flop outside the semiconductor integrated circuit while sequentially inputting the clock signal, and inputting the clock signal by the number of flip-flops of the scan chain The internal state held in the scan flip-flop is restored to the state before the shift,
Then, switching from the shift mode to the normal operation mode again, this time of the function pattern inputs up to the second time point from the first point in time, the internal state of the semiconductor integrated circuit to the scan flip-flops Hold and
Further, switching from the normal operation mode to the shift mode, causing the shift feedback selector to select the output signal of the scan chain, and sequentially inputting the clock signal, the scan flip-flop is connected to the outside of the semiconductor integrated circuit. A failure analysis method for a semiconductor integrated circuit, wherein data is read.

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