JPH0696153A - Logic circuit verification device - Google Patents

Abstract

PURPOSE:To easily compare the simulated results before and after test pattern correction with each other at the time of logic circuit simulation by an operator. CONSTITUTION:A resimulated result/last simulated result change data extracting means 15 extracts changed data by comparing the uncorrected simulated result obtd. by simulating the data of an uncorrected test pattern held in a test pattern data holding means 11 with the corrected simulated result obtd. by simulating the data of a corrected test pattern based on the correcting position of a test pattern held in a test pattern correcting position holding means 12. Basing on the extracted change data, a waveform change and a delay change with respect to the waveform of the corrected simulated result are displayed at a resimulated result waveform/change data display means 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit verification device for verifying a logic circuit such as an ASIC or a printed circuit board designed using a CAD system.

[0002]

2. Description of the Related Art Conventionally, an ASIC using a logic circuit verification device
For logic verification of logic circuits such as, a logic simulator is used to perform simulation on the logic circuit with a test pattern, the simulation results are displayed as waveforms, and the operator confirms whether the waveforms are as expected in advance. The method of visual confirmation is used, and it is still an effective method.

Further, recently, due to a limitation of a tester in designing a logic circuit such as an ASIC, a logic circuit verification device automatically checks whether or not a simulation result is the same as a value expected by an operator. An expected value comparison is often performed in which an expected value for each cycle is input to a test pattern for simulation by using a cyclic idea and the expected value and the simulation result are compared.

[0004]

However, in the expected value compare as described above, since it is not possible to directly compare the simulation results before and after the modification of the test pattern, there is a delay between the simulation result before the modification and the simulation result after the modification. There is a problem that it is difficult to capture the difference and verify the difference in the waveform. Also,
Even the conventional error detection control method of the logic circuit verification device does not consider the simulation result before the test pattern correction.

Therefore, there is a problem that the operator cannot check the following items during the simulation. (1) Since one cycle is checked at the strobe point position with respect to the cycle width, waveform differences such as short pulses cannot be found.

(2) It is impossible to grasp how much the delay has changed in the re-simulation. (3) Since it is a comparison with the expected value, the error that occurred in the simulation before the test pattern modification will occur again in the simulation after the modification.

The present invention has been made in view of the above points, and it is an object of the present invention to allow an operator to easily compare the simulation results before and after the test pattern correction in the logic circuit simulation.

[0008]

In order to achieve the above object, a logic circuit verification device according to the present invention comprises a test pattern input / correction means for inputting or modifying a test pattern for simulating a logic circuit such as an ASIC. ,
Test pattern data holding means for holding the data of the test pattern input or corrected by the means, and test pattern correction position holding means for holding the correction position of the test pattern by the test pattern input / correction means,
The test pattern data holding means is provided with a simulation executing means for executing the simulation of the logic circuit by the data of the test pattern and a simulation result holding means for holding the simulation result by the means.

Further, the pre-correction simulation result obtained by simulating the data of the pre-correction test pattern held in the test pattern data holding means by the simulation executing means, and the correction position of the test pattern held in the test pattern correction position holding means A pre-correction simulation result change data extracting means for extracting the changed data by comparing the post-correction test pattern data obtained by correcting the pre-correction test pattern data with the post-correction simulation result simulated by the simulation executing means; A corrected simulator for displaying the waveform change and the delay change based on the change data extracted by the simulation result change data extracting means before and after the correction with respect to the waveform of the corrected simulation result. In which the provided Deployment result change status display means.

Further, it is preferable to provide change data extraction test pattern specifying means for specifying a test pattern for extracting change data by the before / after correction simulation result change data extracting means.

Further, it is preferable to provide a waveform change / delay change extraction designating means for designating to extract either one or both of the waveform change and the delay change by the before / after simulation result change data extracting means.

Furthermore, the same timing part group designating and modifying means for designating and modifying the same timing portion of the pre-correction test pattern and the same timing when the pre-correction simulation result and the post-correction simulation result are compared. It is preferable to provide an in-group same-timing partial change status display means for distinguishably displaying whether or not the waveform change and delay change of each portion at the same timing corrected and designated by the partial group designation / correction means are the same.

Further, change data totaling means for totaling the number of occurrences of change data extracted by the simulation result change data extracting means before and after modification at the same timing, and total result displaying means for displaying the number of occurrences totaled by the means. Should be provided.

[0014]

The logic circuit verifying device according to the present invention is an ASIC.
When a test pattern for simulating a logic circuit such as is input or modified, the data of the input or modified test pattern and the correction position of the test pattern are held, and the data of the held test pattern holds the logic circuit. The simulation is executed and the simulation result is retained.

Then, the pre-correction simulation pattern obtained by simulating the held pre-correction test pattern data and the post-correction test pattern in which the pre-correction test pattern data is corrected based on the correction position of the held test pattern. The changed data is extracted by comparing the modified data obtained by simulating the above data with the modified simulation result, and the waveform change and the delay change based on the extracted change data are displayed for the waveform of the modified simulation result.

Therefore, it is possible to display the waveform change and delay change between the pre-correction simulation result by the pre-correction test pattern and the post-correction simulation result by the post-correction test pattern.

If a test pattern for extracting change data is designated by comparing the pre-correction simulation result with the post-correction simulation result, the simulation results of the pre-correction test pattern and the pre-correction test pattern are compared only for the specified test pattern. Waveform changes and delay changes due to can be displayed.

Further, by comparing the pre-correction simulation result with the post-correction simulation result and designating to extract either one or both of the waveform change and the delay change, the simulation result of the pre-correction test pattern Either or both of waveform change and delay change by comparison can be displayed

Furthermore, when the portions of the pre-correction test pattern having the same timing are designated as a group and the pre-correction simulation result and the post-correction simulation result are compared, the waveform change and the waveform change of each portion of the same timing which is designated by the group and corrected. If it is possible to display whether delay changes are the same or not, it is possible to display waveform changes and delay changes by comparing the simulation results of the test patterns before and after correction for the same timing part of the pre-correction test patterns specified in the group. Can be displayed.

Further, if the change data extracted by comparing the pre-correction simulation result with the post-correction simulation result is aggregated at the same timing and the aggregated occurrence count is displayed, The number of occurrences of the same timing can be aggregated and displayed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 2 is a block diagram showing a configuration example of the logic circuit verification device according to the present invention. This logic circuit verification device comprises a keyboard device 1, a mouse 2, a screen display device 3, a storage device 4, and a data processing device 5.

The keyboard device 1 is an input device provided with various input keys, and inputs various operation instructions at the time of logic circuit verification. The mouse 2 is an input device for inputting position information of a mouse cursor displayed on the screen display device 3, and like the keyboard device 1, inputs various operation instructions at the time of logic circuit verification.

The screen display device 3 is a display device such as a CRT or LCD, and displays a test pattern, a simulation result, various messages and the like at the time of logic circuit verification. The storage device 4 is a memory such as a floppy disk device or a hard disk device, and stores various data such as a logic circuit, a test pattern, and a simulation result.

The data processing device 5 includes a CPU, ROM, RA
A microcomputer including M and the like is built in to control the entire logic circuit verification device and execute various processes related to the logic circuit verification.

FIG. 1 is a block diagram showing the functions of the logic circuit verification device shown in FIG. This logic circuit verification device
Test pattern input / correction means 10, test pattern data holding means 11, test pattern correction position holding means 1
2, the simulation executing means 13, the simulation result holding means 14, the re-simulation result / pre-simulation result change data extracting means 15, and the re-simulation result waveform / change data display means 16 are provided.

Further, change data extraction signal name designating means 1
7, a delay change / waveform change classification designating means 18, a group designation / correction supporting grouping extraction setting means 19, a change data totaling means 20, and a totaling result displaying means 21 are also provided.

The test pattern input / correction means 10 has a function of creating a test pattern for simulating a logic circuit, and inputs or corrects a test pattern for simulating a logic circuit such as an ASIC or a printed circuit board. The test pattern holding unit 11 holds the test pattern input or corrected by the test pattern input / correction unit 10.

The test pattern correction position holding means 12 is
The function of holding the correction position of the test pattern by the test pattern input / correction means 10 and holding the position of the correction of the test pattern is held.

The simulation executing means 13 has a function of executing the simulation of the logic circuit by the test pattern data held in the test pattern data holding means 11. The simulation result holding means 14 has a function of holding the simulation result by the simulation executing means 13.

The re-simulation result / pre-simulation result change data extracting means 15 has a function of comparing the result of re-simulation (corrected simulation result) with the result of previous simulation (pre-correction simulation result) to extract change data. .

That is, the pre-correction simulation result obtained by simulating the data of the pre-correction test pattern held in the test pattern data holding means 11 corresponding to the above-mentioned pre- and post-correction simulation result change data extracting means and the test pattern correction position holding Based on the correction position of the test pattern held in the means 12, the data of the pre-correction test pattern is corrected and the data of the post-correction test pattern is simulated, and the post-correction simulation result is compared to extract the changed data.

The re-simulation result waveform / change data display means 16 has a function of displaying the waveform of the re-simulation result (corrected simulation result) and the change data.

That is, it corresponds to the above-mentioned re-simulation result waveform / change data display means, and is a waveform based on the change data extracted by the re-simulation result / pre-simulation result change data extracting means 15 with respect to the waveform of the corrected simulation result. Show changes and delay changes.

The change data extraction signal name designating means 17 has a function of designating a signal name for extracting change data. In other words, the re-simulation result / pre-simulation result change data extracting unit 15 specifies the test pattern for extracting the change data, which corresponds to the change data extracting test pattern specifying unit described above.

Delay change / waveform change classification designation means 1
A function 8 is a function of separately extracting a change part which is not a delay difference and a part where the waveform is changed, and selecting either one or both of them.

That is, it corresponds to the above-mentioned waveform change / delay change extraction specifying means, and specifies that either the waveform change or the delay change or both are extracted by the re-simulation result / pre-simulation result change data extracting means 15. .

The group designation correction correspondence grouping extraction setting means 19 designates whether or not the portion corrected by the group is directly subjected to the data extraction by the group. That is, the same timing portion group designating / correcting means for designating and modifying the same timing portion of the pre-correction test pattern described above, and the group designating and modifying when the pre-correction simulation result and the post-correction simulation result are compared. It corresponds to the in-group same-timing partial change status display means for distinguishably displaying whether or not the waveform change and the delay change of each part at the same timing are the same.

The change data totaling means 20 performs the function of totaling the change data, that is, the re-simulation result / pre-simulation result change data extracting means 1
The number of occurrences of the change data extracted by 5 is counted at the same timing. The aggregation result display means 21 fulfills the function of displaying the aggregation result, that is, displays the number of occurrences aggregated by the change data aggregation means 20.

Next, the operation between the respective means shown in FIG. 1 will be described. The test pattern input / correction means 10 inputs or corrects a test pattern for simulating a logic circuit, and the input test pattern data is held in the test pattern data holding means 11.
The correction position of the corrected test pattern is held in the test pattern correction position holding means 12.

Thereafter, the simulation executing means 13 executes the simulation of the logic circuit by the data of the test pattern held in the test pattern data holding means 11, and holds the simulation result in the simulation result holding means 14.

Further, the re-simulation result / pre-simulation result change data extraction means 15 simulates the pre-correction test pattern data held in the test pattern data holding means 11 and the pre-correction simulation result and the test pattern correction position holding. Based on the correction position of the test pattern held in the means 12, the data of the pre-correction test pattern is corrected and the data of the post-correction test pattern is simulated, and the post-correction simulation result is compared to extract the changed data.

Then, based on the extracted change data, the waveform change and delay change for the corrected simulation result waveform are displayed on the re-simulation result waveform / change data display means 16. In this way, the waveform change and delay change between the pre-correction simulation result and the post-correction simulation result of the test pattern are displayed.

Further, change data extraction signal name designating means 17
The re-simulation result / pre-simulation result change data extraction means 15 specifies a test pattern for extracting change data, and only the specified test pattern is subjected to waveform change and delay change by comparing the simulation results of before and after correction test patterns. indicate.

Further, the delay change / waveform change classification designating unit 18 designates to extract either or both of the waveform change and the delay change by the re-simulation result / pre-simulation result change data extracting unit 15, and the pre-correction test and the post-correction test are performed. Either or both of the waveform change and the delay change are displayed by comparing the pattern simulation results.

Furthermore, the group designation correction correspondence grouping extraction setting means 19 designates a group at the same timing part of the pre-correction test pattern and designates the group when comparing the pre-correction simulation result and the post-correction simulation result. It is possible to distinguish whether or not the waveform changes and delay changes of each part of the same timing corrected by The waveform change and delay change by comparison are displayed.

Further, the number of occurrences of the change data extracted by the change data totalizing means 20 by the re-simulation result / pre-simulation result change data extracting means 15 is totaled at the same timing, and the totaled number of occurrences is displayed as a totalized result. It is displayed by the means 21.
In this way, the number of occurrences of the same timing is totaled and displayed.

3 to 6 are flowcharts showing the processing in this logic circuit verification device. As shown in FIG. 3, it is checked whether the test pattern is input, and YES.
If so, the test pattern input process is performed, and if NO, the process directly proceeds to a process of checking (determining) whether or not the test pattern is corrected.

In the process of checking whether or not the test pattern is corrected, if NO, the process branches to the process shown in FIG. 4, but if YES, the test pattern correction process is performed,
The process of storing the corrected portion is performed, and the process proceeds to the process of checking whether or not the simulation is executed.

In the processing of FIG. 4, first, it is checked whether or not the test pattern group is designated and corrected, and if YES, the group designated correction and the group correction position storage processing are performed.
If NO, the process proceeds directly to the process of checking whether the change data extraction signal name is designated. In the process of checking whether or not the change data extraction signal name is designated, if YES, the signal name to be extracted is designated, and if NO, the process proceeds to the process of checking whether or not the extraction designation is made by dividing the delay change and the waveform change.

In the process of checking whether or not the extraction designation is made by the division of the delay change and the waveform change, it is checked whether the change due to the delay and the change in which the waveform is changed are specified and one or both of them are specified. Then, if YES, the extraction method by the division of the delay change and the waveform change is designated, and if NO, the process proceeds to the process of checking whether or not the grouped correction is processed as a group.

Then, it is checked whether or not the grouping-corrected portion is extracted by a group. If YES, the grouping extraction flag is turned ON, and if NO, the process proceeds to the process of checking whether or not the aggregation designation of change data is specified. . In the process of checking whether or not the change data is specified to be totaled, if YES, the totalization designation flag is turned ON, and NO
If so, the process returns to that of FIG.

Next, returning to FIG. 3, it is checked whether or not the simulation is executed. If NO, the process returns to the first process, but YE.
If S, it is checked whether or not there is previous simulation data. If YES, the previous simulation data is moved and stored in another area, and if NO, the process directly proceeds to the simulation execution process.

Therefore, a simulation is executed to check whether or not there is previous simulation data that has been moved and stored. If NO, the process branches to the process shown in FIG. 6, and if YES, the change data extraction signal name is designated. Check if there is, and if NO, target all signals and specify Y
If it is ES, the process directly proceeds to the process shown in FIG.

In the processing of FIG. 5, it is first checked whether or not extraction designation by delay change and waveform change classification has been made. If NO, both delay change and waveform change are designated as extraction, and if YES, the group designation correction group is directly accepted. Then, the process proceeds to the process of checking whether or not there is a chemical extraction setting.

In checking whether or not there is a grouping extraction setting corresponding to the group designation correction, if YES, the group is set as an extraction target, and if NO, it is set using the previous simulation result data and the re-simulation result data as it is. The change (difference) data is analyzed under the conditions.

Next, it is checked whether or not there is a test pattern correction portion. If YES, the test pattern correction portion is highlighted, and if NO, the process proceeds as it is and FIG.
The processing shifts to the processing shown in.

In the process of FIG. 6, the result of re-simulation is first displayed to check whether or not there is change (difference) data. If NO, the process ends. Also,
If YES, change (difference) data is highlighted on the waveform, check whether change (difference) data is totaled, if NO, end this process as it is, if YES, change (difference) data are totaled Then, the totalized result is displayed, and this processing ends. That is, it is checked whether or not a flag for totaling change (difference) data is set, and the flag is turned on.
Then, the change (difference) data is totaled and the totalized result is displayed.

Next, a display example of the simulation result in this logic circuit verification device will be described. 7 and 8 are diagrams showing an example of a screen displaying the simulation result of a certain logic circuit.

FIG. 7 is a diagram showing a display example of the simulation result by the pre-correction test pattern, FIG. 8 is a diagram showing a display example of the simulation result by the post-correction test pattern, and FIG. 8 is a simulation result by the pre-correction test pattern. The comparison result of is displayed.

On these screens 30, input signals IN1, IN2, and IN2 are obtained as a result of simulating a certain logic circuit with a test pattern before or after correction.
Test signal TEST, clock signal CLK, output signal O
Waveforms W1 to W of UT1, OUT2, and OUT3, respectively
7 is displayed.

In the display example shown in FIG. 8, the waveform 31 indicating the test pattern changing position (corrected portion) is displayed in a different color on the input waveform W2. Also, the output waveform W
In FIG. 5, a simulation result before modification and a simulation result after modification are compared, and a waveform 32 indicating a portion where the waveform has changed is displayed in a different color.

Further, in the output waveform W6, the waveform 33 showing the portion where the delay has changed is displayed in a different color by comparing the simulation result before the correction and the simulation result after the correction. Therefore, it is possible to easily compare the simulation results before and after the modification with respect to the part changed by the modification of the test pattern or the modification of the logic circuit.

Next, FIGS. 9 and 10 are views showing an example of a display screen when a signal for comparing the simulation results before and after the test pattern correction is designated. FIG. 9 is a diagram showing an example of a display screen when a signal is not designated,
FIG. 10 is a diagram showing an example of a display screen when a signal is designated.

As shown in FIG. 9, if no signal is specified, the simulation results before and after the modification are compared for all the signals, that is, the waveform 32 which is the waveform change and the delay change,
33 and 35 are displayed.

For example, when the input signal IN1 is designated in advance, as shown in FIG. 10, except for the waveform 35 which is the waveform change and the delay change due to the comparison of the simulation results before and after the test pattern correction with respect to the input signal IN1,
Only waveforms 32 and 33 are displayed. Therefore, the signals for analyzing the change in the simulation result before and after the modification can be limited to a part of the signals for comparison.

Next, FIGS. 11 and 12 are views showing an example of a display screen when designation is made to display either one or both of the waveform change and the delay change. For example, when only the waveform change is designated to be displayed in advance, only the waveform 32 indicating the changed waveform portion of the waveform W5 is displayed as shown in FIG.

When it is designated to display only the delay change, as shown in FIG. 12, only the waveform 33 showing the delay change portion of the waveform W6 is displayed. Alternatively, when it is designated to display both the waveform change and the delay change, the display is as shown in FIG.

Next, FIG. 13 is a diagram showing an example of a display screen when the waveform change and the delay change of each portion of the group-designated same timing are discriminatively displayed. Screen 3
6 shows waveforms W10, W11, W1 as simulation results of the input signals I1, I2 and the output signal O1.
2 is displayed.

The waveform portions 37, 38 of the waveform W10 are designated as a group at the same timing, and how the simulation result after changing the waveform portions 37, 38 as a group changes the waveform portion of the waveform W12. 39 and 40 are displayed in differently distinguishable colors (hatched portions in the figure).

If there is a difference in the change in the waveform portions 37 and 38, the changed portion is displayed in a different color. For example, when the delay difference between the waveform portions 37 and 38 is different,
As shown in FIG. 14, the waveform of the uncorrected simulation result shown by the shaded portion 42 is displayed in a different color from the simulation result shown by the solid line 41 of the waveform portion 40, and the waveform portion 39 shown by the cross hatched portion 43 is displayed. Display the simulation result waveform in different colors.

Next, FIG. 15 is a diagram showing an example of a screen when the number of occurrences of the same timing of the simulation result is displayed. On the screen 50, the waveform of the pattern having the same timing and the number of times of occurrence “12” are displayed.

Next, the effects of the logic circuit verification device of this embodiment will be listed. (1) By checking the waveform between the previous simulation result and the re-simulation result and analyzing how the waveform changed from the previous one, how much the delay was different from the previous one and where the waveform changed Can be extracted, and it is possible to eliminate the troublesome work visually observed by the operator.

(2) By making it possible to specify the signal for waveform check, it becomes possible to narrow down the extracted data and make it the data that one really wants to see, and it is possible to eliminate the complicated work by the operator.

(3) There is a change in the analyzed data only when the delay is changed and a change in the mutual relationship of the waveforms, and it is specified that either one or both of them are displayed separately. By making it possible, it becomes possible to further narrow down the extracted data and make it the data that you really want to see. Therefore, it is possible to eliminate complicated work by the operator.

(4) By making it possible to capture the data to be analyzed as a group, it is possible to check whether all the changes are the same when the same timing exists many times at different real times. It becomes possible to check whether the same result is obtained with all inputs at the same timing, so that oversight can be eliminated and the operator can make an accurate judgment.

(5) By making it possible to aggregate a large amount of change data extracted by, for example, arranging delay changes together in the order of maximum change, it is possible to eliminate complicated operations by the operator.

[0077]

As described above, the logic circuit verification device according to the present invention has the following effects. (1) Since it is possible to extract a portion where the delay change and the waveform are changed in the post-correction simulation result from the pre-correction simulation result, it is possible to eliminate complicated operations by the operator.

(2) Since the signal name to display the waveform change and delay change by comparing the simulation results before and after the modification can be specified, the extracted data can be narrowed down and the operator's complicated work can be eliminated. (3) Since it is possible to select and extract the portion where the delay has changed and the portion where the waveform has changed, the data can be further narrowed down and the operator's complicated work can be eliminated.

(4) By easily identifying whether the same change occurs for the input at the same timing by specifying the group, human error such as oversight or check mistake can be eliminated.

(5) Conventionally, it becomes possible to compile a large amount of change data that has been produced for each item such as delay.
As a result, since it becomes possible to see in the group, it becomes possible to easily catch the abnormal point, so that human error such as oversight or check mistake is eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing functions of the logic circuit verification device shown in FIG.

FIG. 2 is a block diagram showing a configuration example of a logic circuit verification device according to the present invention.

FIG. 3 is a flowchart showing a process in this logic circuit verification device.

FIG. 4 is a flowchart showing the subsequent processing.

FIG. 5 is a flow chart showing the further processing.

FIG. 6 is a flowchart showing the subsequent processing.

FIG. 7 is a diagram showing a display example of a simulation result by an uncorrected test pattern.

FIG. 8 is a diagram showing a display example of simulation results by a corrected test pattern.

FIG. 9 is a diagram showing an example of a display screen when a signal is not designated.

FIG. 10 is a diagram showing an example of a display screen when a signal is designated.

FIG. 11 is a diagram showing an example of a display screen when designation is made to display only waveform changes.

FIG. 12 is a diagram showing an example of a display screen when designation is made to display only delay changes.

FIG. 13 is a diagram showing an example of a display screen when a waveform change and a delay change of each portion of a group designated same timing are discriminatively displayed.

FIG. 14 is an explanatory diagram when the display is made so as to be discriminable.

FIG. 15 is a diagram showing an example of a screen when the number of occurrences of the same timing of the simulation result is displayed.

[Explanation of symbols]

1 keyboard device 2 mouse 3 screen display device 4 storage device 5 data processing device 10 test pattern input / correction means 11 test pattern data holding means 12 test pattern correction position holding means 13 simulation execution means 14 simulation result holding means 15 re-simulation result Pre-simulation result change data extraction means 16 Re-simulation result waveform / change data display means 17 Change data extraction signal name designation means 18 Delay change / waveform change classification designation means 19 Group designation correction correspondence grouping extraction setting means 20 Change data totaling means 21 Total result display means

Claims (5)

[Claims] 1. A test pattern input / correction means for inputting or modifying a test pattern for simulating a logic circuit such as an ASIC, and a test pattern data holding means for holding data of the test pattern input or modified by the means. And a test pattern correction position holding means for holding the correction position of the test pattern by the test pattern input / correction means, and the data of the test pattern held in the test pattern data holding means for executing the simulation of the logic circuit. The simulation executing means, the simulation result holding means for holding the simulation result by the means, and the data of the uncorrected test pattern held in the test pattern data holding means are simulated by the simulation executing means. The corrected pre-correction test pattern data based on the corrected pre-correction simulation result and the correction position of the test pattern held in the test pattern correction position holding means by the simulation executing means. Pre- and post-correction simulation result change data extracting means for extracting changed data by comparing the simulated post-correction simulation result, and changes extracted by the pre- and post-correction simulation result change data extracting means for the waveform of the post-correction simulation result A logic circuit verification device comprising: modified simulation result change status display means for displaying waveform change and delay change based on data. 2. The logic circuit verification apparatus according to claim 1, further comprising change data extraction test pattern designating means for designating a test pattern for extracting change data by said pre- and post-correction simulation result change data extracting means. Logic circuit verification device. 3. The logic circuit verification apparatus according to claim 1, wherein the waveform change / delay is designated by the pre / post-correction simulation result change data extracting means so as to extract either one or both of the waveform change and the delay change. A logic circuit verification device characterized by comprising change extraction designating means. 4. The logic circuit verification apparatus according to claim 1, further comprising: same timing portion group designation / correction means that designates and corrects portions of the pre-correction test pattern at the same timing by group. When comparing the pre-correction simulation result with the post-correction simulation result, it is possible to determine whether or not the waveform change and the delay change of each part of the same timing corrected by the group designation by the same timing portion group designation correcting means are the same. A logic circuit verification device, characterized in that a display unit for displaying the same timing partial change status in a group is provided. 5. The logic circuit verification device according to claim 1, wherein the change data extracted by the before / after correction simulation result change data extracting means is a change data for totaling the number of occurrences thereof at the same timing. A logic circuit verifying device comprising: a totaling means and totaling result display means for displaying the number of occurrences totaled by the means.